40 lines
1.1 KiB
C
40 lines
1.1 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2022, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H
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#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H
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/* Clocks */
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#define DISP_CC_PLL0 0
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#define DISP_CC_PLL0_OUT_MAIN 1
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#define DISP_CC_MDSS_AHB_CLK 2
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#define DISP_CC_MDSS_AHB_CLK_SRC 3
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#define DISP_CC_MDSS_BYTE0_CLK 4
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#define DISP_CC_MDSS_BYTE0_CLK_SRC 5
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#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6
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#define DISP_CC_MDSS_BYTE0_INTF_CLK 7
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#define DISP_CC_MDSS_ESC0_CLK 8
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#define DISP_CC_MDSS_ESC0_CLK_SRC 9
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#define DISP_CC_MDSS_MDP_CLK 10
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#define DISP_CC_MDSS_MDP_CLK_SRC 11
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#define DISP_CC_MDSS_MDP_LUT_CLK 12
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#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 13
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#define DISP_CC_MDSS_PCLK0_CLK 14
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#define DISP_CC_MDSS_PCLK0_CLK_SRC 15
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#define DISP_CC_MDSS_ROT_CLK 16
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#define DISP_CC_MDSS_ROT_CLK_SRC 17
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#define DISP_CC_MDSS_VSYNC_CLK 18
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#define DISP_CC_MDSS_VSYNC_CLK_SRC 19
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#define DISP_CC_SLEEP_CLK 20
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#define DISP_CC_SLEEP_CLK_SRC 21
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/* Resets */
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#define DISP_CC_MDSS_CORE_BCR 0
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/* GDSCs */
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#define MDSS_GDSC 0
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#endif
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