221 lines
5.4 KiB
C
221 lines
5.4 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
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/*
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* Copyright (c) 2024 Rockchip Electronics Co. Ltd.
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* Author: Elaine Zhang <zhangqing@rock-chips.com>
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*/
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#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H
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#define _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H
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#define PLL_GPLL 0
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#define ARMCLK 1
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#define PLL_DPLL 2
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#define XIN_OSC0_HALF 3
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#define CLK_GPLL_DIV24 4
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#define CLK_GPLL_DIV12 5
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#define CLK_GPLL_DIV6 6
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#define CLK_GPLL_DIV4 7
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#define CLK_GPLL_DIV3 8
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#define CLK_GPLL_DIV2P5 9
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#define CLK_GPLL_DIV2 10
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#define CLK_UART0_SRC 11
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#define CLK_UART1_SRC 12
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#define CLK_UART2_SRC 13
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#define CLK_UART0_FRAC 14
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#define CLK_UART1_FRAC 15
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#define CLK_UART2_FRAC 16
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#define CLK_SAI_SRC 17
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#define CLK_SAI_FRAC 18
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#define LSCLK_NPU_SRC 19
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#define CLK_NPU_SRC 20
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#define ACLK_VEPU_SRC 21
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#define CLK_VEPU_SRC 22
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#define ACLK_VI_SRC 23
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#define CLK_ISP_SRC 24
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#define DCLK_VICAP 25
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#define CCLK_EMMC 26
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#define CCLK_SDMMC0 27
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#define SCLK_SFC_2X 28
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#define LSCLK_PERI_SRC 29
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#define ACLK_PERI_SRC 30
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#define HCLK_HPMCU 31
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#define SCLK_UART0 32
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#define SCLK_UART1 33
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#define SCLK_UART2 34
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#define CLK_I2C_PMU 35
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#define CLK_I2C_PERI 36
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#define CLK_SPI0 37
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#define CLK_PWM0_SRC 38
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#define CLK_PWM1 39
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#define CLK_PWM2 40
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#define DCLK_DECOM_SRC 41
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#define CCLK_SDMMC1 42
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#define CLK_CORE_CRYPTO 43
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#define CLK_PKA_CRYPTO 44
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#define CLK_CORE_RGA 45
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#define MCLK_SAI_SRC 46
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#define CLK_FREQ_PWM0_SRC 47
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#define CLK_COUNTER_PWM0_SRC 48
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#define PCLK_TOP_ROOT 49
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#define CLK_REF_MIPI0 50
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#define CLK_MIPI0_OUT2IO 51
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#define CLK_REF_MIPI1 52
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#define CLK_MIPI1_OUT2IO 53
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#define MCLK_SAI_OUT2IO 54
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#define ACLK_NPU_ROOT 55
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#define HCLK_RKNN 56
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#define ACLK_RKNN 57
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#define LSCLK_VEPU_ROOT 58
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#define HCLK_VEPU 59
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#define ACLK_VEPU 60
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#define CLK_CORE_VEPU 61
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#define PCLK_IOC_VCCIO3 62
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#define PCLK_ACODEC 63
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#define PCLK_USBPHY 64
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#define LSCLK_VI_100M 65
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#define LSCLK_VI_ROOT 66
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#define HCLK_ISP 67
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#define ACLK_ISP 68
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#define CLK_CORE_ISP 69
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#define ACLK_VICAP 70
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#define HCLK_VICAP 71
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#define ISP0CLK_VICAP 72
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#define PCLK_CSI2HOST0 73
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#define PCLK_CSI2HOST1 74
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#define HCLK_EMMC 75
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#define HCLK_SFC 76
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#define HCLK_SFC_XIP 77
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#define HCLK_SDMMC0 78
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#define PCLK_CSIPHY 79
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#define PCLK_GPIO1 80
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#define DBCLK_GPIO1 81
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#define PCLK_IOC_VCCIO47 82
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#define LSCLK_DDR_ROOT 83
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#define CLK_TIMER_DDRMON 84
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#define LSCLK_PMU_ROOT 85
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#define PCLK_PMU 86
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#define XIN_RC_DIV 87
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#define CLK_32K 88
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#define PCLK_PMU_GPIO0 89
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#define DBCLK_PMU_GPIO0 90
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#define CLK_DDR_FAIL_SAFE 91
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#define PCLK_PMU_HP_TIMER 92
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#define CLK_PMU_32K_HP_TIMER 93
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#define PCLK_PWM0 94
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#define CLK_PWM0 95
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#define CLK_OSC_PWM0 96
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#define CLK_RC_PWM0 97
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#define CLK_FREQ_PWM0 98
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#define CLK_COUNTER_PWM0 99
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#define PCLK_I2C0 100
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#define CLK_I2C0 101
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#define PCLK_UART0 102
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#define PCLK_IOC_PMUIO0 103
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#define CLK_REFOUT 104
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#define CLK_PREROLL 105
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#define CLK_PREROLL_32K 106
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#define CLK_LPMCU_PMU 107
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#define PCLK_SPI2AHB 108
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#define HCLK_SPI2AHB 109
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#define SCLK_SPI2AHB 110
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#define PCLK_WDT_LPMCU 111
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#define TCLK_WDT_LPMCU 112
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#define HCLK_SFC_PMU1 113
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#define HCLK_SFC_XIP_PMU1 114
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#define SCLK_SFC_2X_PMU1 115
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#define CLK_LPMCU 116
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#define CLK_LPMCU_RTC 117
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#define PCLK_LPMCU_MAILBOX 118
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#define PCLK_IOC_PMUIO1 119
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#define PCLK_CRU_PMU1 120
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#define PCLK_PERI_ROOT 121
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#define PCLK_RTC_ROOT 122
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#define CLK_TIMER_ROOT 123
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#define PCLK_TIMER 124
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#define CLK_TIMER0 125
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#define CLK_TIMER1 126
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#define CLK_TIMER2 127
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#define CLK_TIMER3 128
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#define CLK_TIMER4 129
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#define CLK_TIMER5 130
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#define PCLK_STIMER 131
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#define CLK_STIMER0 132
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#define CLK_STIMER1 133
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#define PCLK_WDT_NS 134
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#define TCLK_WDT_NS 135
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#define PCLK_WDT_S 136
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#define TCLK_WDT_S 137
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#define PCLK_WDT_HPMCU 138
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#define TCLK_WDT_HPMCU 139
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#define PCLK_I2C1 140
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#define CLK_I2C1 141
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#define PCLK_I2C2 142
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#define CLK_I2C2 143
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#define PCLK_I2C3 144
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#define CLK_I2C3 145
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#define PCLK_I2C4 146
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#define CLK_I2C4 147
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#define PCLK_SPI0 148
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#define PCLK_PWM1 149
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#define CLK_OSC_PWM1 150
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#define PCLK_PWM2 151
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#define CLK_OSC_PWM2 152
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#define PCLK_UART2 153
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#define PCLK_UART1 154
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#define ACLK_RKDMA 155
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#define PCLK_TSADC 156
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#define CLK_TSADC 157
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#define CLK_TSADC_TSEN 158
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#define PCLK_SARADC 159
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#define CLK_SARADC 160
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#define PCLK_GPIO2 161
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#define DBCLK_GPIO2 162
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#define PCLK_IOC_VCCIO6 163
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#define ACLK_USBOTG 164
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#define CLK_REF_USBOTG 165
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#define HCLK_SDMMC1 166
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#define HCLK_SAI 167
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#define MCLK_SAI 168
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#define ACLK_CRYPTO 169
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#define HCLK_CRYPTO 170
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#define HCLK_RK_RNG_NS 171
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#define HCLK_RK_RNG_S 172
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#define PCLK_OTPC_NS 173
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#define CLK_OTPC_ROOT_NS 174
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#define CLK_SBPI_OTPC_NS 175
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#define CLK_USER_OTPC_NS 176
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#define PCLK_OTPC_S 177
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#define CLK_OTPC_ROOT_S 178
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#define CLK_SBPI_OTPC_S 179
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#define CLK_USER_OTPC_S 180
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#define CLK_OTPC_ARB 181
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#define PCLK_OTP_MASK 182
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#define HCLK_RGA 183
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#define ACLK_RGA 184
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#define ACLK_MAC 185
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#define PCLK_MAC 186
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#define CLK_MACPHY 187
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#define ACLK_SPINLOCK 188
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#define HCLK_CACHE 189
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#define PCLK_HPMCU_MAILBOX 190
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#define PCLK_HPMCU_INTMUX 191
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#define CLK_HPMCU 192
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#define CLK_HPMCU_RTC 193
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#define DCLK_DECOM 194
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#define ACLK_DECOM 195
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#define PCLK_DECOM 196
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#define ACLK_SYS_SRAM 197
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#define PCLK_DMA2DDR 198
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#define ACLK_DMA2DDR 199
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#define PCLK_DCF 200
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#define ACLK_DCF 201
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#define MCLK_ACODEC_TX 202
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#define SCLK_UART0_SRC 203
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#define SCLK_UART1_SRC 204
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#define SCLK_UART2_SRC 205
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#define XIN_RC_SRC 206
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#define CLK_UTMI_USBOTG 207
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#define CLK_REF_USBPHY 208
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#endif // _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H
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