128 lines
4.3 KiB
C
128 lines
4.3 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#ifndef _DT_BINDINGS_RESET_IPQ_GCC_IPQ5210_H
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#define _DT_BINDINGS_RESET_IPQ_GCC_IPQ5210_H
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#define GCC_ADSS_BCR 0
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#define GCC_ADSS_PWM_ARES 1
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#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 2
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#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_ARES 3
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#define GCC_APSS_AHB_ARES 4
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#define GCC_APSS_ATB_ARES 5
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#define GCC_APSS_AXI_ARES 6
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#define GCC_APSS_TS_ARES 7
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#define GCC_BOOT_ROM_AHB_ARES 8
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#define GCC_BOOT_ROM_BCR 9
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#define GCC_GEPHY_BCR 10
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#define GCC_GEPHY_SYS_ARES 11
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#define GCC_GP1_ARES 12
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#define GCC_GP2_ARES 13
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#define GCC_GP3_ARES 14
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#define GCC_MDIO_AHB_ARES 15
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#define GCC_MDIO_BCR 16
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#define GCC_MDIO_GEPHY_AHB_ARES 17
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#define GCC_NSS_BCR 18
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#define GCC_NSS_TS_ARES 19
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#define GCC_NSSCC_ARES 20
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#define GCC_NSSCFG_ARES 21
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#define GCC_NSSNOC_ATB_ARES 22
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#define GCC_NSSNOC_MEMNOC_1_ARES 23
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#define GCC_NSSNOC_MEMNOC_ARES 24
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#define GCC_NSSNOC_NSSCC_ARES 25
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#define GCC_NSSNOC_PCNOC_1_ARES 26
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#define GCC_NSSNOC_QOSGEN_REF_ARES 27
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#define GCC_NSSNOC_SNOC_1_ARES 28
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#define GCC_NSSNOC_SNOC_ARES 29
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#define GCC_NSSNOC_TIMEOUT_REF_ARES 30
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#define GCC_NSSNOC_XO_DCD_ARES 31
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#define GCC_PCIE0_AHB_ARES 32
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#define GCC_PCIE0_AUX_ARES 33
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#define GCC_PCIE0_AXI_M_ARES 34
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#define GCC_PCIE0_AXI_S_BRIDGE_ARES 35
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#define GCC_PCIE0_AXI_S_ARES 36
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#define GCC_PCIE0_BCR 37
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#define GCC_PCIE0_LINK_DOWN_BCR 38
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#define GCC_PCIE0_PHY_BCR 39
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#define GCC_PCIE0_PIPE_ARES 40
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#define GCC_PCIE0PHY_PHY_BCR 41
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#define GCC_PCIE1_AHB_ARES 42
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#define GCC_PCIE1_AUX_ARES 43
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#define GCC_PCIE1_AXI_M_ARES 44
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#define GCC_PCIE1_AXI_S_BRIDGE_ARES 45
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#define GCC_PCIE1_AXI_S_ARES 46
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#define GCC_PCIE1_BCR 47
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#define GCC_PCIE1_LINK_DOWN_BCR 48
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#define GCC_PCIE1_PHY_BCR 49
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#define GCC_PCIE1_PIPE_ARES 50
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#define GCC_PCIE1PHY_PHY_BCR 51
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#define GCC_QRNG_AHB_ARES 52
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#define GCC_QRNG_BCR 53
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#define GCC_QUPV3_2X_CORE_ARES 54
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#define GCC_QUPV3_AHB_MST_ARES 55
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#define GCC_QUPV3_AHB_SLV_ARES 56
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#define GCC_QUPV3_BCR 57
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#define GCC_QUPV3_CORE_ARES 58
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#define GCC_QUPV3_WRAP_SE0_ARES 59
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#define GCC_QUPV3_WRAP_SE0_BCR 60
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#define GCC_QUPV3_WRAP_SE1_ARES 61
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#define GCC_QUPV3_WRAP_SE1_BCR 62
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#define GCC_QUPV3_WRAP_SE2_ARES 63
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#define GCC_QUPV3_WRAP_SE2_BCR 64
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#define GCC_QUPV3_WRAP_SE3_ARES 65
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#define GCC_QUPV3_WRAP_SE3_BCR 66
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#define GCC_QUPV3_WRAP_SE4_ARES 67
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#define GCC_QUPV3_WRAP_SE4_BCR 68
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#define GCC_QUPV3_WRAP_SE5_ARES 69
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#define GCC_QUPV3_WRAP_SE5_BCR 70
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#define GCC_QUSB2_0_PHY_BCR 71
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#define GCC_SDCC1_AHB_ARES 72
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#define GCC_SDCC1_APPS_ARES 73
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#define GCC_SDCC1_ICE_CORE_ARES 74
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#define GCC_SDCC_BCR 75
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#define GCC_TLMM_AHB_ARES 76
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#define GCC_TLMM_ARES 77
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#define GCC_TLMM_BCR 78
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#define GCC_UNIPHY0_AHB_ARES 79
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#define GCC_UNIPHY0_BCR 80
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#define GCC_UNIPHY0_SYS_ARES 81
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#define GCC_UNIPHY1_AHB_ARES 82
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#define GCC_UNIPHY1_BCR 83
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#define GCC_UNIPHY1_SYS_ARES 84
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#define GCC_UNIPHY2_AHB_ARES 85
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#define GCC_UNIPHY2_BCR 86
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#define GCC_UNIPHY2_SYS_ARES 87
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#define GCC_USB0_AUX_ARES 88
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#define GCC_USB0_MASTER_ARES 89
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#define GCC_USB0_MOCK_UTMI_ARES 90
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#define GCC_USB0_PHY_BCR 91
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#define GCC_USB0_PHY_CFG_AHB_ARES 92
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#define GCC_USB0_PIPE_ARES 93
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#define GCC_USB0_SLEEP_ARES 94
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#define GCC_USB3PHY_0_PHY_BCR 95
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#define GCC_USB_BCR 96
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#define GCC_PCIE0_PIPE_RESET 97
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#define GCC_PCIE0_CORE_STICKY_RESET 98
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#define GCC_PCIE0_AXI_S_STICKY_RESET 99
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#define GCC_PCIE0_AXI_S_RESET 100
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#define GCC_PCIE0_AXI_M_STICKY_RESET 101
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#define GCC_PCIE0_AXI_M_RESET 102
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#define GCC_PCIE0_AUX_RESET 103
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#define GCC_PCIE0_AHB_RESET 104
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#define GCC_PCIE1_PIPE_RESET 105
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#define GCC_PCIE1_CORE_STICKY_RESET 106
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#define GCC_PCIE1_AXI_S_STICKY_RESET 107
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#define GCC_PCIE1_AXI_S_RESET 108
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#define GCC_PCIE1_AXI_M_STICKY_RESET 109
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#define GCC_PCIE1_AXI_M_RESET 110
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#define GCC_PCIE1_AUX_RESET 111
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#define GCC_PCIE1_AHB_RESET 112
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#define GCC_UNIPHY0_XPCS_ARES 113
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#define GCC_UNIPHY1_XPCS_ARES 114
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#define GCC_UNIPHY2_XPCS_ARES 115
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#define GCC_QDSS_BCR 116
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#endif
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