216 lines
8.0 KiB
C
216 lines
8.0 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#ifndef _DT_BINDINGS_RESET_IPQ_GCC_IPQ9650_H
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#define _DT_BINDINGS_RESET_IPQ_GCC_IPQ9650_H
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#define GCC_ADSS_BCR 0
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#define GCC_ADSS_PWM_CLK_ARES 1
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#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 2
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#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES 3
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#define GCC_APSS_AHB_CLK_ARES 4
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#define GCC_APSS_ATB_CLK_ARES 5
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#define GCC_APSS_AXI_CLK_ARES 6
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#define GCC_APSS_TS_CLK_ARES 7
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#define GCC_BOOT_ROM_AHB_CLK_ARES 8
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#define GCC_BOOT_ROM_BCR 9
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#define GCC_CMN_12GPLL_AHB_CLK_ARES 10
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#define GCC_CMN_12GPLL_APU_CLK_ARES 11
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#define GCC_CMN_12GPLL_SYS_CLK_ARES 12
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#define GCC_CMN_BLK_BCR 13
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#define GCC_CMN_LDO_CLK_ARES 14
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#define GCC_CPUSS_TRIG_CLK_ARES 15
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#define GCC_GP1_CLK_ARES 16
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#define GCC_GP2_CLK_ARES 17
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#define GCC_GP3_CLK_ARES 18
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#define GCC_MDIO_AHB_CLK_ARES 19
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#define GCC_MDIO_BCR 20
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#define GCC_NSSCC_CLK_ARES 21
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#define GCC_NSSCFG_CLK_ARES 22
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#define GCC_NSSNOC_ATB_CLK_ARES 23
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#define GCC_NSSNOC_MEMNOC_1_CLK_ARES 24
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#define GCC_NSSNOC_MEMNOC_CLK_ARES 25
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#define GCC_NSSNOC_NSSCC_CLK_ARES 26
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#define GCC_NSSNOC_PCNOC_1_CLK_ARES 27
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#define GCC_NSSNOC_QOSGEN_REF_CLK_ARES 28
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#define GCC_NSSNOC_SNOC_1_CLK_ARES 29
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#define GCC_NSSNOC_SNOC_CLK_ARES 30
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#define GCC_NSSNOC_TIMEOUT_REF_CLK_ARES 31
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#define GCC_NSSNOC_XO_DCD_CLK_ARES 32
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#define GCC_NSS_BCR 33
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#define GCC_NSS_TS_CLK_ARES 34
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#define GCC_PCIE0PHY_PHY_BCR 35
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#define GCC_PCIE0_AHB_CLK_ARES 36
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#define GCC_PCIE0_AHB_RESET 37
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#define GCC_PCIE0_AUX_CLK_ARES 38
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#define GCC_PCIE0_AUX_RESET 39
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#define GCC_PCIE0_AXI_M_CLK_ARES 40
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#define GCC_PCIE0_AXI_M_RESET 41
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#define GCC_PCIE0_AXI_M_STICKY_RESET 42
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#define GCC_PCIE0_AXI_S_BRIDGE_CLK_ARES 43
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#define GCC_PCIE0_AXI_S_CLK_ARES 44
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#define GCC_PCIE0_AXI_S_RESET 45
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#define GCC_PCIE0_AXI_S_STICKY_RESET 46
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#define GCC_PCIE0_BCR 47
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#define GCC_PCIE0_CORE_STICKY_RESET 48
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#define GCC_PCIE0_LINK_DOWN_BCR 49
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#define GCC_PCIE0_PHY_BCR 50
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#define GCC_PCIE0_PIPE_CLK_ARES 51
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#define GCC_PCIE0_PIPE_RESET 52
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#define GCC_PCIE1PHY_PHY_BCR 53
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#define GCC_PCIE1_AHB_CLK_ARES 54
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#define GCC_PCIE1_AHB_RESET 55
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#define GCC_PCIE1_AUX_CLK_ARES 56
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#define GCC_PCIE1_AUX_RESET 57
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#define GCC_PCIE1_AXI_M_CLK_ARES 58
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#define GCC_PCIE1_AXI_M_RESET 59
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#define GCC_PCIE1_AXI_M_STICKY_RESET 60
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#define GCC_PCIE1_AXI_S_BRIDGE_CLK_ARES 61
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#define GCC_PCIE1_AXI_S_CLK_ARES 62
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#define GCC_PCIE1_AXI_S_RESET 63
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#define GCC_PCIE1_AXI_S_STICKY_RESET 64
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#define GCC_PCIE1_BCR 65
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#define GCC_PCIE1_CORE_STICKY_RESET 66
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#define GCC_PCIE1_LINK_DOWN_BCR 67
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#define GCC_PCIE1_PHY_BCR 68
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#define GCC_PCIE1_PIPE_CLK_ARES 69
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#define GCC_PCIE1_PIPE_RESET 70
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#define GCC_PCIE2PHY_PHY_BCR 71
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#define GCC_PCIE2_AHB_CLK_ARES 72
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#define GCC_PCIE2_AHB_RESET 73
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#define GCC_PCIE2_AUX_CLK_ARES 74
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#define GCC_PCIE2_AUX_RESET 75
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#define GCC_PCIE2_AXI_M_CLK_ARES 76
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#define GCC_PCIE2_AXI_M_RESET 77
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#define GCC_PCIE2_AXI_M_STICKY_RESET 78
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#define GCC_PCIE2_AXI_S_BRIDGE_CLK_ARES 79
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#define GCC_PCIE2_AXI_S_CLK_ARES 80
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#define GCC_PCIE2_AXI_S_RESET 81
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#define GCC_PCIE2_AXI_S_STICKY_RESET 82
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#define GCC_PCIE2_BCR 83
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#define GCC_PCIE2_CORE_STICKY_RESET 84
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#define GCC_PCIE2_LINK_DOWN_BCR 85
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#define GCC_PCIE2_PHY_BCR 86
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#define GCC_PCIE2_PIPE_CLK_ARES 87
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#define GCC_PCIE2_PIPE_RESET 88
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#define GCC_PCIE3PHY_PHY_BCR 89
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#define GCC_PCIE3_AHB_CLK_ARES 90
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#define GCC_PCIE3_AHB_RESET 91
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#define GCC_PCIE3_AUX_CLK_ARES 92
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#define GCC_PCIE3_AUX_RESET 93
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#define GCC_PCIE3_AXI_M_CLK_ARES 94
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#define GCC_PCIE3_AXI_M_RESET 95
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#define GCC_PCIE3_AXI_M_STICKY_RESET 96
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#define GCC_PCIE3_AXI_S_BRIDGE_CLK_ARES 97
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#define GCC_PCIE3_AXI_S_CLK_ARES 98
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#define GCC_PCIE3_AXI_S_RESET 99
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#define GCC_PCIE3_AXI_S_STICKY_RESET 100
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#define GCC_PCIE3_BCR 101
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#define GCC_PCIE3_CORE_STICKY_RESET 102
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#define GCC_PCIE3_LINK_DOWN_BCR 103
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#define GCC_PCIE3_PHY_BCR 104
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#define GCC_PCIE3_PIPE_CLK_ARES 105
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#define GCC_PCIE3_PIPE_RESET 106
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#define GCC_PCIE4PHY_PHY_BCR 107
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#define GCC_PCIE4_AHB_CLK_ARES 108
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#define GCC_PCIE4_AHB_RESET 109
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#define GCC_PCIE4_AUX_CLK_ARES 110
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#define GCC_PCIE4_AUX_RESET 111
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#define GCC_PCIE4_AXI_M_CLK_ARES 112
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#define GCC_PCIE4_AXI_M_RESET 113
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#define GCC_PCIE4_AXI_M_STICKY_RESET 114
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#define GCC_PCIE4_AXI_S_BRIDGE_CLK_ARES 115
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#define GCC_PCIE4_AXI_S_CLK_ARES 116
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#define GCC_PCIE4_AXI_S_RESET 117
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#define GCC_PCIE4_AXI_S_STICKY_RESET 118
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#define GCC_PCIE4_BCR 119
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#define GCC_PCIE4_CORE_STICKY_RESET 120
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#define GCC_PCIE4_LINK_DOWN_BCR 121
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#define GCC_PCIE4_PHY_BCR 122
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#define GCC_PCIE4_PIPE_CLK_ARES 123
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#define GCC_PCIE4_PIPE_RESET 124
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#define GCC_QDSS_APB2JTAG_CLK_ARES 125
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#define GCC_QDSS_AT_CLK_ARES 126
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#define GCC_QDSS_BCR 127
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#define GCC_QDSS_CFG_AHB_CLK_ARES 128
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#define GCC_QDSS_DAP_AHB_CLK_ARES 129
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#define GCC_QDSS_DAP_CLK_ARES 130
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#define GCC_QDSS_ETR_USB_CLK_ARES 131
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#define GCC_QDSS_EUD_AT_CLK_ARES 132
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#define GCC_QDSS_STM_CLK_ARES 133
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#define GCC_QDSS_TRACECLKIN_CLK_ARES 134
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#define GCC_QDSS_TSCTR_DIV16_CLK_ARES 135
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#define GCC_QDSS_TSCTR_DIV2_CLK_ARES 136
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#define GCC_QDSS_TSCTR_DIV3_CLK_ARES 137
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#define GCC_QDSS_TSCTR_DIV4_CLK_ARES 138
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#define GCC_QDSS_TSCTR_DIV8_CLK_ARES 139
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#define GCC_QDSS_TS_CLK_ARES 140
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#define GCC_QPIC_AHB_CLK_ARES 141
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#define GCC_QPIC_BCR 142
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#define GCC_QPIC_CLK_ARES 143
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#define GCC_QPIC_IO_MACRO_CLK_ARES 144
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#define GCC_QPIC_SLEEP_CLK_ARES 145
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#define GCC_QUPV3_2X_CORE_CLK_ARES 146
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#define GCC_QUPV3_AHB_MST_CLK_ARES 147
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#define GCC_QUPV3_AHB_SLV_CLK_ARES 148
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#define GCC_QUPV3_BCR 149
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#define GCC_QUPV3_CORE_CLK_ARES 150
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#define GCC_QUPV3_WRAP_SE0_BCR 151
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#define GCC_QUPV3_WRAP_SE0_CLK_ARES 152
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#define GCC_QUPV3_WRAP_SE1_BCR 153
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#define GCC_QUPV3_WRAP_SE1_CLK_ARES 154
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#define GCC_QUPV3_WRAP_SE2_BCR 155
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#define GCC_QUPV3_WRAP_SE2_CLK_ARES 156
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#define GCC_QUPV3_WRAP_SE3_BCR 157
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#define GCC_QUPV3_WRAP_SE3_CLK_ARES 158
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#define GCC_QUPV3_WRAP_SE4_BCR 159
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#define GCC_QUPV3_WRAP_SE4_CLK_ARES 160
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#define GCC_QUPV3_WRAP_SE5_BCR 161
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#define GCC_QUPV3_WRAP_SE5_CLK_ARES 162
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#define GCC_QUPV3_WRAP_SE6_BCR 163
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#define GCC_QUPV3_WRAP_SE6_CLK_ARES 164
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#define GCC_QUPV3_WRAP_SE7_BCR 165
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#define GCC_QUPV3_WRAP_SE7_CLK_ARES 166
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#define GCC_QUSB2_0_PHY_BCR 167
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#define GCC_QUSB2_1_PHY_BCR 168
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#define GCC_SDCC1_APPS_CLK_ARES 169
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#define GCC_SDCC1_ICE_CORE_CLK_ARES 170
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#define GCC_SDCC_BCR 171
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#define GCC_TLMM_AHB_CLK_ARES 172
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#define GCC_TLMM_BCR 173
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#define GCC_TLMM_CLK_ARES 174
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#define GCC_UNIPHY0_AHB_CLK_ARES 175
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#define GCC_UNIPHY0_BCR 176
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#define GCC_UNIPHY0_PMA_BCR 177
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#define GCC_UNIPHY0_SYS_CLK_ARES 178
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#define GCC_UNIPHY0_XPCS_ARES 179
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#define GCC_UNIPHY1_AHB_CLK_ARES 180
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#define GCC_UNIPHY1_BCR 181
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#define GCC_UNIPHY1_PMA_BCR 182
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#define GCC_UNIPHY1_SYS_CLK_ARES 183
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#define GCC_UNIPHY1_XPCS_ARES 184
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#define GCC_UNIPHY2_AHB_CLK_ARES 185
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#define GCC_UNIPHY2_BCR 186
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#define GCC_UNIPHY2_PMA_BCR 187
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#define GCC_UNIPHY2_SYS_CLK_ARES 188
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#define GCC_UNIPHY2_XPCS_ARES 189
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#define GCC_USB0_AUX_CLK_ARES 190
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#define GCC_USB0_MASTER_CLK_ARES 191
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#define GCC_USB0_MOCK_UTMI_CLK_ARES 192
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#define GCC_USB0_PHY_BCR 193
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#define GCC_USB0_PHY_CFG_AHB_CLK_ARES 194
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#define GCC_USB0_PIPE_CLK_ARES 195
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#define GCC_USB0_SLEEP_CLK_ARES 196
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#define GCC_USB1_BCR 197
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#define GCC_USB1_MASTER_CLK_ARES 198
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#define GCC_USB1_MOCK_UTMI_CLK_ARES 199
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#define GCC_USB1_PHY_CFG_AHB_CLK_ARES 200
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#define GCC_USB1_SLEEP_CLK_ARES 201
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#define GCC_USB3PHY_0_PHY_BCR 202
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#define GCC_USB_BCR 203
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#define GCC_UNIPHY1_XLGPCS_ARES 204
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#define GCC_UNIPHY2_XLGPCS_ARES 205
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#endif
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