196 lines
6.6 KiB
C
196 lines
6.6 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2025 SpacemiT Technology Co. Ltd
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*/
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#ifndef _DT_BINDINGS_RESET_SPACEMIT_K3_RESETS_H_
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#define _DT_BINDINGS_RESET_SPACEMIT_K3_RESETS_H_
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/* MPMU resets */
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#define RESET_MPMU_WDT 0
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#define RESET_MPMU_RIPC 1
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/* APBC resets */
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#define RESET_APBC_UART0 0
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#define RESET_APBC_UART2 1
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#define RESET_APBC_UART3 2
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#define RESET_APBC_UART4 3
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#define RESET_APBC_UART5 4
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#define RESET_APBC_UART6 5
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#define RESET_APBC_UART7 6
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#define RESET_APBC_UART8 7
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#define RESET_APBC_UART9 8
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#define RESET_APBC_UART10 9
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#define RESET_APBC_GPIO 10
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#define RESET_APBC_PWM0 11
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#define RESET_APBC_PWM1 12
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#define RESET_APBC_PWM2 13
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#define RESET_APBC_PWM3 14
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#define RESET_APBC_PWM4 15
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#define RESET_APBC_PWM5 16
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#define RESET_APBC_PWM6 17
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#define RESET_APBC_PWM7 18
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#define RESET_APBC_PWM8 19
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#define RESET_APBC_PWM9 20
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#define RESET_APBC_PWM10 21
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#define RESET_APBC_PWM11 22
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#define RESET_APBC_PWM12 23
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#define RESET_APBC_PWM13 24
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#define RESET_APBC_PWM14 25
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#define RESET_APBC_PWM15 26
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#define RESET_APBC_PWM16 27
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#define RESET_APBC_PWM17 28
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#define RESET_APBC_PWM18 29
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#define RESET_APBC_PWM19 30
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#define RESET_APBC_SPI0 31
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#define RESET_APBC_SPI1 32
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#define RESET_APBC_SPI3 33
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#define RESET_APBC_RTC 34
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#define RESET_APBC_TWSI0 35
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#define RESET_APBC_TWSI1 36
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#define RESET_APBC_TWSI2 37
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#define RESET_APBC_TWSI4 38
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#define RESET_APBC_TWSI5 39
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#define RESET_APBC_TWSI6 40
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#define RESET_APBC_TWSI8 41
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#define RESET_APBC_TIMERS0 42
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#define RESET_APBC_TIMERS1 43
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#define RESET_APBC_TIMERS2 44
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#define RESET_APBC_TIMERS3 45
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#define RESET_APBC_TIMERS4 46
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#define RESET_APBC_TIMERS5 47
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#define RESET_APBC_TIMERS6 48
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#define RESET_APBC_TIMERS7 49
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#define RESET_APBC_AIB 50
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#define RESET_APBC_ONEWIRE 51
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#define RESET_APBC_I2S0 52
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#define RESET_APBC_I2S1 53
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#define RESET_APBC_I2S2 54
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#define RESET_APBC_I2S3 55
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#define RESET_APBC_I2S4 56
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#define RESET_APBC_I2S5 57
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#define RESET_APBC_DRO 58
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#define RESET_APBC_IR0 59
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#define RESET_APBC_IR1 60
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#define RESET_APBC_TSEN 61
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#define RESET_IPC_AP2AUD 62
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#define RESET_APBC_CAN0 63
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#define RESET_APBC_CAN1 64
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#define RESET_APBC_CAN2 65
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#define RESET_APBC_CAN3 66
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#define RESET_APBC_CAN4 67
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/* APMU resets */
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#define RESET_APMU_CSI 0
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#define RESET_APMU_CCIC2PHY 1
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#define RESET_APMU_CCIC3PHY 2
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#define RESET_APMU_ISP_CIBUS 3
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#define RESET_APMU_DSI_ESC 4
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#define RESET_APMU_LCD 5
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#define RESET_APMU_V2D 6
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#define RESET_APMU_LCD_MCLK 7
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#define RESET_APMU_LCD_DSCCLK 8
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#define RESET_APMU_SC2_HCLK 9
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#define RESET_APMU_CCIC_4X 10
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#define RESET_APMU_CCIC1_PHY 11
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#define RESET_APMU_SDH_AXI 12
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#define RESET_APMU_SDH0 13
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#define RESET_APMU_SDH1 14
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#define RESET_APMU_SDH2 15
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#define RESET_APMU_USB2_AHB 16
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#define RESET_APMU_USB2_VCC 17
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#define RESET_APMU_USB2_PHY 18
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#define RESET_APMU_USB3_A_AHB 19
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#define RESET_APMU_USB3_A_VCC 20
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#define RESET_APMU_QSPI 21
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#define RESET_APMU_QSPI_BUS 22
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#define RESET_APMU_DMA 23
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#define RESET_APMU_AES_WTM 24
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#define RESET_APMU_MCB_DCLK 25
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#define RESET_APMU_MCB_ACLK 26
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#define RESET_APMU_VPU 27
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#define RESET_APMU_DTC 28
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#define RESET_APMU_GPU 29
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#define RESET_APMU_ALZO 30
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#define RESET_APMU_MC 31
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#define RESET_APMU_CPU0_POP 32
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#define RESET_APMU_CPU0_SW 33
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#define RESET_APMU_CPU1_POP 34
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#define RESET_APMU_CPU1_SW 35
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#define RESET_APMU_CPU2_POP 36
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#define RESET_APMU_CPU2_SW 37
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#define RESET_APMU_CPU3_POP 38
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#define RESET_APMU_CPU3_SW 39
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#define RESET_APMU_C0_MPSUB_SW 40
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#define RESET_APMU_CPU4_POP 41
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#define RESET_APMU_CPU4_SW 42
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#define RESET_APMU_CPU5_POP 43
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#define RESET_APMU_CPU5_SW 44
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#define RESET_APMU_CPU6_POP 45
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#define RESET_APMU_CPU6_SW 46
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#define RESET_APMU_CPU7_POP 47
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#define RESET_APMU_CPU7_SW 48
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#define RESET_APMU_C1_MPSUB_SW 49
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#define RESET_APMU_MPSUB_DBG 50
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#define RESET_APMU_USB3_A_PHY 51 /* USB3 A */
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#define RESET_APMU_USB3_B_AHB 52
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#define RESET_APMU_DSI4LN2_ESCCLK 53
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#define RESET_APMU_DSI4LN2_LCD_SW 54
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#define RESET_APMU_DSI4LN2_LCD_MCLK 55
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#define RESET_APMU_DSI4LN2_LCD_DSCCLK 56
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#define RESET_APMU_DSI4LN2_DPU_ACLK 57
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#define RESET_APMU_DPU_ACLK 58
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#define RESET_APMU_UFS_ACLK 59
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#define RESET_APMU_EDP0 60
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#define RESET_APMU_EDP1 61
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#define RESET_APMU_USB3_B_VCC 62 /* USB3 B */
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#define RESET_APMU_USB3_B_PHY 63
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#define RESET_APMU_USB3_C_AHB 64
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#define RESET_APMU_USB3_C_VCC 65
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#define RESET_APMU_USB3_C_PHY 66
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#define RESET_APMU_EMAC0 67
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#define RESET_APMU_EMAC1 68
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#define RESET_APMU_EMAC2 69
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#define RESET_APMU_ESPI_MCLK 70
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#define RESET_APMU_ESPI_SCLK 71
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#define RESET_APMU_USB3_D_AHB 72 /* USB3 D */
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#define RESET_APMU_USB3_D_VCC 73
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#define RESET_APMU_USB3_D_PHY 74
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#define RESET_APMU_UCIE_IP 75
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#define RESET_APMU_UCIE_HOT 76
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#define RESET_APMU_UCIE_MON 77
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#define RESET_APMU_RCPU_AUDIO_SYS 78
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#define RESET_APMU_RCPU_MCU_CORE 79
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#define RESET_APMU_RCPU_AUDIO_APMU 80
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#define RESET_APMU_PCIE_A_DBI 81
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#define RESET_APMU_PCIE_A_SLAVE 82
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#define RESET_APMU_PCIE_A_MASTER 83
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#define RESET_APMU_PCIE_B_DBI 84
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#define RESET_APMU_PCIE_B_SLAVE 85
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#define RESET_APMU_PCIE_B_MASTER 86
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#define RESET_APMU_PCIE_C_DBI 87
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#define RESET_APMU_PCIE_C_SLAVE 88
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#define RESET_APMU_PCIE_C_MASTER 89
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#define RESET_APMU_PCIE_D_DBI 90
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#define RESET_APMU_PCIE_D_SLAVE 91
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#define RESET_APMU_PCIE_D_MASTER 92
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#define RESET_APMU_PCIE_E_DBI 93
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#define RESET_APMU_PCIE_E_SLAVE 94
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#define RESET_APMU_PCIE_E_MASTER 95
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/* DCIU resets*/
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#define RESET_DCIU_HDMA 0
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#define RESET_DCIU_DMA350 1
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#define RESET_DCIU_DMA350_0 2
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#define RESET_DCIU_DMA350_1 3
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#define RESET_DCIU_AXIDMA0 4
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#define RESET_DCIU_AXIDMA1 5
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#define RESET_DCIU_AXIDMA2 6
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#define RESET_DCIU_AXIDMA3 7
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#define RESET_DCIU_AXIDMA4 8
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#define RESET_DCIU_AXIDMA5 9
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#define RESET_DCIU_AXIDMA6 10
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#define RESET_DCIU_AXIDMA7 11
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#endif /* _DT_BINDINGS_RESET_SPACEMIT_K3_H_ */
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