37 lines
1.2 KiB
C
37 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <asm/cpufeature.h>
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extern struct xor_block_template xor_block_pII_mmx;
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extern struct xor_block_template xor_block_p5_mmx;
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extern struct xor_block_template xor_block_sse;
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extern struct xor_block_template xor_block_sse_pf64;
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extern struct xor_block_template xor_block_avx;
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/*
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* When SSE is available, use it as it can write around L2. We may also be able
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* to load into the L1 only depending on how the cpu deals with a load to a line
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* that is being prefetched.
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*
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* When AVX2 is available, force using it as it is better by all measures.
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*
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* 32-bit without MMX can fall back to the generic routines.
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*/
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static __always_inline void __init arch_xor_init(void)
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{
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if (boot_cpu_has(X86_FEATURE_AVX) &&
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boot_cpu_has(X86_FEATURE_OSXSAVE)) {
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xor_force(&xor_block_avx);
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} else if (IS_ENABLED(CONFIG_X86_64) || boot_cpu_has(X86_FEATURE_XMM)) {
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xor_register(&xor_block_sse);
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xor_register(&xor_block_sse_pf64);
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} else if (boot_cpu_has(X86_FEATURE_MMX)) {
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xor_register(&xor_block_pII_mmx);
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xor_register(&xor_block_p5_mmx);
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} else {
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xor_register(&xor_block_8regs);
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xor_register(&xor_block_8regs_p);
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xor_register(&xor_block_32regs);
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xor_register(&xor_block_32regs_p);
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}
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}
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