311 lines
16 KiB
JSON
311 lines
16 KiB
JSON
[
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{
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"BriefDescription": "C1 residency percent per core",
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"MetricExpr": "cstate_core@c1\\-residency@ / msr@tsc@",
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"MetricGroup": "Power",
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"MetricName": "C1_Core_Residency",
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"ScaleUnit": "100%"
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},
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{
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"BriefDescription": "C2 residency percent per package",
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"MetricExpr": "cstate_pkg@c2\\-residency@ / msr@tsc@",
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"MetricGroup": "Power",
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"MetricName": "C2_Pkg_Residency",
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"ScaleUnit": "100%"
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},
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{
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"BriefDescription": "C6 residency percent per core",
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"MetricExpr": "cstate_core@c6\\-residency@ / msr@tsc@",
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"MetricGroup": "Power",
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"MetricName": "C6_Core_Residency",
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"ScaleUnit": "100%"
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},
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{
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"BriefDescription": "C6 residency percent per package",
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"MetricExpr": "cstate_pkg@c6\\-residency@ / msr@tsc@",
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"MetricGroup": "Power",
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"MetricName": "C6_Pkg_Residency",
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"ScaleUnit": "100%"
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},
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{
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"BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles",
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"MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY",
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"MetricName": "cpi",
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"ScaleUnit": "1per_instr"
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},
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{
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"BriefDescription": "The average number of cores that are in cstate C0 as observed by the power control unit (PCU)",
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"MetricExpr": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C0 / pcu_0@UNC_P_CLOCKTICKS@ * #num_packages",
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"MetricName": "cpu_cstate_c0"
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},
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{
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"BriefDescription": "The average number of cores are in cstate C6 as observed by the power control unit (PCU)",
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"MetricExpr": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C6 / pcu_0@UNC_P_CLOCKTICKS@ * #num_packages",
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"MetricName": "cpu_cstate_c6"
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},
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{
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"BriefDescription": "CPU operating frequency (in GHz)",
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"MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9",
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"MetricName": "cpu_operating_frequency",
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"ScaleUnit": "1GHz"
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},
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{
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"BriefDescription": "Percentage of time spent in the active CPU power state C0",
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"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
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"MetricName": "cpu_utilization",
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"ScaleUnit": "100%"
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},
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{
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"BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions",
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"MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
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"MetricName": "dtlb_2nd_level_load_mpi",
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"PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB",
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"ScaleUnit": "1per_instr"
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},
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{
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"BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions",
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"MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
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"MetricName": "dtlb_2nd_level_store_mpi",
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"PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB",
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"ScaleUnit": "1per_instr"
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},
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{
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"BriefDescription": "Bandwidth observed by the integrated I/O traffic controller (IIO) of IO reads that are initiated by end device controllers that are requesting memory from the CPU",
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"MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS * 4 / 1e6 / duration_time",
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"MetricName": "iio_bandwidth_read",
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"ScaleUnit": "1MB/s"
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},
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{
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"BriefDescription": "Bandwidth observed by the integrated I/O traffic controller (IIO) of IO writes that are initiated by end device controllers that are writing memory to the CPU",
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"MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS * 4 / 1e6 / duration_time",
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"MetricName": "iio_bandwidth_write",
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"ScaleUnit": "1MB/s"
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},
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{
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"BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU",
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"MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e6 / duration_time",
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"MetricName": "io_bandwidth_read",
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"ScaleUnit": "1MB/s"
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},
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{
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"BriefDescription": "Bandwidth of inbound IO reads that are initiated by end device controllers that are requesting memory from the CPU and miss the L3 cache",
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"MetricExpr": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR * 64 / 1e6 / duration_time",
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"MetricName": "io_bandwidth_read_l3_miss",
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"ScaleUnit": "1MB/s"
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},
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{
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"BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the local CPU socket",
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"MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL * 64 / 1e6 / duration_time",
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"MetricName": "io_bandwidth_read_local",
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"ScaleUnit": "1MB/s"
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},
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{
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"BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from a remote CPU socket",
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"MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE * 64 / 1e6 / duration_time",
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"MetricName": "io_bandwidth_read_remote",
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"ScaleUnit": "1MB/s"
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},
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{
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"BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU",
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"MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR) * 64 / 1e6 / duration_time",
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"MetricName": "io_bandwidth_write",
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"ScaleUnit": "1MB/s"
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},
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{
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"BriefDescription": "Bandwidth of inbound IO writes that are initiated by end device controllers that are writing memory to the CPU",
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"MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR) * 64 / 1e6 / duration_time",
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"MetricName": "io_bandwidth_write_l3_miss",
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"ScaleUnit": "1MB/s"
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},
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{
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"BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the local CPU socket",
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"MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL) * 64 / 1e6 / duration_time",
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"MetricName": "io_bandwidth_write_local",
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"ScaleUnit": "1MB/s"
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},
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{
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"BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to a remote CPU socket",
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"MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE) * 64 / 1e6 / duration_time",
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"MetricName": "io_bandwidth_write_remote",
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"ScaleUnit": "1MB/s"
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},
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{
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"BriefDescription": "The percent of inbound full cache line writes initiated by IO that miss the L3 cache",
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"MetricExpr": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM / UNC_CHA_TOR_INSERTS.IO_ITOM",
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"MetricName": "io_full_write_l3_miss",
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"ScaleUnit": "100%"
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},
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{
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"BriefDescription": "The number of times per second that ownership of a cacheline was stolen from the integrated IO controller before it was able to write back the modified line",
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"MetricExpr": "(UNC_I_MISC1.LOST_FWD + UNC_I_MISC1.SEC_RCVD_INVLD) / duration_time",
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"MetricName": "io_lost_fwd",
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"ScaleUnit": "1per_sec"
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},
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{
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"BriefDescription": "Message Signaled Interrupts (MSI) per second sent by the integrated I/O traffic controller (IIO) to System Configuration Controller (Ubox)",
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"MetricExpr": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX_POSTED / duration_time",
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"MetricName": "io_msi",
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"ScaleUnit": "1per_sec"
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},
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{
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"BriefDescription": "",
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"MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_RFO) / duration_time",
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"MetricName": "io_number_of_partial_pci_writes",
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"ScaleUnit": "1per_sec"
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},
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{
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"BriefDescription": "The percent of inbound partial writes initiated by IO that miss the L3 cache",
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"MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_RFO) / (UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_RFO)",
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"MetricName": "io_partial_write_l3_miss",
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"ScaleUnit": "100%"
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},
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{
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"BriefDescription": "The percent of inbound reads initiated by IO that miss the L3 cache",
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"MetricExpr": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR / UNC_CHA_TOR_INSERTS.IO_PCIRDCUR",
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"MetricName": "io_read_l3_miss",
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"ScaleUnit": "100%"
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},
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{
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"BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions",
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"MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
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"MetricName": "itlb_2nd_level_mpi",
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"PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB",
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"ScaleUnit": "1per_instr"
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},
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{
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"BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
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"MetricExpr": "ICACHE.MISSES / INST_RETIRED.ANY",
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"MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
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"ScaleUnit": "1per_instr"
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},
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{
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"BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions",
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"MetricExpr": "MEM_LOAD_UOPS_RETIRED.L1_HIT / INST_RETIRED.ANY",
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"MetricName": "l1d_demand_data_read_hits_per_instr",
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"ScaleUnit": "1per_instr"
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},
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{
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"BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions",
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"MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_HIT / INST_RETIRED.ANY",
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"MetricName": "l2_demand_data_read_hits_per_instr",
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"ScaleUnit": "1per_instr"
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},
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{
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"BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
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"MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
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"MetricName": "l2_demand_data_read_mpi",
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"ScaleUnit": "1per_instr"
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},
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{
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"BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
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"MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_CRD + UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF) / INST_RETIRED.ANY",
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"MetricName": "llc_code_read_mpi_demand_plus_prefetch",
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"ScaleUnit": "1per_instr"
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},
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{
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"BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
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"MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF + UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA) / INST_RETIRED.ANY",
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"MetricName": "llc_data_read_mpi_demand_plus_prefetch",
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"ScaleUnit": "1per_instr"
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},
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{
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"BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds",
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"MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT) * #num_packages)) * duration_time",
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"MetricName": "llc_demand_data_read_miss_latency",
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"ScaleUnit": "1ns"
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},
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{
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"BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory",
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"MetricExpr": "UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1e6 / duration_time",
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"MetricName": "llc_miss_local_memory_bandwidth_read",
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"ScaleUnit": "1MB/s"
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},
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{
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"BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory",
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"MetricExpr": "UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1e6 / duration_time",
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"MetricName": "llc_miss_local_memory_bandwidth_write",
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"ScaleUnit": "1MB/s"
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},
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{
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"BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory",
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"MetricExpr": "UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1e6 / duration_time",
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"MetricName": "llc_miss_remote_memory_bandwidth_read",
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"ScaleUnit": "1MB/s"
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},
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{
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"BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory",
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"MetricExpr": "UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1e6 / duration_time",
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"MetricName": "llc_miss_remote_memory_bandwidth_write",
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"ScaleUnit": "1MB/s"
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},
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{
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"BriefDescription": "",
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"MetricExpr": "MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
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"MetricName": "loads_retired_per_instr",
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"ScaleUnit": "1per_instr"
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},
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{
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"BriefDescription": "DDR memory read bandwidth (MB/sec)",
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"MetricExpr": "(UNC_M_CAS_COUNT_SCH0.RD + UNC_M_CAS_COUNT_SCH1.RD) * 64 / 1e6 / duration_time",
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"MetricName": "memory_bandwidth_read",
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"ScaleUnit": "1MB/s"
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},
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{
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"BriefDescription": "DDR memory bandwidth (MB/sec)",
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"MetricExpr": "(UNC_M_CAS_COUNT_SCH0.RD + UNC_M_CAS_COUNT_SCH1.RD + UNC_M_CAS_COUNT_SCH0.WR + UNC_M_CAS_COUNT_SCH1.WR) * 64 / 1e6 / duration_time",
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"MetricName": "memory_bandwidth_total",
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"ScaleUnit": "1MB/s"
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},
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{
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"BriefDescription": "DDR memory write bandwidth (MB/sec)",
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"MetricExpr": "(UNC_M_CAS_COUNT_SCH0.WR + UNC_M_CAS_COUNT_SCH1.WR) * 64 / 1e6 / duration_time",
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"MetricName": "memory_bandwidth_write",
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"ScaleUnit": "1MB/s"
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},
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{
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"BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches",
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"MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_REMOTE)",
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"MetricName": "numa_reads_addressed_to_local_dram",
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"ScaleUnit": "100%"
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},
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{
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"BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches",
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"MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_REMOTE) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_REMOTE)",
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"MetricName": "numa_reads_addressed_to_remote_dram",
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"ScaleUnit": "100%"
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},
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{
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"BriefDescription": "Percentage of cycles spent in System Management Interrupts.",
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"MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
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"MetricGroup": "smi",
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"MetricName": "smi_cycles",
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"MetricThreshold": "smi_cycles > 0.1",
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"ScaleUnit": "100%"
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},
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{
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"BriefDescription": "Number of SMI interrupts.",
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"MetricExpr": "msr@smi@",
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"MetricGroup": "smi",
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"MetricName": "smi_num",
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"ScaleUnit": "1SMI#"
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},
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{
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"BriefDescription": "",
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"MetricExpr": "MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY",
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"MetricName": "stores_retired_per_instr",
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"ScaleUnit": "1per_instr"
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},
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{
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"BriefDescription": "Uncore operating frequency in GHz",
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"MetricExpr": "UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages) / 1e9 / duration_time",
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"MetricName": "uncore_frequency",
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"ScaleUnit": "1GHz"
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},
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{
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"BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)",
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"MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 7.111111111111111 / 1e6 / duration_time",
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"MetricName": "upi_data_transmit_bw",
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"ScaleUnit": "1MB/s"
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}
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]
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