921 lines
45 KiB
JSON
921 lines
45 KiB
JSON
[
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{
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"BriefDescription": "Counts the number of cycles when any of the floating point or integer dividers are active.",
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"Counter": "0,1,2,3,4,5,6,7",
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"CounterMask": "1",
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"EventCode": "0xcd",
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"EventName": "ARITH.DIV_ACTIVE",
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"SampleAfterValue": "1000003",
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"UMask": "0x3"
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},
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{
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"BriefDescription": "Counts the number of cycles when any of the integer dividers are active.",
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"Counter": "0,1,2,3,4,5,6,7",
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"CounterMask": "1",
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"EventCode": "0xcd",
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"EventName": "ARITH.IDIV_ACTIVE",
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"SampleAfterValue": "1000003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts number of active integer dividers per cycle.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xcd",
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"EventName": "ARITH.IDIV_OCCUPANCY",
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"SampleAfterValue": "1000003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts the number of integer divider uops executed per cycle.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xcd",
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"EventName": "ARITH.IDIV_UOPS",
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"SampleAfterValue": "1000003",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Counts the total number of branch instructions retired for all branch types.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
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"PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for. Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003"
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},
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{
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"BriefDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT]",
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"Counter": "0,1,2,3,4,5,6,7",
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"Deprecated": "1",
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"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.ALL_NEAR_IND",
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"PublicDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT] Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x50"
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},
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{
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"BriefDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_OR_RETURN]",
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"Counter": "0,1,2,3,4,5,6,7",
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"Deprecated": "1",
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"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.ALL_NEAR_IND_OR_RET",
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"PublicDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_OR_RETURN] Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x58"
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},
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{
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"BriefDescription": "Counts the number of conditional branch instructions retired.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.COND",
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"PublicDescription": "Counts the number of conditional branch instructions retired. Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x7"
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},
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{
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"BriefDescription": "Counts the number of not taken conditional branch instructions retired.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.COND_NTAKEN",
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"PublicDescription": "Counts the number of not taken conditional branch instructions retired. Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Counts the number of taken conditional branch instructions retired.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.COND_TAKEN",
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"PublicDescription": "Counts the number of taken conditional branch instructions retired. Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x3"
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},
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{
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"BriefDescription": "Counts the number of taken backward conditional branch instructions retired.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.COND_TAKEN_BWD",
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"PublicDescription": "Counts the number of taken backward conditional branch instructions retired. Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts the number of taken forward conditional branch instructions retired.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.COND_TAKEN_FWD",
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"PublicDescription": "Counts the number of taken forward conditional branch instructions retired. Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Counts the number of near CALL branch instructions retired.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.NEAR_CALL",
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"PublicDescription": "Counts the number of near CALL branch instructions retired. Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x30"
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},
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{
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"BriefDescription": "Counts the number of near direct CALL branch instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_DIR_CALL]",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.NEAR_DIRECT_CALL",
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"PublicDescription": "Counts the number of near direct CALL branch instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_DIR_CALL] Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x20"
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},
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{
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"BriefDescription": "Counts the number of near direct JMP branch instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_DIR_JMP]",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.NEAR_DIRECT_JMP",
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"PublicDescription": "Counts the number of near direct JMP branch instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_DIR_JMP] Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x80"
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},
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{
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"BriefDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_DIRECT_CALL]",
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"Counter": "0,1,2,3,4,5,6,7",
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"Deprecated": "1",
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"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.NEAR_DIR_CALL",
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"PublicDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_DIRECT_CALL] Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x20"
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},
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{
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"BriefDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_DIRECT_JMP]",
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"Counter": "0,1,2,3,4,5,6,7",
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"Deprecated": "1",
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"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.NEAR_DIR_JMP",
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"PublicDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_DIRECT_JMP] Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x80"
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},
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{
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"BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired. [This event is alias to BR_INST_RETIRED.ALL_NEAR_IND]",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.NEAR_INDIRECT",
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"PublicDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired. [This event is alias to BR_INST_RETIRED.ALL_NEAR_IND] Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x50"
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},
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{
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"BriefDescription": "Counts the number of near indirect CALL branch instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_IND_CALL]",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.NEAR_INDIRECT_CALL",
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"PublicDescription": "Counts the number of near indirect CALL branch instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_IND_CALL] Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "Counts the number of near indirect JMP branch instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_IND_JMP]",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.NEAR_INDIRECT_JMP",
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"PublicDescription": "Counts the number of near indirect JMP branch instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_IND_JMP] Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x40"
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},
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{
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"BriefDescription": "Counts the number of near indirect JMP, near indirect CALL, and RET branch instructions retired. [This event is alias to BR_INST_RETIRED.ALL_NEAR_IND_OR_RET]",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.NEAR_INDIRECT_OR_RETURN",
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"PublicDescription": "Counts the number of near indirect JMP, near indirect CALL, and RET branch instructions retired. [This event is alias to BR_INST_RETIRED.ALL_NEAR_IND_OR_RET] Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x58"
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},
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{
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"BriefDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_CALL]",
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"Counter": "0,1,2,3,4,5,6,7",
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"Deprecated": "1",
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"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.NEAR_IND_CALL",
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"PublicDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_CALL] Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_JMP]",
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"Counter": "0,1,2,3,4,5,6,7",
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"Deprecated": "1",
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"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.NEAR_IND_JMP",
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"PublicDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_JMP] Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x40"
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},
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{
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"BriefDescription": "Counts the number of near JMP branch instructions retired.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.NEAR_JMP",
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"PublicDescription": "Counts the number of near JMP branch instructions retired. Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0xc0"
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},
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{
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"BriefDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_RETURN]",
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"Counter": "0,1,2,3,4,5,6,7",
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"Deprecated": "1",
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"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.NEAR_RET",
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"PublicDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_RETURN] Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x8"
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},
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{
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"BriefDescription": "Counts the number of near RET branch instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_RET]",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.NEAR_RETURN",
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"PublicDescription": "Counts the number of near RET branch instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_RET] Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x8"
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},
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{
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"BriefDescription": "Counts the number of near taken branch instructions retired.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc4",
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"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
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"PublicDescription": "Counts the number of near taken branch instructions retired. Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0xfb"
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},
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{
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"BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc5",
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"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
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"PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path. Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003"
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},
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{
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"BriefDescription": "This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_INDIRECT]",
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"Counter": "0,1,2,3,4,5,6,7",
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"Deprecated": "1",
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"EventCode": "0xc5",
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"EventName": "BR_MISP_RETIRED.ALL_NEAR_IND",
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"PublicDescription": "This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_INDIRECT] Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x50"
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},
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{
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"BriefDescription": "Counts the number of mispredicted not taken conditional branch instructions retired.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc5",
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"EventName": "BR_MISP_RETIRED.COND_NTAKEN",
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"PublicDescription": "Counts the number of mispredicted not taken conditional branch instructions retired. Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Counts the number of mispredicted taken conditional branch instructions retired.",
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"Counter": "0,1,2,3,4,5,6,7",
|
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"EventCode": "0xc5",
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"EventName": "BR_MISP_RETIRED.COND_TAKEN",
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"PublicDescription": "Counts the number of mispredicted taken conditional branch instructions retired. Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x3"
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},
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{
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"BriefDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired. [This event is alias to BR_MISP_RETIRED.ALL_NEAR_IND]",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc5",
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"EventName": "BR_MISP_RETIRED.NEAR_INDIRECT",
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"PublicDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired. [This event is alias to BR_MISP_RETIRED.ALL_NEAR_IND] Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x50"
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},
|
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{
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"BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]",
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"Counter": "Fixed counter 1",
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"EventName": "CPU_CLK_UNHALTED.CORE",
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"SampleAfterValue": "2000003",
|
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"UMask": "0x2"
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},
|
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{
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"BriefDescription": "Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD_P]",
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"Counter": "0,1,2,3,4,5,6,7",
|
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"EventCode": "0x3c",
|
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"EventName": "CPU_CLK_UNHALTED.CORE_P",
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"SampleAfterValue": "2000003"
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},
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{
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"BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles.",
|
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"Counter": "Fixed counter 2",
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"EventName": "CPU_CLK_UNHALTED.REF_TSC",
|
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"SampleAfterValue": "2000003",
|
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"UMask": "0x3"
|
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},
|
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{
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"BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.",
|
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"Counter": "0,1,2,3,4,5,6,7",
|
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"EventCode": "0x3c",
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"EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
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"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.",
|
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"SampleAfterValue": "2000003",
|
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"UMask": "0x1"
|
|
},
|
|
{
|
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"BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]",
|
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"Counter": "Fixed counter 1",
|
|
"EventName": "CPU_CLK_UNHALTED.THREAD",
|
|
"SampleAfterValue": "2000003",
|
|
"UMask": "0x2"
|
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},
|
|
{
|
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"BriefDescription": "Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE_P]",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x3c",
|
|
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
|
|
"SampleAfterValue": "2000003"
|
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},
|
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{
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"BriefDescription": "Fixed Counter: Counts the number of instructions retired.",
|
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"Counter": "Fixed counter 0",
|
|
"EventName": "INST_RETIRED.ANY",
|
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"PublicDescription": "Fixed Counter: Counts the number of instructions retired. Available PDIST counters: 32",
|
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"SampleAfterValue": "2000003",
|
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"UMask": "0x1"
|
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},
|
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{
|
|
"BriefDescription": "Counts the number of instructions retired.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc0",
|
|
"EventName": "INST_RETIRED.ANY_P",
|
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"PublicDescription": "Counts the number of instructions retired. Available PDIST counters: 0,1",
|
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"SampleAfterValue": "2000003"
|
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},
|
|
{
|
|
"BriefDescription": "Counts the number of uops executed on secondary integer ports 0,1,2,3.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
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"EventCode": "0xb3",
|
|
"EventName": "INT_UOPS_EXECUTED.2ND",
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|
"SampleAfterValue": "1000003",
|
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"UMask": "0x80"
|
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},
|
|
{
|
|
"BriefDescription": "Counts the number of uops executed on all Integer ports.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
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"EventCode": "0xb3",
|
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"EventName": "INT_UOPS_EXECUTED.ALL",
|
|
"SampleAfterValue": "1000003",
|
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"UMask": "0xff"
|
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},
|
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{
|
|
"BriefDescription": "Counts the number of uops executed on a load port.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xb3",
|
|
"EventName": "INT_UOPS_EXECUTED.LD",
|
|
"PublicDescription": "Counts the number of uops executed on a load port. This event counts for integer uops even if the destination is FP/vector",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x1"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of uops executed on integer port 0.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xb3",
|
|
"EventName": "INT_UOPS_EXECUTED.P0",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x8"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of uops executed on integer port 1.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xb3",
|
|
"EventName": "INT_UOPS_EXECUTED.P1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x10"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of uops executed on integer port 2.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xb3",
|
|
"EventName": "INT_UOPS_EXECUTED.P2",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x20"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of uops executed on integer port 3.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xb3",
|
|
"EventName": "INT_UOPS_EXECUTED.P3",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x40"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of uops executed on integer port 0,1, 2, 3.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xb3",
|
|
"EventName": "INT_UOPS_EXECUTED.PRIMARY",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x78"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of uops executed on a Store address port.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xb3",
|
|
"EventName": "INT_UOPS_EXECUTED.STA",
|
|
"PublicDescription": "Counts the number of uops executed on a Store address port. This event counts integer uops even if the data source is FP/vector",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x2"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of uops executed on an integer store data and jump port.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xb3",
|
|
"EventName": "INT_UOPS_EXECUTED.STD_JMP",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x4"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x03",
|
|
"EventName": "LD_BLOCKS.ADDRESS_ALIAS",
|
|
"PublicDescription": "Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x4"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of retired loads that are blocked for any of the following reasons: DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks) and others.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x03",
|
|
"EventName": "LD_BLOCKS.ALL",
|
|
"PublicDescription": "Counts the number of retired loads that are blocked for any of the following reasons: DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks) and others. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x1f"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x03",
|
|
"EventName": "LD_BLOCKS.DATA_UNKNOWN",
|
|
"PublicDescription": "Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x1"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of retired loads that are blocked because its address partially overlapped with an older store.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x03",
|
|
"EventName": "LD_BLOCKS.STORE_FORWARD",
|
|
"PublicDescription": "Counts the number of retired loads that are blocked because its address partially overlapped with an older store. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x2"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the total number of machine clears for any reason including, but not limited to, memory ordering, memory disambiguation, SMC, and FP assist.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc3",
|
|
"EventName": "MACHINE_CLEARS.ANY",
|
|
"SampleAfterValue": "1000003"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc3",
|
|
"EventName": "MACHINE_CLEARS.ANY_FAST",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x80ff"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc3",
|
|
"EventName": "MACHINE_CLEARS.DISAMBIGUATION",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x8"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc3",
|
|
"EventName": "MACHINE_CLEARS.DISAMBIGUATION_FAST",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x8008"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of virtual traps taken.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc3",
|
|
"EventName": "MACHINE_CLEARS.FPC_VIRTUAL_TRAP",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x40"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of machine clears due to memory renaming.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc3",
|
|
"EventName": "MACHINE_CLEARS.MRN_NUKE",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x10"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc3",
|
|
"EventName": "MACHINE_CLEARS.MRN_NUKE_FAST",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x8010"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc3",
|
|
"EventName": "MACHINE_CLEARS.PAGE_FAULT",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x20"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc3",
|
|
"EventName": "MACHINE_CLEARS.SMC",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x1"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of machine clears due to program modifying data (cross-core modifying code) within 1K of a recently fetched code page.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc3",
|
|
"EventName": "MACHINE_CLEARS.XMC",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x80"
|
|
},
|
|
{
|
|
"BriefDescription": "This event is deprecated. [This event is alias to LBR_INSERTS.ANY]",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"Deprecated": "1",
|
|
"EventCode": "0xe4",
|
|
"EventName": "MISC_RETIRED.LBR_INSERTS",
|
|
"PublicDescription": "This event is deprecated. [This event is alias to LBR_INSERTS.ANY] Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x1"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xe0",
|
|
"EventName": "MISC_RETIRED1.CL_INST",
|
|
"PublicDescription": "Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0xff"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of LFENCE instructions retired.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xe0",
|
|
"EventName": "MISC_RETIRED1.LFENCE",
|
|
"PublicDescription": "Counts the number of LFENCE instructions retired. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x2"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of accesses to KeyLocker cache.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xe1",
|
|
"EventName": "MISC_RETIRED2.KEYLOCKER_ACCESS",
|
|
"PublicDescription": "Counts the number of accesses to KeyLocker cache. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x10"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of misses to KeyLocker cache.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xe1",
|
|
"EventName": "MISC_RETIRED2.KEYLOCKER_MISS",
|
|
"PublicDescription": "Counts the number of misses to KeyLocker cache. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x11"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. For Tremont, UMWAIT and TPAUSE will only put the CPU into C0.1 activity state (not C0.2 activity state).",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x75",
|
|
"EventName": "SERIALIZATION.C01_MS_SCB",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x4"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of issue slots not consumed due to a color request for an FCW or MXCSR control register when all 4 colors (copies) are already in use.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x75",
|
|
"EventName": "SERIALIZATION.COLOR_STALLS",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x8"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of issue slots where no uop could issue due to an IQ scoreboard that stalls allocation until a specified older uop retires or (in the case of jump scoreboard) executes. Commonly executed instructions with IQ scoreboards include LFENCE and MFENCE.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x75",
|
|
"EventName": "SERIALIZATION.IQ_JEU_SCB",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x1"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x75",
|
|
"EventName": "SERIALIZATION.NON_C01_MS_SCB",
|
|
"PublicDescription": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires. The most commonly executed instruction with an MS scoreboard is PAUSE.",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x2"
|
|
},
|
|
{
|
|
"BriefDescription": "Fixed Counter: Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
|
|
"Counter": "Fixed counter 4",
|
|
"EventName": "TOPDOWN_BAD_SPECULATION.ALL",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x5"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x73",
|
|
"EventName": "TOPDOWN_BAD_SPECULATION.ALL_P",
|
|
"PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
|
|
"SampleAfterValue": "1000003"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to Fast Nukes such as Memory Ordering Machine clears and MRN nukes",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x73",
|
|
"EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x2"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to a branch mispredict that resulted in LSD exit.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x73",
|
|
"EventName": "TOPDOWN_BAD_SPECULATION.LSD_MISPREDICT",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x8"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x73",
|
|
"EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x3"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to Branch Mispredict",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x73",
|
|
"EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x4"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke).",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x73",
|
|
"EventName": "TOPDOWN_BAD_SPECULATION.NUKE",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x1"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls. [This event is alias to TOPDOWN_BE_BOUND.ALL_P]",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xa4",
|
|
"EventName": "TOPDOWN_BE_BOUND.ALL",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x2"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to due to certain allocation restrictions.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x74",
|
|
"EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x1"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls. [This event is alias to TOPDOWN_BE_BOUND.ALL]",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xa4",
|
|
"EventName": "TOPDOWN_BE_BOUND.ALL_P",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x2"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to LSD entry.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x74",
|
|
"EventName": "TOPDOWN_BE_BOUND.LSD",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x80"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stall (scheduler not being able to accept another uop). This could be caused by RSV full or load/store buffer block.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x74",
|
|
"EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x2"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC and FPC RAT stalls - which can be due to the FIQ and IEC reservation station stall (integer, FP and SIMD scheduler not being able to accept another uop).",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x74",
|
|
"EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x8"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to mrbl stall. A marble refers to a physical register file entry, also known as the physical destination (PDST).",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x74",
|
|
"EventName": "TOPDOWN_BE_BOUND.REGISTER",
|
|
"PublicDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to mrbl stall. A 'marble' refers to a physical register file entry, also known as the physical destination (PDST).",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x20"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x74",
|
|
"EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x40"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to iq/jeu scoreboards or ms scb",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x74",
|
|
"EventName": "TOPDOWN_BE_BOUND.SERIALIZATION",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x10"
|
|
},
|
|
{
|
|
"BriefDescription": "Fixed Counter: Counts the number of retirement slots not consumed due to front end stalls.",
|
|
"Counter": "Fixed counter 5",
|
|
"EventName": "TOPDOWN_FE_BOUND.ALL",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x6"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x9c",
|
|
"EventName": "TOPDOWN_FE_BOUND.ALL_P",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x1"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BAClear",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x71",
|
|
"EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x2"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTClear",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x71",
|
|
"EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x40"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ms",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x71",
|
|
"EventName": "TOPDOWN_FE_BOUND.CISC",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x1"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stall",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x71",
|
|
"EventName": "TOPDOWN_FE_BOUND.DECODE",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x8"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x71",
|
|
"EventName": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x8d"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x71",
|
|
"EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x72"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to itlb miss",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x71",
|
|
"EventName": "TOPDOWN_FE_BOUND.ITLB_MISS",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x10"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend that do not categorize into any other common frontend stall",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x71",
|
|
"EventName": "TOPDOWN_FE_BOUND.OTHER",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x80"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to predecode wrong",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x71",
|
|
"EventName": "TOPDOWN_FE_BOUND.PREDECODE",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x4"
|
|
},
|
|
{
|
|
"BriefDescription": "Fixed Counter: Counts the number of consumed retirement slots.",
|
|
"Counter": "Fixed counter 6",
|
|
"EventName": "TOPDOWN_RETIRING.ALL",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x7"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of consumed retirement slots.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc2",
|
|
"EventName": "TOPDOWN_RETIRING.ALL_P",
|
|
"PublicDescription": "Counts the number of consumed retirement slots. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x2"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of uops issued by the front end every cycle.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x0e",
|
|
"EventName": "UOPS_ISSUED.ANY",
|
|
"PublicDescription": "Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued.",
|
|
"SampleAfterValue": "1000003"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of uops retired that were dual destination.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc2",
|
|
"EventName": "UOPS_RETIRED.DUAL_DEST",
|
|
"PublicDescription": "Counts the number of uops retired that were dual destination. Dual destination (dual dest) micro-operations require writing to two separate destination registers or memory addresses upon execution. These uops consume two entries in the ROB and tracked separately because they involve more complex operations that necessitate multiple results. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x10"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of uops retired that are the last uop of a macro-instruction.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc2",
|
|
"EventName": "UOPS_RETIRED.EOM",
|
|
"PublicDescription": "Counts the number of uops retired that are the last uop of a macro-instruction. EOM uops indicate the 'end of a macro-instruction' and play a crucial role in the processor's control flow and recovery mechanisms.",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x1"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of integer divide uops retired.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc2",
|
|
"EventName": "UOPS_RETIRED.IDIV",
|
|
"PublicDescription": "Counts the number of integer divide uops retired. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x80"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of uops retired that originated from a loop stream detector.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc2",
|
|
"EventName": "UOPS_RETIRED.LSD",
|
|
"PublicDescription": "Counts the number of uops retired that originated from a loop stream detector. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x20"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc2",
|
|
"EventName": "UOPS_RETIRED.MS",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x4"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of x87 uops retired, includes those in ms flows.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc2",
|
|
"EventName": "UOPS_RETIRED.X87",
|
|
"SampleAfterValue": "1000003"
|
|
}
|
|
]
|