261 lines
6.5 KiB
C
261 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* dwarf-regs.c : Mapping of DWARF debug register numbers into register names.
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* Extracted from probe-finder.c
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*
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* Written by Masami Hiramatsu <mhiramat@redhat.com>
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*/
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#include <errno.h> /* for EINVAL */
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#include <string.h> /* for strcmp */
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#include <linux/kernel.h> /* for ARRAY_SIZE */
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#include <dwarf-regs.h>
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#include "../../../arch/x86/include/uapi/asm/perf_regs.h"
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struct dwarf_regs_idx {
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const char *name;
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int dwarf_regnum;
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};
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static const struct dwarf_regs_idx i386_regidx_table[] = {
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{ "eax", 0 }, { "ax", 0 }, { "al", 0 },
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{ "ecx", 1 }, { "cx", 1 }, { "cl", 1 },
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{ "edx", 2 }, { "dx", 2 }, { "dl", 2 },
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{ "ebx", 3 }, { "bx", 3 }, { "bl", 3 },
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{ "esp", 4 }, { "sp", 4 }, { "$stack", 4},
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{ "ebp", 5 }, { "bp", 5 },
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{ "esi", 6 }, { "si", 6 },
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{ "edi", 7 }, { "di", 7 },
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// 8 - Return Address RA
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{ "eflags", 9}, { "flags", 9},
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// 10 - reserved
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{ "st0", 11},
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{ "st1", 12},
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{ "st2", 13},
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{ "st3", 14},
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{ "st4", 15},
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{ "st5", 16},
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{ "st6", 17},
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{ "st7", 18},
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// 19-20 - reserved
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{ "xmm0", 21},
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{ "xmm1", 22},
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{ "xmm2", 23},
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{ "xmm3", 24},
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{ "xmm4", 25},
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{ "xmm5", 26},
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{ "xmm6", 27},
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{ "xmm7", 28},
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{ "mm0", 29},
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{ "mm1", 30},
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{ "mm2", 31},
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{ "mm3", 32},
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{ "mm4", 33},
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{ "mm5", 34},
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{ "mm6", 35},
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{ "mm7", 36},
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// 37-38 - unknown
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{ "mxcsr", 39}, // 128-bit Media Control and Status
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{ "es", 40},
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{ "cs", 41},
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{ "ss", 42},
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{ "ds", 43},
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{ "fs", 44},
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{ "gs", 45},
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// 46-47 - reserved
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{ "tr", 48}, // Task Register
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{ "ldtr", 49}, // LDT Register
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// 50-92 - reserved
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{ "fs.base", 92},
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{ "gs.base", 93},
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// End of regular dwarf registers.
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{ "eip", DWARF_REG_PC }, { "ip", DWARF_REG_PC },
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};
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static const struct dwarf_regs_idx x86_64_regidx_table[] = {
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{ "rax", 0 }, { "eax", 0 }, { "ax", 0 }, { "al", 0 },
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{ "rdx", 1 }, { "edx", 1 }, { "dx", 1 }, { "dl", 1 },
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{ "rcx", 2 }, { "ecx", 2 }, { "cx", 2 }, { "cl", 2 },
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{ "rbx", 3 }, { "edx", 3 }, { "bx", 3 }, { "bl", 3 },
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{ "rsi", 4 }, { "esi", 4 }, { "si", 4 }, { "sil", 4 },
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{ "rdi", 5 }, { "edi", 5 }, { "di", 5 }, { "dil", 5 },
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{ "rbp", 6 }, { "ebp", 6 }, { "bp", 6 }, { "bpl", 6 },
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{ "rsp", 7 }, { "esp", 7 }, { "sp", 7 }, { "spl", 7 },
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{ "r8", 8 }, { "r8d", 8 }, { "r8w", 8 }, { "r8b", 8 },
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{ "r9", 9 }, { "r9d", 9 }, { "r9w", 9 }, { "r9b", 9 },
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{ "r10", 10 }, { "r10d", 10 }, { "r10w", 10 }, { "r10b", 10 },
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{ "r11", 11 }, { "r11d", 11 }, { "r11w", 11 }, { "r11b", 11 },
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{ "r12", 12 }, { "r12d", 12 }, { "r12w", 12 }, { "r12b", 12 },
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{ "r13", 13 }, { "r13d", 13 }, { "r13w", 13 }, { "r13b", 13 },
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{ "r14", 14 }, { "r14d", 14 }, { "r14w", 14 }, { "r14b", 14 },
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{ "r15", 15 }, { "r15d", 15 }, { "r15w", 15 }, { "r15b", 15 },
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// 16 - Return Address RA
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{ "xmm0", 17},
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{ "xmm1", 18},
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{ "xmm2", 19},
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{ "xmm3", 20},
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{ "xmm4", 21},
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{ "xmm5", 22},
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{ "xmm6", 23},
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{ "xmm7", 24},
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{ "xmm8", 25},
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{ "xmm9", 26},
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{ "xmm10", 27},
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{ "xmm11", 28},
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{ "xmm12", 29},
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{ "xmm13", 30},
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{ "xmm14", 31},
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{ "xmm15", 32},
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{ "st0", 33},
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{ "st1", 34},
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{ "st2", 35},
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{ "st3", 36},
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{ "st4", 37},
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{ "st5", 38},
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{ "st6", 39},
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{ "st7", 40},
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{ "mm0", 41},
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{ "mm1", 42},
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{ "mm2", 43},
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{ "mm3", 44},
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{ "mm4", 45},
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{ "mm5", 46},
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{ "mm6", 47},
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{ "mm7", 48},
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{ "rflags", 49}, { "eflags", 49}, { "flags", 49},
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{ "es", 50},
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{ "cs", 51},
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{ "ss", 52},
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{ "ds", 53},
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{ "fs", 54},
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{ "gs", 55},
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// 56-47 - reserved
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{ "fs.base", 58},
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{ "gs.base", 59},
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// 60-61 - reserved
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{ "tr", 62}, // Task Register
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{ "ldtr", 63}, // LDT Register
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{ "mxcsr", 64}, // 128-bit Media Control and Status
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{ "fcw", 65}, // x87 Control Word
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{ "fsw", 66}, // x87 Status Word
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// End of regular dwarf registers.
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{ "rip", DWARF_REG_PC }, { "eip", DWARF_REG_PC }, { "ip", DWARF_REG_PC },
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};
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static int get_regnum(const struct dwarf_regs_idx *entries, size_t num_entries, const char *name)
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{
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if (*name != '%')
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return -EINVAL;
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name++;
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for (size_t i = 0; i < num_entries; i++) {
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if (!strcmp(entries[i].name, name))
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return entries[i].dwarf_regnum;
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}
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return -ENOENT;
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}
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int __get_dwarf_regnum_i386(const char *name)
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{
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return get_regnum(i386_regidx_table, ARRAY_SIZE(i386_regidx_table), name);
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}
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int __get_dwarf_regnum_x86_64(const char *name)
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{
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return get_regnum(x86_64_regidx_table, ARRAY_SIZE(x86_64_regidx_table), name);
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}
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int __get_dwarf_regnum_for_perf_regnum_i386(int perf_regnum)
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{
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static const int dwarf_i386_regnums[] = {
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[PERF_REG_X86_AX] = 0,
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[PERF_REG_X86_BX] = 3,
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[PERF_REG_X86_CX] = 1,
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[PERF_REG_X86_DX] = 2,
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[PERF_REG_X86_SI] = 6,
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[PERF_REG_X86_DI] = 7,
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[PERF_REG_X86_BP] = 5,
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[PERF_REG_X86_SP] = 4,
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[PERF_REG_X86_IP] = 8,
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[PERF_REG_X86_FLAGS] = 9,
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[PERF_REG_X86_CS] = 41,
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[PERF_REG_X86_SS] = 42,
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[PERF_REG_X86_DS] = 43,
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[PERF_REG_X86_ES] = 40,
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[PERF_REG_X86_FS] = 44,
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[PERF_REG_X86_GS] = 45,
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[PERF_REG_X86_XMM0] = 21,
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[PERF_REG_X86_XMM1] = 22,
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[PERF_REG_X86_XMM2] = 23,
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[PERF_REG_X86_XMM3] = 24,
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[PERF_REG_X86_XMM4] = 25,
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[PERF_REG_X86_XMM5] = 26,
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[PERF_REG_X86_XMM6] = 27,
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[PERF_REG_X86_XMM7] = 28,
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};
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if (perf_regnum == 0)
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return 0;
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if (perf_regnum < 0 || perf_regnum > (int)ARRAY_SIZE(dwarf_i386_regnums) ||
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dwarf_i386_regnums[perf_regnum] == 0)
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return -ENOENT;
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return dwarf_i386_regnums[perf_regnum];
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}
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int __get_dwarf_regnum_for_perf_regnum_x86_64(int perf_regnum)
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{
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static const int dwarf_x86_64_regnums[] = {
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[PERF_REG_X86_AX] = 0,
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[PERF_REG_X86_BX] = 3,
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[PERF_REG_X86_CX] = 2,
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[PERF_REG_X86_DX] = 1,
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[PERF_REG_X86_SI] = 4,
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[PERF_REG_X86_DI] = 5,
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[PERF_REG_X86_BP] = 6,
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[PERF_REG_X86_SP] = 7,
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[PERF_REG_X86_IP] = 16,
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[PERF_REG_X86_FLAGS] = 49,
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[PERF_REG_X86_CS] = 51,
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[PERF_REG_X86_SS] = 52,
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[PERF_REG_X86_DS] = 53,
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[PERF_REG_X86_ES] = 50,
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[PERF_REG_X86_FS] = 54,
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[PERF_REG_X86_GS] = 55,
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[PERF_REG_X86_R8] = 8,
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[PERF_REG_X86_R9] = 9,
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[PERF_REG_X86_R10] = 10,
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[PERF_REG_X86_R11] = 11,
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[PERF_REG_X86_R12] = 12,
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[PERF_REG_X86_R13] = 13,
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[PERF_REG_X86_R14] = 14,
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[PERF_REG_X86_R15] = 15,
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[PERF_REG_X86_XMM0] = 17,
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[PERF_REG_X86_XMM1] = 18,
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[PERF_REG_X86_XMM2] = 19,
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[PERF_REG_X86_XMM3] = 20,
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[PERF_REG_X86_XMM4] = 21,
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[PERF_REG_X86_XMM5] = 22,
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[PERF_REG_X86_XMM6] = 23,
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[PERF_REG_X86_XMM7] = 24,
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[PERF_REG_X86_XMM8] = 25,
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[PERF_REG_X86_XMM9] = 26,
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[PERF_REG_X86_XMM10] = 27,
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[PERF_REG_X86_XMM11] = 28,
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[PERF_REG_X86_XMM12] = 29,
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[PERF_REG_X86_XMM13] = 30,
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[PERF_REG_X86_XMM14] = 31,
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[PERF_REG_X86_XMM15] = 32,
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};
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if (perf_regnum == 0)
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return 0;
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if (perf_regnum < 0 || perf_regnum > (int)ARRAY_SIZE(dwarf_x86_64_regnums) ||
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dwarf_x86_64_regnums[perf_regnum] == 0)
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return -ENOENT;
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return dwarf_x86_64_regnums[perf_regnum];
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}
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