97 lines
2.1 KiB
YAML
97 lines
2.1 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/cpufreq/qcom,shikra-epss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Shikra SoC EPSS
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maintainers:
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- Imran Shaik <imran.shaik@oss.qualcomm.com>
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- Taniya Das <taniya.das@oss.qualcomm.com>
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description: |
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EPSS is a hardware engine used by some Qualcomm SoCs to manage
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frequency in hardware. It is capable of controlling frequency for
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multiple clusters.
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The Qualcomm Shikra SoC EPSS supports up to 12 frequency lookup table
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(LUT) entries.
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properties:
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compatible:
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enum:
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- qcom,shikra-epss
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reg:
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items:
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- description: Frequency domain 0 register region
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- description: Frequency domain 1 register region
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reg-names:
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items:
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- const: freq-domain0
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- const: freq-domain1
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clocks:
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items:
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- description: XO Clock
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- description: GPLL0 Clock
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clock-names:
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items:
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- const: xo
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- const: alternate
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interrupts:
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items:
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- description: IRQ line for DCVSH 0
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- description: IRQ line for DCVSH 1
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interrupt-names:
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items:
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- const: dcvsh-irq-0
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- const: dcvsh-irq-1
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'#freq-domain-cells':
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const: 1
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- interrupts
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- interrupt-names
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- '#freq-domain-cells'
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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cpufreq@fd91000 {
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compatible = "qcom,shikra-epss";
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reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>;
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reg-names = "freq-domain0", "freq-domain1";
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gpll0>;
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clock-names = "xo", "alternate";
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";
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#freq-domain-cells = <1>;
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#clock-cells = <1>;
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};
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};
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...
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