95 lines
3.1 KiB
YAML
95 lines
3.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,sdram-props.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Common properties for SDRAM types
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description:
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Different SDRAM types generally use the same properties and only differ in the
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range of legal values for each. This file defines the common parts that can be
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reused for each type. Nodes using this schema should generally be nested under
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a SDRAM channel node.
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maintainers:
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- Krzysztof Kozlowski <krzk@kernel.org>
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properties:
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compatible:
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description: |
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Compatible strings can be either explicit vendor names and part numbers
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(e.g. elpida,ECB240ABACN), or generated strings of the form
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lpddrX-YY,ZZZZ or ddrX-YYYY,AAAA...-ZZ where X, Y, and Z are lowercase
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hexadecimal with leading zeroes, and A is lowercase ASCII.
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For LPDDR and DDR SDRAM, X is the SDRAM version (2, 3, 4, etc.).
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For LPDDR SDRAM:
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- YY is the manufacturer ID (from MR5), 1 byte
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- ZZZZ is the revision ID (from MR6 and MR7), 2 bytes
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For DDR4 SDRAM with SPD, according to JEDEC SPD4.1.2.L-6:
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- YYYY is the manufacturer ID, 2 bytes, from bytes 320 and 321
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- AAAA... is the part number, 20 bytes (20 chars) from bytes 329 to 348
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without trailing spaces
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- ZZ is the revision ID, 1 byte, from byte 349
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The former form is useful when the SDRAM vendor and part number are
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known, for example, when memory is soldered on the board. The latter
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form is useful when SDRAM nodes are created at runtime by boot firmware
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that doesn't have access to static part number information.
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reg:
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description:
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The rank number of this memory rank when used as a subnode to an memory
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channel.
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minimum: 0
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maximum: 3
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revision-id:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description: |
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SDRAM revision ID:
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- LPDDR SDRAM, decoded from Mode Registers 6 and 7, always 2 bytes.
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- DDR4 SDRAM, decoded from the SPD from byte 349 according to
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JEDEC SPD4.1.2.L-6, always 1 byte.
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One byte per uint32 cell (e.g., <MR6 MR7>).
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maxItems: 2
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items:
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minimum: 0
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maximum: 255
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density:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Density of the SDRAM chip in megabits:
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- LPDDR SDRAM, decoded from Mode Register 8.
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- DDR4 SDRAM, decoded from the SPD from bits 3-0 of byte 4 according to
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JEDEC SPD4.1.2.L-6.
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enum:
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- 64
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- 128
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- 256
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- 512
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- 1024
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- 2048
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- 3072
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- 4096
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- 6144
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- 8192
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- 12288
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- 16384
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- 24576
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- 32768
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io-width:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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I/O bus width in bits of the SDRAM chip:
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- LPDDR SDRAM, decoded from Mode Register 8.
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- DDR4 SDRAM, decoded from the SPD from bits 2-0 of byte 12 according to
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JEDEC SPD4.1.2.L-6.
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enum:
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- 8
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- 16
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- 32
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additionalProperties: true
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