188 lines
4.8 KiB
Devicetree
188 lines
4.8 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Support for the common parts shared by all the different CPU options on
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* Variscite VAR-SOM-6UL Module
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*
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* Copyright 2019 Variscite Ltd.
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* Copyright 2025 Bootlin
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*/
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#include <dt-bindings/clock/imx6ul-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Variscite VAR-SOM-6UL module";
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compatible = "variscite,var-som-imx6ul", "fsl,imx6ul";
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x20000000>;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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reg_gpio_dvfs: reg-gpio-dvfs {
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compatible = "regulator-gpio";
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regulator-min-microvolt = <1300000>;
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regulator-max-microvolt = <1400000>;
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regulator-name = "gpio_dvfs";
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regulator-type = "voltage";
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gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
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states = <1300000 0x1
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1400000 0x0>;
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};
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};
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&clks {
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assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
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assigned-clock-rates = <786432000>;
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};
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&iomuxc {
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
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MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
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>;
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};
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pinctrl_tsc: tscgrp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
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MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
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MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
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MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
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MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
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MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
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MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
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MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059
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MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
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MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
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MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
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MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
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fsl,pins = <
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MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
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MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
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MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
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MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
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MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
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MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
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fsl,pins = <
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MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
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MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
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MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
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MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
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MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
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MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
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MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
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MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
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MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
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MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
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MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
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MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
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MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
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MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
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MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
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fsl,pins = <
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MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
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MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
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MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
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MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
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MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
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MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
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MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
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MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
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MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
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MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
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fsl,pins = <
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MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
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MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
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MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
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MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
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MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
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MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
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MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
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MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
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MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
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MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
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>;
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};
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};
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&pxp {
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status = "okay";
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};
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&snvs_poweroff {
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status = "okay";
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};
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&tsc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_tsc>;
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xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
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measure-delay-time = <0xffff>;
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pre-charge-time = <0xfff>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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uart-has-rtscts;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
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bus-width = <8>;
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no-1-8-v;
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non-removable;
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keep-power-in-suspend;
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wakeup-source;
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status = "okay";
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};
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