45 lines
1.1 KiB
Devicetree
45 lines
1.1 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Ethernet ENET1 support for Variscite VAR-SOM-6UL module with
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* the EC configuration option ((ethernet PHY assembled on SOM).
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*
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* Copyright 2019-2024 Variscite Ltd.
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* Copyright 2026 Dimonoff
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*/
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>;
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phy-mode = "rmii";
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phy-handle = <ðphy0>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
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MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
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>;
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};
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};
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&mdio_enet2 {
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ethphy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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clocks = <&rmii_ref_clk>;
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clock-names = "rmii-ref";
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reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
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reset-assert-us = <100000>;
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micrel,led-mode = <1>;
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micrel,rmii-reference-clock-select-25-mhz;
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};
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};
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