414 lines
9.1 KiB
Devicetree
414 lines
9.1 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) Protonic Holland
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* Author: David Jander <david@protonic.nl>
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*/
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#include "stm32mp15xc.dtsi"
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#include "stm32mp15-pinctrl.dtsi"
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#include "stm32mp15xxaa-pinctrl.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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chosen {
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stdout-path = "serial0:1500000n8";
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};
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aliases {
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serial0 = &uart4;
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ethernet0 = ðernet0;
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spi1 = &spi1;
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spi2 = &spi2;
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spi3 = &spi3;
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spi4 = &spi4;
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spi5 = &spi5;
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spi6 = &spi6;
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};
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memory@c0000000 {
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device_type = "memory";
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reg = <0xC0000000 0x10000000>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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mcuram2: mcuram2@10000000 {
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compatible = "shared-dma-pool";
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reg = <0x10000000 0x40000>;
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no-map;
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};
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vdev0vring0: vdev0vring0@10040000 {
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compatible = "shared-dma-pool";
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reg = <0x10040000 0x1000>;
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no-map;
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};
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vdev0vring1: vdev0vring1@10041000 {
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compatible = "shared-dma-pool";
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reg = <0x10041000 0x1000>;
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no-map;
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};
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vdev0buffer: vdev0buffer@10042000 {
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compatible = "shared-dma-pool";
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reg = <0x10042000 0x4000>;
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no-map;
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};
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mcuram: mcuram@30000000 {
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compatible = "shared-dma-pool";
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reg = <0x30000000 0x40000>;
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no-map;
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};
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retram: retram@38000000 {
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compatible = "shared-dma-pool";
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reg = <0x38000000 0x10000>;
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no-map;
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};
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};
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v3v3: regulator-v3v3 {
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compatible = "regulator-fixed";
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regulator-name = "v3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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v5v: regulator-v5v {
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compatible = "regulator-fixed";
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regulator-name = "v5v";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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};
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};
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&adc {
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/* ANA0, ANA1 are dedicated pins and don't need pinctrl. */
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pinctrl-0 = <&adc12_pins_mecsbc>;
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pinctrl-names = "default";
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vdd-supply = <&v3v3>;
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vdda-supply = <&v3v3>;
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vref-supply = <&vrefbuf>;
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status = "okay";
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};
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&adc1 {
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status = "okay";
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channel@2 {
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reg = <2>;
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st,min-sample-time-ns = <20000>;
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label = "ain0";
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};
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channel@6 {
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reg = <6>;
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st,min-sample-time-ns = <20000>;
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label = "ain1";
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};
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channel@10 {
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reg = <10>;
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st,min-sample-time-ns = <200000>;
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label = "phint0_ain";
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};
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channel@16 {
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reg = <16>;
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st,min-sample-time-ns = <20000>;
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label = "lsin";
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};
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channel@19 {
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reg = <19>;
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st,min-sample-time-ns = <20000>;
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label = "hpdcm1_i1";
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};
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};
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&adc2 {
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status = "okay";
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channel@2 {
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reg = <2>;
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st,min-sample-time-ns = <20000>;
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label = "ain2";
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};
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channel@6 {
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reg = <6>;
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st,min-sample-time-ns = <20000>;
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label = "ain3";
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};
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};
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ðernet0 {
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status = "okay";
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pinctrl-0 = <ðernet0_rgmii_pins_x>;
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pinctrl-1 = <ðernet0_rgmii_sleep_pins_x>;
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pinctrl-names = "default", "sleep";
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phy-mode = "rgmii-id";
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max-speed = <1000>;
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phy-handle = <&phy0>;
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st,eth-clk-sel;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@8 {
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reg = <8>;
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interrupts-extended = <&gpiog 7 IRQ_TYPE_LEVEL_LOW>;
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reset-gpios = <&gpiog 10 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10>;
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reset-deassert-us = <35>;
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};
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};
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_pins_a>;
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pinctrl-1 = <&i2c2_sleep_pins_a>;
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status = "okay";
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gpio0: gpio@20 {
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compatible = "ti,tca6416";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio1: gpio@21 {
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compatible = "ti,tca6416";
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reg = <0x21>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&qspi {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qspi_clk_pins_a
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&qspi_bk1_pins_a
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&qspi_cs1_pins_a>;
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pinctrl-1 = <&qspi_clk_sleep_pins_a
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&qspi_bk1_sleep_pins_a
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&qspi_cs1_sleep_pins_a>;
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <104000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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&{qspi_bk1_pins_a/pins} {
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pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
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<STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
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<STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
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<STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
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/delete-property/ bias-disable;
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bias-pull-up;
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};
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&timers1 {
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/delete-property/dmas;
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/delete-property/dma-names;
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status = "okay";
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hpdcm0_pwm: pwm {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pwm1_pins_mecio1>;
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pinctrl-1 = <&pwm1_sleep_pins_mecio1>;
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status = "okay";
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};
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};
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&timers8 {
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/delete-property/dmas;
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/delete-property/dma-names;
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status = "okay";
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hpdcm1_pwm: pwm {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pwm8_pins_mecio1>;
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pinctrl-1 = <&pwm8_sleep_pins_mecio1>;
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status = "okay";
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};
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};
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&uart4 {
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pinctrl-names = "default", "sleep", "idle";
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pinctrl-0 = <&uart4_pins_a>;
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pinctrl-1 = <&uart4_sleep_pins_a>;
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pinctrl-2 = <&uart4_idle_pins_a>;
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/delete-property/dmas;
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/delete-property/dma-names;
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status = "okay";
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};
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&{uart4_pins_a/pins1} {
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pinmux = <STM32_PINMUX('B', 9, AF8)>; /* UART4_TX */
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};
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&{uart4_pins_a/pins2} {
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pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
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/delete-property/ bias-disable;
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bias-pull-up;
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};
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&usbotg_hs {
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dr_mode = "host";
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pinctrl-0 = <&usbotg_hs_pins_a>;
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pinctrl-names = "default";
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phys = <&usbphyc_port1 0>;
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phy-names = "usb2-phy";
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vbus-supply = <&v5v>;
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status = "okay";
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};
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&usbphyc {
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status = "okay";
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};
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&usbphyc_port0 {
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phy-supply = <&v3v3>;
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};
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&usbphyc_port1 {
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phy-supply = <&v3v3>;
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};
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&vrefbuf {
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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vdda-supply = <&v3v3>;
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status = "okay";
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};
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&pinctrl {
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adc12_pins_mecsbc: adc12-ain-mecsbc-0 {
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pins {
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pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* ADC1_INP2 */
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<STM32_PINMUX('F', 12, ANALOG)>, /* ADC1_INP6 */
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<STM32_PINMUX('F', 13, ANALOG)>, /* ADC2_INP2 */
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<STM32_PINMUX('F', 14, ANALOG)>, /* ADC2_INP6 */
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<STM32_PINMUX('A', 0, ANALOG)>, /* ADC1_INP16 */
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<STM32_PINMUX('A', 3, ANALOG)>, /* ADC1_INP15 */
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<STM32_PINMUX('A', 4, ANALOG)>, /* ADC1_INP18 */
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<STM32_PINMUX('A', 5, ANALOG)>, /* ADC1_INP19 */
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<STM32_PINMUX('A', 6, ANALOG)>, /* ADC1_INP3 */
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<STM32_PINMUX('B', 0, ANALOG)>, /* ADC1_INP9 */
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<STM32_PINMUX('B', 1, ANALOG)>, /* ADC1_INP5 */
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<STM32_PINMUX('C', 0, ANALOG)>, /* ADC1_INP10 */
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<STM32_PINMUX('C', 3, ANALOG)>; /* ADC1_INP13 */
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};
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};
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pinctrl_hog_d_mecsbc: hog-d-0 {
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pins {
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pinmux = <STM32_PINMUX('D', 12, GPIO)>; /* STP_RESETn */
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bias-pull-up;
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drive-push-pull;
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slew-rate = <0>;
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};
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};
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pwm1_pins_mecio1: pwm1-mecio1-0 {
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pins {
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pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */
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<STM32_PINMUX('A', 8, AF1)>; /* TIM1_CH2 */
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bias-pull-down;
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drive-push-pull;
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slew-rate = <0>;
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};
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};
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pwm1_sleep_pins_mecio1: pwm1-sleep-mecio1-0 {
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pins {
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pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* TIM1_CH1 */
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<STM32_PINMUX('A', 8, ANALOG)>; /* TIM1_CH2 */
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};
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};
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pwm8_pins_mecio1: pwm8-mecio1-0 {
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pins {
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pinmux = <STM32_PINMUX('I', 5, AF3)>, /* TIM8_CH1 */
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<STM32_PINMUX('I', 6, AF3)>; /* TIM8_CH2 */
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bias-pull-down;
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drive-push-pull;
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slew-rate = <0>;
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};
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};
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pwm8_sleep_pins_mecio1: pwm8-sleep-mecio1-0 {
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pins {
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pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* TIM8_CH1 */
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<STM32_PINMUX('I', 6, ANALOG)>; /* TIM8_CH2 */
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};
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};
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ethernet0_rgmii_pins_x: rgmii-0 {
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pins1 {
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pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
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<STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
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<STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */
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<STM32_PINMUX('B', 13, AF11)>, /* ETH_RGMII_TXD1 */
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<STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
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<STM32_PINMUX('B', 8, AF11)>, /* ETH_RGMII_TXD3 */
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<STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
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<STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
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bias-disable;
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drive-push-pull;
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slew-rate = <3>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins3 {
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pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
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<STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
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<STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
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<STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */
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<STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
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<STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
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bias-disable;
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};
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};
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ethernet0_rgmii_sleep_pins_x: rgmii-sleep-0 {
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pins1 {
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pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
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<STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
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<STM32_PINMUX('B', 12, ANALOG)>, /* ETH_RGMII_TXD0 */
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<STM32_PINMUX('B', 13, ANALOG)>, /* ETH_RGMII_TXD1 */
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<STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
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<STM32_PINMUX('B', 8, ANALOG)>, /* ETH_RGMII_TXD3 */
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<STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
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<STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
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<STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
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<STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
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<STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
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<STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
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<STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */
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<STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
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<STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
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};
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};
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};
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