99 lines
2.0 KiB
Devicetree
99 lines
2.0 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2025 Fedor Ross <fedor.ross@ifm.com>
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include "imx8mn-pinfunc.h"
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&ecspi1 {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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ksz8794: ethernet-switch@1 {
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compatible = "microchip,ksz8794";
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pinctrl-names = "default", "reset";
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pinctrl-0 = <&pinctrl_ks8794>;
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pinctrl-1 = <&pinctrl_ks8794>;
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reg = <1>;
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reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
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spi-max-frequency = <5000000>;
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan1";
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};
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port@1 {
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reg = <1>;
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label = "lan2";
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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};
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port@4 {
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reg = <4>;
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label = "cpu";
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ethernet = <&fec1>;
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phy-mode = "rgmii-id";
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rx-internal-delay-ps = <2000>;
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tx-internal-delay-ps = <2000>;
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fixed-link {
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full-duplex;
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speed = <1000>;
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};
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};
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};
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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status = "okay";
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fixed-link {
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full-duplex;
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speed = <1000>;
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};
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};
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&iomuxc {
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pinctrl_fec1: fec1-grp {
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fsl,pins = <
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MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x16
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MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x96
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MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16
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MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16
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MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16
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MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16
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MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x96
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MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x96
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MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x96
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MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x96
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MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x10
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MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x96
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MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x96
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MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16
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MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1d6
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>;
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};
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pinctrl_ks8794: ks8794-grp {
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fsl,pins = <
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/* KSZ8794 reset line */
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MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x16
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>;
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};
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};
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