162 lines
2.4 KiB
Devicetree
162 lines
2.4 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2023 Marvell Technology Group Ltd.
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*
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* Device Tree file for Marvell Armada 7020 Com Express CPU module board.
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*/
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#include "armada-7020.dtsi"
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/ {
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model = "Marvell Armada-7020 COMEXPRESS board setup";
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compatible = "marvell,armada7020-cpu-module", "marvell,armada7020",
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"marvell,armada-ap806-dual", "marvell,armada-ap806";
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x2 0x00000000>;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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ethernet0 = &cp0_eth0;
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ethernet1 = &cp0_eth1;
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};
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};
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&ap_clk {
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status = "okay";
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};
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&gic {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <100000>;
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};
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&spi0 {
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status = "okay";
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};
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&uart0 {
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status = "okay";
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};
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&cp0_mdio {
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status = "okay";
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phy0: ethernet-phy@10 {
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reg = <0x10>;
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};
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};
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&cp0_ethernet {
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status = "okay";
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};
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&cp0_eth0 {
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status = "okay";
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phy-mode = "10gbase-r";
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managed = "in-band-status";
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/* Generic PHY, providing serdes lanes */
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phys = <&cp0_comphy4 0>;
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};
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&cp0_eth1 {
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status = "okay";
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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};
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&cp0_usb3_0 {
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status = "okay";
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};
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&cp0_usb3_1 {
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status = "okay";
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};
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&cp0_clk {
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status = "okay";
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};
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&cp0_i2c0 {
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status = "okay";
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clock-frequency = <100000>;
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};
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&cp0_nand_controller {
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status = "okay";
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nand@0 {
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reg = <0>;
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label = "main-storage";
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nand-rb = <0>;
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nand-ecc-mode = "hw";
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nand-on-flash-bbt;
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nand-ecc-strength = <8>;
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nand-ecc-step-size = <512>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "U-Boot";
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reg = <0 0x400000>;
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};
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partition@200000 {
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label = "Linux";
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reg = <0x400000 0x100000>;
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};
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partition@1000000 {
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label = "Filesystem";
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reg = <0x500000 0x1e00000>;
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};
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};
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};
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};
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&cp0_pcie0 {
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status = "okay";
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num-lanes = <4>;
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num-viewport = <8>;
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ranges = <0x81000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x00010000
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0x82000000 0x0 0x00000000 0x0 0xc0000000 0x0 0x30000000>;
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/* Generic PHY, providing serdes lanes */
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phys = <&cp0_comphy0 0
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&cp0_comphy1 0
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&cp0_comphy2 0
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&cp0_comphy3 0>;
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};
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&cp0_sata0 {
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/* CPM Lane 0 - U29 */
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status = "okay";
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sata-port@1 {
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status = "okay";
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/* Generic PHY, providing serdes lanes */
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phys = <&cp0_comphy5 1>;
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};
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};
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&cp0_sdhci0 {
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pinctrl-names = "default";
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pinctrl-0 = <&sdhci_pins>;
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status = "okay";
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bus-width = <4>;
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no-1-8-v;
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broken-cd;
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};
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