4173 lines
97 KiB
Devicetree
4173 lines
97 KiB
Devicetree
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
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#include <dt-bindings/clock/qcom,eliza-dispcc.h>
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#include <dt-bindings/clock/qcom,eliza-gcc.h>
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#include <dt-bindings/clock/qcom,eliza-tcsr.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/dma/qcom-gpi.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interconnect/qcom,eliza-rpmh.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,osm-l3.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mailbox/qcom-ipcc.h>
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#include <dt-bindings/phy/phy-qcom-qmp.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a520";
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reg = <0x0 0x0>;
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clocks = <&cpufreq_hw 0>;
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power-domains = <&cpu_pd0>;
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power-domain-names = "psci";
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enable-method = "psci";
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next-level-cache = <&l2_0>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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l2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3>;
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l3: l3-cache {
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compatible = "cache";
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cache-level = <3>;
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cache-unified;
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};
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};
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a520";
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reg = <0x0 0x100>;
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clocks = <&cpufreq_hw 0>;
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power-domains = <&cpu_pd1>;
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power-domain-names = "psci";
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enable-method = "psci";
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next-level-cache = <&l2_0>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a520";
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reg = <0x0 0x200>;
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clocks = <&cpufreq_hw 0>;
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power-domains = <&cpu_pd2>;
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power-domain-names = "psci";
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enable-method = "psci";
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next-level-cache = <&l2_2>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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qcom,freq-domain = <&cpufreq_hw 0>;
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l2_2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3>;
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};
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a720";
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reg = <0x0 0x300>;
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clocks = <&cpufreq_hw 1>;
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power-domains = <&cpu_pd3>;
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power-domain-names = "psci";
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enable-method = "psci";
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next-level-cache = <&l2_3>;
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capacity-dmips-mhz = <1792>;
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dynamic-power-coefficient = <238>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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l2_3: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3>;
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};
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};
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cpu4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,cortex-a720";
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reg = <0x0 0x400>;
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clocks = <&cpufreq_hw 1>;
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power-domains = <&cpu_pd4>;
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power-domain-names = "psci";
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enable-method = "psci";
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next-level-cache = <&l2_4>;
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capacity-dmips-mhz = <1792>;
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dynamic-power-coefficient = <238>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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l2_4: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3>;
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};
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};
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cpu5: cpu@500 {
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device_type = "cpu";
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compatible = "arm,cortex-a720";
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reg = <0x0 0x500>;
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clocks = <&cpufreq_hw 1>;
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power-domains = <&cpu_pd5>;
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power-domain-names = "psci";
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enable-method = "psci";
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next-level-cache = <&l2_5>;
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capacity-dmips-mhz = <1792>;
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dynamic-power-coefficient = <238>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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l2_5: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3>;
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};
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};
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cpu6: cpu@600 {
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device_type = "cpu";
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compatible = "arm,cortex-a720";
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reg = <0x0 0x600>;
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clocks = <&cpufreq_hw 1>;
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power-domains = <&cpu_pd6>;
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power-domain-names = "psci";
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enable-method = "psci";
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next-level-cache = <&l2_6>;
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capacity-dmips-mhz = <1792>;
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dynamic-power-coefficient = <238>;
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qcom,freq-domain = <&cpufreq_hw 1>;
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l2_6: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3>;
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};
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};
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cpu7: cpu@700 {
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device_type = "cpu";
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compatible = "arm,cortex-x3";
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reg = <0x0 0x700>;
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clocks = <&cpufreq_hw 2>;
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power-domains = <&cpu_pd7>;
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power-domain-names = "psci";
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enable-method = "psci";
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next-level-cache = <&l2_7>;
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capacity-dmips-mhz = <1894>;
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dynamic-power-coefficient = <588>;
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qcom,freq-domain = <&cpufreq_hw 2>;
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l2_7: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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core4 {
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cpu = <&cpu4>;
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};
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core5 {
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cpu = <&cpu5>;
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};
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core6 {
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cpu = <&cpu6>;
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};
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core7 {
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cpu = <&cpu7>;
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};
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};
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};
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idle-states {
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entry-method = "psci";
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cluster0_c4: cpu-sleep-0 {
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compatible = "arm,idle-state";
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idle-state-name = "silver-rail-power-collapse";
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arm,psci-suspend-param = <0x40000004>;
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entry-latency-us = <550>;
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exit-latency-us = <750>;
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min-residency-us = <6700>;
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};
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cluster1_c4: cpu-sleep-1 {
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compatible = "arm,idle-state";
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idle-state-name = "gold-rail-power-collapse";
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arm,psci-suspend-param = <0x40000004>;
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entry-latency-us = <550>;
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exit-latency-us = <1050>;
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min-residency-us = <7951>;
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};
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cluster2_c4: cpu-sleep-2 {
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compatible = "arm,idle-state";
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idle-state-name = "gold-plus-rail-power-collapse";
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arm,psci-suspend-param = <0x40000004>;
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entry-latency-us = <500>;
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exit-latency-us = <1350>;
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min-residency-us = <7480>;
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};
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};
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domain-idle-states {
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cluster_sleep_0: cluster-sleep-0 {
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compatible = "domain-idle-state";
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arm,psci-suspend-param = <0x41000044>;
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entry-latency-us = <750>;
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exit-latency-us = <2350>;
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min-residency-us = <9144>;
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};
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cluster_sleep_1: cluster-sleep-1 {
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compatible = "domain-idle-state";
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arm,psci-suspend-param = <0x4100b344>;
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entry-latency-us = <2800>;
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exit-latency-us = <4400>;
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min-residency-us = <10150>;
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};
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};
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};
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firmware {
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scm: scm {
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compatible = "qcom,scm-eliza", "qcom,scm";
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interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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qcom,dload-mode = <&tcsr 0x1a000>;
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};
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};
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clk_virt: interconnect-0 {
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compatible = "qcom,eliza-clk-virt";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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mc_virt: interconnect-1 {
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compatible = "qcom,eliza-mc-virt";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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memory@a0000000 {
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device_type = "memory";
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/* We expect the bootloader to fill in the size */
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reg = <0x0 0xa0000000 0x0 0x0>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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cpu_pd0: power-domain-cpu0 {
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#power-domain-cells = <0>;
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power-domains = <&cluster_pd>;
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domain-idle-states = <&cluster0_c4>;
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};
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cpu_pd1: power-domain-cpu1 {
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#power-domain-cells = <0>;
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power-domains = <&cluster_pd>;
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domain-idle-states = <&cluster0_c4>;
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};
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cpu_pd2: power-domain-cpu2 {
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#power-domain-cells = <0>;
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power-domains = <&cluster_pd>;
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domain-idle-states = <&cluster0_c4>;
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};
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cpu_pd3: power-domain-cpu3 {
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#power-domain-cells = <0>;
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power-domains = <&cluster_pd>;
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domain-idle-states = <&cluster1_c4>;
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};
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cpu_pd4: power-domain-cpu4 {
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#power-domain-cells = <0>;
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power-domains = <&cluster_pd>;
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domain-idle-states = <&cluster1_c4>;
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};
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cpu_pd5: power-domain-cpu5 {
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#power-domain-cells = <0>;
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power-domains = <&cluster_pd>;
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domain-idle-states = <&cluster1_c4>;
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};
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cpu_pd6: power-domain-cpu6 {
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#power-domain-cells = <0>;
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power-domains = <&cluster_pd>;
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domain-idle-states = <&cluster1_c4>;
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};
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cpu_pd7: power-domain-cpu7 {
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#power-domain-cells = <0>;
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power-domains = <&cluster_pd>;
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domain-idle-states = <&cluster2_c4>;
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};
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cluster_pd: power-domain-cluster {
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#power-domain-cells = <0>;
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domain-idle-states = <&cluster_sleep_0>,
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<&cluster_sleep_1>;
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gunyah_hyp_mem: gunyah-hyp@80000000 {
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reg = <0x0 0x80000000 0x0 0xe00000>;
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no-map;
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};
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cpusys_vm_mem: cpusys-vm-mem@80e00000 {
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reg = <0x0 0x80e00000 0x0 0x400000>;
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no-map;
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};
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cpucp_mem: cpucp@81200000 {
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reg = <0x0 0x81200000 0x0 0x100000>;
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no-map;
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};
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xbl_dtlog_mem: xbl-dtlog@81a00000 {
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reg = <0x0 0x81a00000 0x0 0x40000>;
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no-map;
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};
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aop_image_mem: aop-image@81c00000 {
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reg = <0x0 0x81c00000 0x0 0x60000>;
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no-map;
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};
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aop_cmd_db_mem: aop-cmd-db@81c60000 {
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compatible = "qcom,cmd-db";
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reg = <0x0 0x81c60000 0x0 0x20000>;
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no-map;
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};
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/* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */
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aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 {
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reg = <0x0 0x81c80000 0x0 0x74000>;
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no-map;
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};
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/* Secdata region can be reused by apps */
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smem_mem: smem@81d00000 {
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compatible = "qcom,smem";
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reg = <0x0 0x81d00000 0x0 0x200000>;
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hwlocks = <&tcsr_mutex 3>;
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no-map;
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};
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cpucp_scandump_mem: cpucp-scandump@82200000 {
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reg = <0x0 0x82200000 0x0 0x180000>;
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no-map;
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};
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adsp_mhi_mem: adsp-mhi@82380000 {
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reg = <0x0 0x82380000 0x0 0x20000>;
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no-map;
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};
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soccp_sdi_mem: soccp-sdi@823a0000 {
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reg = <0x0 0x823a0000 0x0 0x40000>;
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no-map;
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};
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pmic_minii_dump_mem: pmic-minii-dump@823e0000 {
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reg = <0x0 0x823e0000 0x0 0x80000>;
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no-map;
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};
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pvmfw_mem: pvmfw@824a0000 {
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reg = <0x0 0x824a0000 0x0 0x100000>;
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no-map;
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};
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hyp_db_mem: hyp-db@825a0000 {
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reg = <0x0 0x825a0000 0x0 0x60000>;
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no-map;
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};
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global_sync_mem: global-sync@82600000 {
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reg = <0x0 0x82600000 0x0 0x100000>;
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no-map;
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};
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tz_stat_mem: tz-stat@82700000 {
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reg = <0x0 0x82700000 0x0 0x100000>;
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no-map;
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};
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qdss_mem: qdss@82800000 {
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reg = <0x0 0x82800000 0x0 0x2000000>;
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no-map;
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};
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dsm_partition_1_mem: dsm-partition-1@84a00000 {
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reg = <0x0 0x84a00000 0x0 0x3700000>;
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no-map;
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};
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mpss_mem: mpss@88100000 {
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reg = <0x0 0x88100000 0x0 0xcd00000>;
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no-map;
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};
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q6_mpss_dtb_mem: q6-mpss-dtb@94e00000 {
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reg = <0x0 0x94e00000 0x0 0x80000>;
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no-map;
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};
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ipa_fw_mem: ipa-fw@94e80000 {
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reg = <0x0 0x94e80000 0x0 0x10000>;
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no-map;
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};
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ipa_gsi_mem: ipa-gsi@94e90000 {
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reg = <0x0 0x94e90000 0x0 0xa000>;
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no-map;
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};
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gpu_micro_code_mem: gpu-micro-code@94e9a000 {
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reg = <0x0 0x94e9a000 0x0 0x2000>;
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no-map;
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};
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camera_mem: camera@94f00000 {
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reg = <0x0 0x94f00000 0x0 0x800000>;
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no-map;
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};
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camera_2_mem: camera-2@95700000 {
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reg = <0x0 0x95700000 0x0 0x800000>;
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no-map;
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};
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video_mem: video@95f00000 {
|
|
reg = <0x0 0x95f00000 0x0 0x800000>;
|
|
no-map;
|
|
};
|
|
|
|
soccp_mem: soccp@96700000 {
|
|
reg = <0x0 0x96700000 0x0 0x180000>;
|
|
no-map;
|
|
};
|
|
|
|
wpss_mem: wpss@97000000 {
|
|
reg = <0x0 0x97000000 0x0 0x1900000>;
|
|
no-map;
|
|
};
|
|
|
|
cdsp_mem: cdsp@98900000 {
|
|
reg = <0x0 0x98900000 0x0 0x1400000>;
|
|
no-map;
|
|
};
|
|
|
|
q6_cdsp_dtb_mem: q6-cdsp-dtb@99d00000 {
|
|
reg = <0x0 0x99d00000 0x0 0x80000>;
|
|
no-map;
|
|
};
|
|
|
|
q6_adsp_dtb_mem: q6-adsp-dtb@99d80000 {
|
|
reg = <0x0 0x99d80000 0x0 0x80000>;
|
|
no-map;
|
|
};
|
|
|
|
adspslpi_mem: adspslpi@99e00000 {
|
|
reg = <0x0 0x99e00000 0x0 0x2a00000>;
|
|
no-map;
|
|
};
|
|
|
|
wlan_msa_mem: wlan-msa@a6400000 {
|
|
reg = <0x0 0xa6400000 0x0 0xc00000>;
|
|
no-map;
|
|
};
|
|
|
|
xbl_ramdump_mem: xbl-ramdump@b8000000 {
|
|
reg = <0x0 0xb8000000 0x0 0x1c0000>;
|
|
no-map;
|
|
};
|
|
|
|
/* Merged tz_reserved, xbl_sc, and qtee regions */
|
|
tz_merged_mem: tz-merged@d8000000 {
|
|
reg = <0x0 0xd8000000 0x0 0x600000>;
|
|
no-map;
|
|
};
|
|
|
|
trust_ui_vm_mem: trust-ui-vm@f3800000 {
|
|
reg = <0x0 0xf3800000 0x0 0x4400000>;
|
|
no-map;
|
|
};
|
|
|
|
oem_vm_mem: oem-vm@f7c00000 {
|
|
reg = <0x0 0xf7c00000 0x0 0x4c00000>;
|
|
no-map;
|
|
};
|
|
|
|
llcc_lpi_mem: llcc-lpi@ff800000 {
|
|
reg = <0x0 0xff800000 0x0 0x180000>;
|
|
no-map;
|
|
};
|
|
};
|
|
|
|
smp2p-adsp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <443>, <429>;
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
|
|
IPCC_MPROC_SIGNAL_SMP2P
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc IPCC_CLIENT_LPASS
|
|
IPCC_MPROC_SIGNAL_SMP2P>;
|
|
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <2>;
|
|
|
|
smp2p_adsp_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
smp2p_adsp_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
soc: soc@0 {
|
|
compatible = "simple-bus";
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
|
|
ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
|
|
|
|
gcc: clock-controller@100000 {
|
|
compatible = "qcom,eliza-gcc";
|
|
reg = <0x0 0x00100000 0x0 0x1f4200>;
|
|
|
|
clocks = <&bi_tcxo_div2>,
|
|
<&sleep_clk>,
|
|
<0>,
|
|
<0>,
|
|
<&ufs_mem_phy 0>,
|
|
<&ufs_mem_phy 1>,
|
|
<&ufs_mem_phy 2>,
|
|
<0>;
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
ipcc: mailbox@406000 {
|
|
compatible = "qcom,eliza-ipcc", "qcom,ipcc";
|
|
reg = <0x0 0x00406000 0x0 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
|
|
#mbox-cells = <2>;
|
|
};
|
|
|
|
gpi_dma2: dma-controller@800000 {
|
|
compatible = "qcom,eliza-gpi-dma", "qcom,sm6350-gpi-dma";
|
|
reg = <0x0 0x00800000 0x0 0x60000>;
|
|
|
|
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
dma-channels = <12>;
|
|
dma-channel-mask = <0x3f>;
|
|
#dma-cells = <3>;
|
|
|
|
iommus = <&apps_smmu 0x436 0>;
|
|
|
|
dma-coherent;
|
|
};
|
|
|
|
qupv3_2: geniqup@8c0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0x0 0x008c0000 0x0 0x2000>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
|
clock-names = "m-ahb",
|
|
"s-ahb";
|
|
|
|
iommus = <&apps_smmu 0x423 0x0>;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
i2c8: i2c@880000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x00880000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
|
|
<&gpi_dma2 1 0 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c8_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi8: spi@880000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x00880000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 0 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c9: i2c@884000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x00884000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
|
|
<&gpi_dma2 1 1 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c9_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi9: spi@884000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x00884000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 1 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c10: i2c@888000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x00888000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
|
|
<&gpi_dma2 1 2 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c10_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi10: spi@888000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x00888000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 2 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c11: i2c@88c000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x0088c000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
|
|
<&gpi_dma2 1 3 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c11_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi11: spi@88c000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x0088c000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 3 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c12: i2c@890000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x00890000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
|
|
<&gpi_dma2 1 4 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c12_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi12: spi@890000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x00890000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 4 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
uart13: serial@894000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x00894000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config";
|
|
|
|
pinctrl-0 = <&qup_uart13_default>;
|
|
pinctrl-names = "default";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c14: i2c@898000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x00898000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
|
|
<&gpi_dma2 1 6 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c14_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi14: spi@898000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x00898000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 6 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c15: i2c@89c000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x0089c000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
|
|
<&gpi_dma2 1 7 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c15_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi15: spi@89c000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x0089c000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
|
|
<&gpi_dma2 1 7 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
gpi_dma1: dma-controller@a00000 {
|
|
compatible = "qcom,eliza-gpi-dma", "qcom,sm6350-gpi-dma";
|
|
reg = <0x0 0x00a00000 0x0 0x60000>;
|
|
|
|
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
dma-channels = <12>;
|
|
dma-channel-mask = <0x3f>;
|
|
#dma-cells = <3>;
|
|
|
|
iommus = <&apps_smmu 0xb6 0x0>;
|
|
|
|
dma-coherent;
|
|
};
|
|
|
|
qupv3_1: geniqup@ac0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0x0 0x00ac0000 0x0 0x2000>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
clock-names = "m-ahb",
|
|
"s-ahb";
|
|
|
|
iommus = <&apps_smmu 0xa3 0x0>;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
status = "disabled";
|
|
|
|
i2c0: i2c@a80000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x00a80000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 0 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c0_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@a80000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x00a80000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 0 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@a84000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x00a84000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 1 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c1_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@a84000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x00a84000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 1 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@a88000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x00a88000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 2 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c2_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi2: spi@a88000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x00a88000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 2 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@a8c000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x00a8c000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 3 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c3_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi3: spi@a8c000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x00a8c000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 3 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@a90000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x00a90000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 4 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c4_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi4: spi@a90000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x00a90000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 4 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi4_clk>, <&qup_spi4_cs>,
|
|
<&qup_spi4_data>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@a94000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x00a94000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config";
|
|
|
|
pinctrl-0 = <&qup_uart5_default>, <&qup_uart5_cts_rts>;
|
|
pinctrl-names = "default";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
uart6: serial@a98000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x00a98000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config";
|
|
|
|
pinctrl-0 = <&qup_uart6_default>, <&qup_uart6_cts_rts>;
|
|
pinctrl-names = "default";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c7: i2c@a9c000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x00a9c000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 7 QCOM_GPI_I2C>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_i2c7_data_clk>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi7: spi@a9c000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x00a9c000 0x0 0x4000>;
|
|
|
|
interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
|
|
clock-names = "se";
|
|
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
|
|
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
|
|
dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
|
|
<&gpi_dma1 1 7 QCOM_GPI_SPI>;
|
|
dma-names = "tx",
|
|
"rx";
|
|
|
|
pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
|
|
pinctrl-names = "default";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
sdhc_1: mmc@f44000 {
|
|
compatible = "qcom,eliza-sdhci", "qcom,sdhci-msm-v5";
|
|
reg = <0x0 0x00f44000 0x0 0x1000>,
|
|
<0x0 0x00f45000 0x0 0x1000>;
|
|
reg-names = "hc",
|
|
"cqhci";
|
|
|
|
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hc_irq",
|
|
"pwr_irq";
|
|
|
|
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
|
|
<&gcc GCC_SDCC1_APPS_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "iface",
|
|
"core",
|
|
"xo";
|
|
|
|
interconnects = <&aggre2_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc 30 /*TODO: SLAVE_SDCC_1*/ QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
interconnect-names = "sdhc-ddr",
|
|
"cpu-sdhc";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
operating-points-v2 = <&sdhc1_opp_table>;
|
|
|
|
qcom,dll-config = <0x000f44ec>;
|
|
qcom,ddr-config = <0x80040868>;
|
|
|
|
iommus = <&apps_smmu 0x520 0x0>;
|
|
dma-coherent;
|
|
|
|
bus-width = <8>;
|
|
|
|
resets = <&gcc GCC_SDCC1_BCR>;
|
|
|
|
status = "disabled";
|
|
|
|
sdhc1_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-100000000 {
|
|
opp-hz = /bits/ 64 <100000000>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
};
|
|
|
|
opp-384000000 {
|
|
opp-hz = /bits/ 64 <384000000>;
|
|
required-opps = <&rpmhpd_opp_svs_l1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cnoc_main: interconnect@1500000 {
|
|
compatible = "qcom,eliza-cnoc-main";
|
|
reg = <0x0 0x01500000 0x0 0x16080>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
#interconnect-cells = <2>;
|
|
};
|
|
|
|
config_noc: interconnect@1600000 {
|
|
compatible = "qcom,eliza-cnoc-cfg";
|
|
reg = <0x0 0x01600000 0x0 0x5200>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
#interconnect-cells = <2>;
|
|
};
|
|
|
|
system_noc: interconnect@1680000 {
|
|
compatible = "qcom,eliza-system-noc";
|
|
reg = <0x0 0x01680000 0x0 0x40000>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
#interconnect-cells = <2>;
|
|
};
|
|
|
|
pcie_noc: interconnect@16c0000 {
|
|
compatible = "qcom,eliza-pcie-anoc";
|
|
reg = <0x0 0x016c0000 0x0 0x11400>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
|
|
<&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
|
|
#interconnect-cells = <2>;
|
|
};
|
|
|
|
aggre1_noc: interconnect@16e0000 {
|
|
compatible = "qcom,eliza-aggre1-noc";
|
|
reg = <0x0 0x016e0000 0x0 0x16400>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
|
|
#interconnect-cells = <2>;
|
|
};
|
|
|
|
aggre2_noc: interconnect@1700000 {
|
|
compatible = "qcom,eliza-aggre2-noc";
|
|
reg = <0x0 0x01700000 0x0 0x1f400>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
clocks = <&rpmhcc RPMH_IPA_CLK>;
|
|
#interconnect-cells = <2>;
|
|
};
|
|
|
|
mmss_noc: interconnect@1780000 {
|
|
compatible = "qcom,eliza-mmss-noc";
|
|
reg = <0x0 0x01780000 0x0 0x7d800>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
#interconnect-cells = <2>;
|
|
};
|
|
|
|
ufs_mem_phy: phy@1d80000 {
|
|
compatible = "qcom,eliza-qmp-ufs-phy",
|
|
"qcom,sm8650-qmp-ufs-phy";
|
|
reg = <0x0 0x01d80000 0x0 0x2000>;
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
|
|
<&tcsr TCSR_UFS_CLKREF_EN>;
|
|
clock-names = "ref",
|
|
"ref_aux",
|
|
"qref";
|
|
|
|
resets = <&ufs_mem_hc 0>;
|
|
reset-names = "ufsphy";
|
|
|
|
power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
|
|
|
|
#clock-cells = <1>;
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
ufs_mem_hc: ufshc@1d84000 {
|
|
compatible = "qcom,eliza-ufshc",
|
|
"qcom,ufshc",
|
|
"jedec,ufs-2.0";
|
|
reg = <0x0 0x01d84000 0x0 0x3000>,
|
|
<0x0 0x01da0000 0x0 0x15000>;
|
|
reg-names = "std",
|
|
"mcq";
|
|
|
|
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_UFS_PHY_AHB_CLK>,
|
|
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
|
|
<&rpmhcc RPMH_LN_BB_CLK3>,
|
|
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
|
|
clock-names = "core_clk",
|
|
"bus_aggr_clk",
|
|
"iface_clk",
|
|
"core_clk_unipro",
|
|
"ref_clk",
|
|
"tx_lane0_sync_clk",
|
|
"rx_lane0_sync_clk",
|
|
"rx_lane1_sync_clk";
|
|
|
|
operating-points-v2 = <&ufs_opp_table>;
|
|
|
|
resets = <&gcc GCC_UFS_PHY_BCR>;
|
|
reset-names = "rst";
|
|
|
|
interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
interconnect-names = "ufs-ddr",
|
|
"cpu-ufs";
|
|
|
|
power-domains = <&gcc GCC_UFS_PHY_GDSC>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
|
|
iommus = <&apps_smmu 0x60 0x0>;
|
|
dma-coherent;
|
|
|
|
msi-parent = <&gic_its 0x60>;
|
|
|
|
lanes-per-direction = <2>;
|
|
qcom,ice = <&ice>;
|
|
|
|
phys = <&ufs_mem_phy>;
|
|
phy-names = "ufsphy";
|
|
|
|
#reset-cells = <1>;
|
|
|
|
status = "disabled";
|
|
|
|
ufs_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-100000000 {
|
|
opp-hz = /bits/ 64 <100000000>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <100000000>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <0>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
};
|
|
|
|
opp-201500000 {
|
|
opp-hz = /bits/ 64 <201500000>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <201500000>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <0>;
|
|
required-opps = <&rpmhpd_opp_svs_l1>;
|
|
};
|
|
|
|
opp-403000000 {
|
|
opp-hz = /bits/ 64 <403000000>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <403000000>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <0>,
|
|
/bits/ 64 <0>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
};
|
|
};
|
|
};
|
|
|
|
ice: crypto@1d88000 {
|
|
compatible = "qcom,eliza-inline-crypto-engine",
|
|
"qcom,inline-crypto-engine";
|
|
reg = <0x0 0x01d88000 0x0 0x18000>;
|
|
|
|
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
|
|
<&gcc GCC_UFS_PHY_AHB_CLK>;
|
|
clock-names = "core",
|
|
"iface";
|
|
power-domains = <&gcc GCC_UFS_PHY_GDSC>;
|
|
};
|
|
|
|
cryptobam: dma-controller@1dc4000 {
|
|
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
|
|
reg = <0x0 0x01dc4000 0x0 0x28000>;
|
|
|
|
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
#dma-cells = <1>;
|
|
|
|
iommus = <&apps_smmu 0x480 0>,
|
|
<&apps_smmu 0x481 0>;
|
|
|
|
qcom,ee = <0>;
|
|
qcom,num-ees = <4>;
|
|
num-channels = <20>;
|
|
qcom,controlled-remotely;
|
|
};
|
|
|
|
crypto: crypto@1dfa000 {
|
|
compatible = "qcom,eliza-qce", "qcom,sm8150-qce", "qcom,qce";
|
|
reg = <0x0 0x01dfa000 0x0 0x6000>;
|
|
|
|
interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "memory";
|
|
|
|
dmas = <&cryptobam 4>, <&cryptobam 5>;
|
|
dma-names = "rx", "tx";
|
|
|
|
iommus = <&apps_smmu 0x480 0>,
|
|
<&apps_smmu 0x481 0>;
|
|
};
|
|
|
|
tcsr_mutex: hwlock@1f40000 {
|
|
compatible = "qcom,tcsr-mutex";
|
|
reg = <0x0 0x01f40000 0x0 0x20000>;
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
tcsr: clock-controller@1fbf000 {
|
|
compatible = "qcom,eliza-tcsr", "syscon";
|
|
reg = <0x0 0x01fbf000 0x0 0x21000>;
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
remoteproc_adsp: remoteproc@3000000 {
|
|
compatible = "qcom,eliza-adsp-pas";
|
|
reg = <0x0 0x03000000 0x0 0x10000>;
|
|
|
|
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
|
|
<&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "wdog",
|
|
"fatal",
|
|
"ready",
|
|
"handover",
|
|
"stop-ack",
|
|
"shutdown-ack";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_LCX>,
|
|
<&rpmhpd RPMHPD_LMX>;
|
|
power-domain-names = "lcx",
|
|
"lmx";
|
|
|
|
interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
|
|
memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
|
|
|
|
qcom,qmp = <&aoss_qmp>;
|
|
|
|
qcom,smem-states = <&smp2p_adsp_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
status = "disabled";
|
|
|
|
glink-edge {
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc IPCC_CLIENT_LPASS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
|
|
label = "lpass";
|
|
qcom,remote-pid = <2>;
|
|
};
|
|
};
|
|
|
|
lpass_lpiaon_noc: interconnect@7400000 {
|
|
compatible = "qcom,eliza-lpass-lpiaon-noc";
|
|
reg = <0x0 0x07400000 0x0 0x19080>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
#interconnect-cells = <2>;
|
|
};
|
|
|
|
lpass_lpicx_noc: interconnect@7420000 {
|
|
compatible = "qcom,eliza-lpass-lpicx-noc";
|
|
reg = <0x0 0x07420000 0x0 0x44080>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
#interconnect-cells = <2>;
|
|
};
|
|
|
|
sdhc_2: mmc@8804000 {
|
|
compatible = "qcom,eliza-sdhci", "qcom,sdhci-msm-v5";
|
|
reg = <0x0 0x08804000 0x0 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hc_irq",
|
|
"pwr_irq";
|
|
|
|
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
|
|
<&gcc GCC_SDCC2_APPS_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "iface",
|
|
"core",
|
|
"xo";
|
|
|
|
interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
interconnect-names = "sdhc-ddr",
|
|
"cpu-sdhc";
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
operating-points-v2 = <&sdhc2_opp_table>;
|
|
|
|
qcom,dll-config = <0x0007442c>;
|
|
qcom,ddr-config = <0x80040868>;
|
|
|
|
iommus = <&apps_smmu 0x540 0x0>;
|
|
dma-coherent;
|
|
|
|
bus-width = <4>;
|
|
|
|
resets = <&gcc GCC_SDCC2_BCR>;
|
|
|
|
status = "disabled";
|
|
|
|
sdhc2_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-100000000 {
|
|
opp-hz = /bits/ 64 <100000000>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
};
|
|
|
|
opp-202000000 {
|
|
opp-hz = /bits/ 64 <202000000>;
|
|
required-opps = <&rpmhpd_opp_svs_l1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
usb_hsphy: phy@88e3000 {
|
|
compatible = "qcom,eliza-snps-eusb2-phy",
|
|
"qcom,sm8550-snps-eusb2-phy";
|
|
reg = <0x0 0x088e3000 0x0 0x154>;
|
|
#phy-cells = <0>;
|
|
|
|
clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
|
|
clock-names = "ref";
|
|
|
|
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_dp_qmpphy: phy@88e8000 {
|
|
compatible = "qcom,eliza-qmp-usb3-dp-phy",
|
|
"qcom,sm8650-qmp-usb3-dp-phy";
|
|
reg = <0x0 0x088e8000 0x0 0x4000>;
|
|
|
|
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
|
|
<&tcsr TCSR_USB3_CLKREF_EN>,
|
|
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
|
|
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
|
|
clock-names = "aux",
|
|
"ref",
|
|
"com_aux",
|
|
"usb3_pipe";
|
|
|
|
resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
|
|
<&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
|
|
reset-names = "phy",
|
|
"common";
|
|
|
|
power-domains = <&gcc GCC_USB3_PHY_GDSC>;
|
|
|
|
#clock-cells = <1>;
|
|
#phy-cells = <1>;
|
|
|
|
mode-switch;
|
|
orientation-switch;
|
|
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
usb_dp_qmpphy_out: endpoint {
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
usb_dp_qmpphy_usb_ss_in: endpoint {
|
|
remote-endpoint = <&usb_dwc3_ss>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
|
|
usb_dp_qmpphy_dp_in: endpoint {
|
|
remote-endpoint = <&mdss_dp0_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
usb: usb@a600000 {
|
|
compatible = "qcom,eliza-dwc3", "qcom,snps-dwc3";
|
|
reg = <0x0 0x0a600000 0x0 0xfc100>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
|
|
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
|
|
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "dwc_usb3",
|
|
"pwr_event",
|
|
"hs_phy_irq",
|
|
"dp_hs_phy_irq",
|
|
"dm_hs_phy_irq",
|
|
"ss_phy_irq";
|
|
|
|
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
|
|
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
|
|
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
|
|
<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
|
|
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "cfg_noc",
|
|
"core",
|
|
"iface",
|
|
"sleep",
|
|
"mock_utmi",
|
|
"xo";
|
|
|
|
assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
|
|
assigned-clock-rates = <19200000>,
|
|
<200000000>;
|
|
|
|
resets = <&gcc GCC_USB30_PRIM_BCR>;
|
|
|
|
phys = <&usb_hsphy>,
|
|
<&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
|
|
phy-names = "usb2-phy",
|
|
"usb3-phy";
|
|
|
|
interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
interconnect-names = "usb-ddr", "apps-usb";
|
|
|
|
iommus = <&apps_smmu 0x40 0x0>;
|
|
|
|
power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
|
|
snps,hird-threshold = /bits/ 8 <0x0>;
|
|
snps,usb2-gadget-lpm-disable;
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,dis_enblslpm_quirk;
|
|
snps,dis-u1-entry-quirk;
|
|
snps,dis-u2-entry-quirk;
|
|
snps,is-utmi-l1-suspend;
|
|
snps,usb3_lpm_capable;
|
|
snps,usb2-lpm-disable;
|
|
snps,has-lpm-erratum;
|
|
tx-fifo-resize;
|
|
|
|
dma-coherent;
|
|
usb-role-switch;
|
|
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
usb_dwc3_hs: endpoint {
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
usb_dwc3_ss: endpoint {
|
|
remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss: display-subsystem@ae00000 {
|
|
compatible = "qcom,eliza-mdss";
|
|
reg = <0x0 0x0ae00000 0x0 0x1000>;
|
|
reg-names = "mdss";
|
|
ranges;
|
|
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
|
<&gcc GCC_DISP_HF_AXI_CLK>,
|
|
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
|
|
|
resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
|
|
|
|
interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
|
&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
|
|
interconnect-names = "mdp0-mem",
|
|
"cpu-cfg";
|
|
|
|
power-domains = <&dispcc MDSS_GDSC>;
|
|
|
|
iommus = <&apps_smmu 0x800 0x2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
status = "disabled";
|
|
|
|
mdss_mdp: display-controller@ae01000 {
|
|
compatible = "qcom,eliza-dpu";
|
|
reg = <0x0 0x0ae01000 0x0 0x93000>,
|
|
<0x0 0x0aeb0000 0x0 0x3000>;
|
|
reg-names = "mdp",
|
|
"vbif";
|
|
|
|
interrupts-extended = <&mdss 0>;
|
|
|
|
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
|
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
|
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
|
|
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
|
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
|
clock-names = "nrt_bus",
|
|
"iface",
|
|
"lut",
|
|
"core",
|
|
"vsync";
|
|
|
|
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
|
assigned-clock-rates = <19200000>;
|
|
|
|
operating-points-v2 = <&mdp_opp_table>;
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
dpu_intf1_out: endpoint {
|
|
remote-endpoint = <&mdss_dsi0_in>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
dpu_intf2_out: endpoint {
|
|
remote-endpoint = <&mdss_dsi1_in>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
|
|
dpu_intf0_out: endpoint {
|
|
remote-endpoint = <&mdss_dp0_in>;
|
|
};
|
|
};
|
|
/* TODO: HDMI */
|
|
};
|
|
|
|
mdp_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-150000000 {
|
|
opp-hz = /bits/ 64 <150000000>;
|
|
required-opps = <&rpmhpd_opp_low_svs_d1>;
|
|
};
|
|
|
|
opp-207000000 {
|
|
opp-hz = /bits/ 64 <207000000>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
};
|
|
|
|
opp-342000000 {
|
|
opp-hz = /bits/ 64 <342000000>;
|
|
required-opps = <&rpmhpd_opp_svs>;
|
|
};
|
|
|
|
opp-417000000 {
|
|
opp-hz = /bits/ 64 <417000000>;
|
|
required-opps = <&rpmhpd_opp_svs_l1>;
|
|
};
|
|
|
|
opp-532000000 {
|
|
opp-hz = /bits/ 64 <532000000>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
};
|
|
|
|
opp-600000000 {
|
|
opp-hz = /bits/ 64 <600000000>;
|
|
required-opps = <&rpmhpd_opp_nom_l1>;
|
|
};
|
|
|
|
opp-660000000 {
|
|
opp-hz = /bits/ 64 <660000000>;
|
|
required-opps = <&rpmhpd_opp_turbo>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss_dsi0: dsi@ae94000 {
|
|
compatible = "qcom,eliza-dsi-ctrl", "qcom,sm8750-dsi-ctrl",
|
|
"qcom,mdss-dsi-ctrl";
|
|
reg = <0x0 0x0ae94000 0x0 0x400>;
|
|
reg-names = "dsi_ctrl";
|
|
|
|
interrupts-extended = <&mdss 4>;
|
|
|
|
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
|
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
|
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
|
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
|
|
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
|
<&gcc GCC_DISP_HF_AXI_CLK>,
|
|
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
|
|
<&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
|
|
<&dispcc DISP_CC_ESYNC0_CLK>,
|
|
<&dispcc DISP_CC_OSC_CLK>,
|
|
<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
|
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
|
|
clock-names = "byte",
|
|
"byte_intf",
|
|
"pixel",
|
|
"core",
|
|
"iface",
|
|
"bus",
|
|
"dsi_pll_pixel",
|
|
"dsi_pll_byte",
|
|
"esync",
|
|
"osc",
|
|
"byte_src",
|
|
"pixel_src";
|
|
|
|
operating-points-v2 = <&mdss_dsi_opp_table>;
|
|
|
|
phys = <&mdss_dsi0_phy>;
|
|
phy-names = "dsi";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
mdss_dsi0_in: endpoint {
|
|
remote-endpoint = <&dpu_intf1_out>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
mdss_dsi0_out: endpoint {
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss_dsi_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-140630000 {
|
|
opp-hz = /bits/ 64 <140630000>;
|
|
required-opps = <&rpmhpd_opp_low_svs_d1>;
|
|
};
|
|
|
|
opp-187500000 {
|
|
opp-hz = /bits/ 64 <187500000>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
};
|
|
|
|
opp-300000000 {
|
|
opp-hz = /bits/ 64 <300000000>;
|
|
required-opps = <&rpmhpd_opp_svs>;
|
|
};
|
|
|
|
opp-358000000 {
|
|
opp-hz = /bits/ 64 <358000000>;
|
|
required-opps = <&rpmhpd_opp_svs_l1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss_dsi0_phy: phy@ae95000 {
|
|
compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm";
|
|
reg = <0x0 0x0ae95000 0x0 0x200>,
|
|
<0x0 0x0ae95200 0x0 0x300>,
|
|
<0x0 0x0ae95500 0x0 0x400>;
|
|
reg-names = "dsi_phy",
|
|
"dsi_phy_lane",
|
|
"dsi_pll";
|
|
|
|
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
|
<&bi_tcxo_div2>;
|
|
clock-names = "iface",
|
|
"ref";
|
|
|
|
#clock-cells = <1>;
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
mdss_dsi1: dsi@ae96000 {
|
|
compatible = "qcom,eliza-dsi-ctrl", "qcom,sm8750-dsi-ctrl",
|
|
"qcom,mdss-dsi-ctrl";
|
|
reg = <0x0 0x0ae96000 0x0 0x400>;
|
|
reg-names = "dsi_ctrl";
|
|
|
|
interrupts-extended = <&mdss 5>;
|
|
|
|
clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
|
|
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
|
|
<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
|
|
<&dispcc DISP_CC_MDSS_ESC1_CLK>,
|
|
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
|
<&gcc GCC_DISP_HF_AXI_CLK>,
|
|
<&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>,
|
|
<&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
|
|
<&dispcc DISP_CC_ESYNC1_CLK>,
|
|
<&dispcc DISP_CC_OSC_CLK>,
|
|
<&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
|
|
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
|
|
clock-names = "byte",
|
|
"byte_intf",
|
|
"pixel",
|
|
"core",
|
|
"iface",
|
|
"bus",
|
|
"dsi_pll_pixel",
|
|
"dsi_pll_byte",
|
|
"esync",
|
|
"osc",
|
|
"byte_src",
|
|
"pixel_src";
|
|
|
|
operating-points-v2 = <&mdss_dsi_opp_table>;
|
|
|
|
phys = <&mdss_dsi1_phy>;
|
|
phy-names = "dsi";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
mdss_dsi1_in: endpoint {
|
|
remote-endpoint = <&dpu_intf2_out>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
mdss_dsi1_out: endpoint {
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss_dsi1_phy: phy@ae97000 {
|
|
compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm";
|
|
reg = <0x0 0x0ae97000 0x0 0x200>,
|
|
<0x0 0x0ae97200 0x0 0x300>,
|
|
<0x0 0x0ae97500 0x0 0x400>;
|
|
reg-names = "dsi_phy",
|
|
"dsi_phy_lane",
|
|
"dsi_pll";
|
|
|
|
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
|
<&bi_tcxo_div2>;
|
|
clock-names = "iface",
|
|
"ref";
|
|
|
|
#clock-cells = <1>;
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
mdss_dp0: displayport-controller@af54000 {
|
|
compatible = "qcom,eliza-dp", "qcom,sm8650-dp";
|
|
reg = <0x0 0x0af54000 0x0 0x200>,
|
|
<0x0 0x0af54200 0x0 0x200>,
|
|
<0x0 0x0af55000 0x0 0xc00>,
|
|
<0x0 0x0af56000 0x0 0x400>,
|
|
<0x0 0x0af57000 0x0 0x400>,
|
|
<0x0 0x0af58000 0x0 0x400>,
|
|
<0x0 0x0af59000 0x0 0x400>,
|
|
<0x0 0x0af5a000 0x0 0x600>,
|
|
<0x0 0x0af5b000 0x0 0x600>;
|
|
|
|
interrupts-extended = <&mdss 12>;
|
|
|
|
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
|
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
|
|
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
|
|
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
|
|
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
|
|
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
|
|
clock-names = "core_iface",
|
|
"core_aux",
|
|
"ctrl_link",
|
|
"ctrl_link_iface",
|
|
"stream_pixel",
|
|
"stream_1_pixel";
|
|
|
|
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
|
|
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
|
|
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
|
|
assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
|
|
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
|
|
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
|
|
|
|
operating-points-v2 = <&dp_opp_table>;
|
|
|
|
power-domains = <&rpmhpd RPMHPD_CX>;
|
|
|
|
phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
|
|
phy-names = "dp";
|
|
|
|
#sound-dai-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
dp_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-270000000 {
|
|
opp-hz = /bits/ 64 <270000000>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
};
|
|
|
|
opp-540000000 {
|
|
opp-hz = /bits/ 64 <540000000>;
|
|
required-opps = <&rpmhpd_opp_svs_l1>;
|
|
};
|
|
|
|
opp-810000000 {
|
|
opp-hz = /bits/ 64 <810000000>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
};
|
|
};
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
mdss_dp0_in: endpoint {
|
|
remote-endpoint = <&dpu_intf0_out>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
mdss_dp0_out: endpoint {
|
|
data-lanes = <0 1 2 3>;
|
|
remote-endpoint = <&usb_dp_qmpphy_dp_in>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
dispcc: clock-controller@af00000 {
|
|
compatible = "qcom,eliza-dispcc";
|
|
reg = <0x0 0x0af00000 0x0 0x20000>;
|
|
|
|
clocks = <&bi_tcxo_div2>,
|
|
<&bi_tcxo_ao_div2>,
|
|
<&gcc GCC_DISP_AHB_CLK>,
|
|
<&sleep_clk>,
|
|
<&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
|
|
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
|
|
<&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
|
|
<&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>,
|
|
<&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
|
|
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
|
|
<0>, /* dp1 */
|
|
<0>,
|
|
<0>, /* dp2 */
|
|
<0>,
|
|
<0>, /* dp3 */
|
|
<0>,
|
|
<0>; /* HDMI phy */
|
|
|
|
power-domains = <&rpmhpd RPMHPD_MX>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
lpass_ag_noc: interconnect@7e40000 {
|
|
compatible = "qcom,eliza-lpass-ag-noc";
|
|
reg = <0x0 0x07e40000 0x0 0xe080>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
#interconnect-cells = <2>;
|
|
};
|
|
|
|
pdc: interrupt-controller@b220000 {
|
|
compatible = "qcom,eliza-pdc", "qcom,pdc";
|
|
reg = <0x0 0x0b220000 0x0 0x40000>,
|
|
<0x0 0x174000f0 0x0 0x64>;
|
|
|
|
qcom,pdc-ranges = <0 480 8>, <8 719 1>, <9 718 1>,
|
|
<10 230 1>, <11 724 1>, <12 716 1>,
|
|
<13 727 1>, <14 720 1>, <15 726 1>,
|
|
<16 721 1>, <17 262 1>, <18 70 1>,
|
|
<19 723 1>, <20 234 1>, <22 725 1>,
|
|
<23 231 1>, <24 504 5>, <30 510 8>,
|
|
<40 520 6>, <51 531 4>, <58 538 2>,
|
|
<61 541 5>, <66 92 1>, <67 547 13>,
|
|
<80 240 1>, <81 235 1>, <82 310 2>,
|
|
<84 248 1>, <85 241 1>, <86 238 2>,
|
|
<88 254 1>, <89 509 1>, <90 563 1>,
|
|
<91 259 2>, <93 201 1>, <94 246 1>,
|
|
<95 93 1>, <96 611 29>, <125 63 1>,
|
|
<126 366 2>, <128 374 1>, <129 377 1>,
|
|
<130 428 1>, <131 434 2>, <133 437 1>,
|
|
<134 452 2>, <136 458 2>, <138 464 11>,
|
|
<149 671 1>, <150 688 1>, <151 714 2>,
|
|
<153 722 1>, <154 255 1>, <155 269 2>,
|
|
<157 276 1>, <158 287 1>, <159 306 4>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
tsens0: thermal-sensor@c228000 {
|
|
compatible = "qcom,eliza-tsens", "qcom,tsens-v2";
|
|
reg = <0x0 0x0c228000 0x0 0x1000>,
|
|
<0x0 0x0c222000 0x0 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "uplow",
|
|
"critical";
|
|
|
|
#qcom,sensors = <13>;
|
|
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
tsens1: thermal-sensor@c229000 {
|
|
compatible = "qcom,eliza-tsens", "qcom,tsens-v2";
|
|
reg = <0x0 0x0c229000 0x0 0x1000>,
|
|
<0x0 0x0c223000 0x0 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "uplow",
|
|
"critical";
|
|
|
|
#qcom,sensors = <14>;
|
|
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
tsens2: thermal-sensor@c22a000 {
|
|
compatible = "qcom,eliza-tsens", "qcom,tsens-v2";
|
|
reg = <0x0 0x0c22a000 0x0 0x1000>,
|
|
<0x0 0x0c224000 0x0 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "uplow",
|
|
"critical";
|
|
|
|
#qcom,sensors = <5>;
|
|
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
aoss_qmp: power-management@c300000 {
|
|
compatible = "qcom,eliza-aoss-qmp", "qcom,aoss-qmp";
|
|
reg = <0x0 0x0c300000 0x0 0x400>;
|
|
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
spmi: arbiter@c400000 {
|
|
compatible = "qcom,eliza-spmi-pmic-arb",
|
|
"qcom,x1e80100-spmi-pmic-arb";
|
|
reg = <0x0 0x0c400000 0x0 0x3000>,
|
|
<0x0 0x0c500000 0x0 0x400000>,
|
|
<0x0 0x0c440000 0x0 0x80000>;
|
|
reg-names = "core",
|
|
"chnls",
|
|
"obsrvr";
|
|
|
|
qcom,ee = <0>;
|
|
qcom,channel = <0>;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
spmi_bus0: spmi@c42d000 {
|
|
reg = <0x0 0x0c42d000 0x0 0x4000>,
|
|
<0x0 0x0c4c0000 0x0 0x10000>;
|
|
reg-names = "cnfg",
|
|
"intr";
|
|
|
|
interrupt-names = "periph_irq";
|
|
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
spmi_bus1: spmi@c432000 {
|
|
reg = <0x0 0x0c432000 0x0 0x4000>,
|
|
<0x0 0x0c4d0000 0x0 0x10000>;
|
|
reg-names = "cnfg",
|
|
"intr";
|
|
|
|
interrupt-names = "periph_irq";
|
|
interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
tlmm: pinctrl@f100000 {
|
|
compatible = "qcom,eliza-tlmm";
|
|
reg = <0x0 0x0f100000 0x0 0xf00000>;
|
|
|
|
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
gpio-ranges = <&tlmm 0 0 184>;
|
|
wakeup-parent = <&pdc>;
|
|
|
|
qup_i2c0_data_clk: qup-i2c0-data-clk-state {
|
|
pins = "gpio28", "gpio29";
|
|
function = "qup1_se0";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_spi0_cs: qup-spi0-cs-state {
|
|
pins = "gpio31";
|
|
function = "qup1_se0";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi0_data_clk: qup-spi0-data-clk-state {
|
|
/* MISO, MOSI, CLK */
|
|
pins = "gpio28", "gpio29", "gpio30";
|
|
function = "qup1_se0";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_i2c1_data_clk: qup-i2c1-data-clk-state {
|
|
pins = "gpio32", "gpio33";
|
|
function = "qup1_se1";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_spi1_cs: qup-spi1-cs-state {
|
|
pins = "gpio35";
|
|
function = "qup1_se1";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi1_data_clk: qup-spi1-data-clk-state {
|
|
/* MISO, MOSI, CLK */
|
|
pins = "gpio32", "gpio33", "gpio34";
|
|
function = "qup1_se1";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_i2c2_data_clk: qup-i2c2-data-clk-state {
|
|
pins = "gpio52", "gpio53";
|
|
function = "qup1_se2";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_spi2_cs: qup-spi2-cs-state {
|
|
pins = "gpio55";
|
|
function = "qup1_se2";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi2_data_clk: qup-spi2-data-clk-state {
|
|
/* MISO, MOSI, CLK */
|
|
pins = "gpio52", "gpio53", "gpio54";
|
|
function = "qup1_se2";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_i2c3_data_clk: qup-i2c3-data-clk-state {
|
|
pins = "gpio44", "gpio45";
|
|
function = "qup1_se3";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_spi3_cs: qup-spi3-cs-state {
|
|
pins = "gpio47";
|
|
function = "qup1_se3";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi3_data_clk: qup-spi3-data-clk-state {
|
|
/* MISO, MOSI, CLK */
|
|
pins = "gpio44", "gpio45", "gpio46";
|
|
function = "qup1_se3";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_i2c4_data_clk: qup-i2c4-data-clk-state {
|
|
pins = "gpio36", "gpio37";
|
|
function = "qup1_se4_01";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_spi4_clk: qup-spi4-clk-state {
|
|
pins = "gpio37";
|
|
function = "qup1_se4_23";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi4_cs: qup-spi4-cs-state {
|
|
pins = "gpio36";
|
|
function = "qup1_se4_23";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi4_data: qup-spi4-data-state {
|
|
pins = "gpio36", "gpio37";
|
|
function = "qup1_se4_01";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_uart5_default: qup-uart5-default-state {
|
|
/* TX, RX */
|
|
pins = "gpio134", "gpio135";
|
|
function = "qup1_se5";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_uart5_cts_rts: qup-uart5-cts-rts-state {
|
|
/* CTS, RTS */
|
|
pins = "gpio132", "gpio133";
|
|
function = "qup1_se5";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
qup_uart6_default: qup-uart6-default-state {
|
|
/* TX, RX */
|
|
pins = "gpio42", "gpio40";
|
|
function = "qup1_se6";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_uart6_cts_rts: qup-uart6-cts-rts-state {
|
|
/* CTS, RTS */
|
|
pins = "gpio40", "gpio42";
|
|
function = "qup1_se6";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
|
|
qup_i2c7_data_clk: qup-i2c7-data-clk-state {
|
|
pins = "gpio81", "gpio80";
|
|
function = "qup1_se7";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_spi7_cs: qup-spi7-cs-state {
|
|
pins = "gpio78";
|
|
function = "qup1_se7";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi7_data_clk: qup-spi7-data-clk-state {
|
|
pins = "gpio81", "gpio80", "gpio114";
|
|
function = "qup1_se7";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_i2c8_data_clk: qup-i2c8-data-clk-state {
|
|
pins = "gpio0", "gpio1";
|
|
function = "qup2_se0";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_spi8_cs: qup-spi8-cs-state {
|
|
pins = "gpio3";
|
|
function = "qup2_se0";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi8_data_clk: qup-spi8-data-clk-state {
|
|
pins = "gpio0", "gpio1", "gpio2";
|
|
function = "qup2_se0";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_i2c9_data_clk: qup-i2c9-data-clk-state {
|
|
pins = "gpio4", "gpio5";
|
|
function = "qup2_se1";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_spi9_cs: qup-spi9-cs-state {
|
|
pins = "gpio7";
|
|
function = "qup2_se1";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi9_data_clk: qup-spi9-data-clk-state {
|
|
pins = "gpio4", "gpio5", "gpio6";
|
|
function = "qup2_se1";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_i2c10_data_clk: qup-i2c10-data-clk-state {
|
|
pins = "gpio8", "gpio9";
|
|
function = "qup2_se2";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_spi10_cs: qup-spi10-cs-state {
|
|
pins = "gpio11";
|
|
function = "qup2_se2";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi10_data_clk: qup-spi10-data-clk-state {
|
|
pins = "gpio8", "gpio9", "gpio10";
|
|
function = "qup2_se2";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_i2c11_data_clk: qup-i2c11-data-clk-state {
|
|
pins = "gpio79", "gpio97";
|
|
function = "qup2_se3";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_spi11_cs: qup-spi11-cs-state {
|
|
pins = "gpio116";
|
|
function = "qup2_se3";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi11_data_clk: qup-spi11-data-clk-state {
|
|
pins = "gpio79", "gpio97", "gpio100";
|
|
function = "qup2_se3";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_i2c12_data_clk: qup-i2c12-data-clk-state {
|
|
pins = "gpio12", "gpio13";
|
|
function = "qup2_se4";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_spi12_cs: qup-spi12-cs-state {
|
|
pins = "gpio27";
|
|
function = "qup2_se4";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi12_data_clk: qup-spi12-data-clk-state {
|
|
pins = "gpio12", "gpio13", "gpio26";
|
|
function = "qup2_se4";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_uart13_default: qup-uart13-default-state {
|
|
/* TX, RX */
|
|
pins = "gpio18", "gpio19";
|
|
function = "qup2_se5";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_i2c14_data_clk: qup-i2c14-data-clk-state {
|
|
pins = "gpio20", "gpio21";
|
|
function = "qup2_se6";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_spi14_cs: qup-spi14-cs-state {
|
|
pins = "gpio23";
|
|
function = "qup2_se6";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi14_data_clk: qup-spi14-data-clk-state {
|
|
/* MISO, MOSI, CLK */
|
|
pins = "gpio20", "gpio21", "gpio22";
|
|
function = "qup2_se6";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_i2c15_data_clk: qup-i2c15-data-clk-state {
|
|
pins = "gpio27", "gpio26";
|
|
function = "qup2_se7";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
qup_spi15_cs: qup-spi15-cs-state {
|
|
pins = "gpio12";
|
|
function = "qup2_se7";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
qup_spi15_data_clk: qup-spi15-data-clk-state {
|
|
/* MISO, MOSI, CLK */
|
|
pins = "gpio27", "gpio26", "gpio13";
|
|
function = "qup2_se7";
|
|
drive-strength = <6>;
|
|
bias-disable;
|
|
};
|
|
|
|
sdc1_default: sdc1-default-state {
|
|
clk-pins {
|
|
pins = "gpio121";
|
|
function = "sdc1";
|
|
drive-strength = <12>;
|
|
bias-disable;
|
|
};
|
|
|
|
cmd-pins {
|
|
pins = "gpio123";
|
|
function = "sdc1";
|
|
drive-strength = <12>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
data-pins {
|
|
pins = "gpio124", "gpio125",
|
|
"gpio126", "gpio127",
|
|
"gpio128", "gpio129",
|
|
"gpio130", "gpio131";
|
|
function = "sdc1";
|
|
drive-strength = <12>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
rclk-pins {
|
|
pins = "gpio120";
|
|
function = "sdc1";
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
sdc1_sleep: sdc1-sleep-state {
|
|
clk-pins {
|
|
pins = "gpio121";
|
|
function = "sdc1";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
cmd-pins {
|
|
pins = "gpio123";
|
|
function = "sdc1";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
data-pins {
|
|
pins = "gpio124", "gpio125",
|
|
"gpio126", "gpio127",
|
|
"gpio128", "gpio129",
|
|
"gpio130", "gpio131";
|
|
function = "sdc1";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
rclk-pins {
|
|
pins = "gpio120";
|
|
function = "sdc1";
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
sdc2_default: sdc2-default-state {
|
|
clk-pins {
|
|
pins = "gpio62";
|
|
function = "sdc2";
|
|
drive-strength = <16>;
|
|
bias-disable;
|
|
};
|
|
|
|
cmd-pins {
|
|
pins = "gpio51";
|
|
function = "sdc2";
|
|
drive-strength = <10>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
data-pins {
|
|
pins = "gpio38", "gpio39",
|
|
"gpio48", "gpio49";
|
|
function = "sdc2";
|
|
drive-strength = <10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
sdc2_sleep: sdc2-sleep-state {
|
|
clk-pins {
|
|
pins = "gpio62";
|
|
function = "sdc2";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
cmd-pins {
|
|
pins = "gpio51";
|
|
function = "sdc2";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
|
|
data-pins {
|
|
pins = "gpio38", "gpio39",
|
|
"gpio48", "gpio49";
|
|
function = "sdc2";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
sram@14680000 {
|
|
compatible = "qcom,eliza-imem", "mmio-sram";
|
|
reg = <0x0 0x14680000 0x0 0x2c000>;
|
|
ranges = <0x0 0x0 0x14680000 0x2c000>;
|
|
|
|
no-memory-wc;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
pil-reloc-sram@94c {
|
|
compatible = "qcom,pil-reloc-info";
|
|
reg = <0x94c 0xc8>;
|
|
};
|
|
|
|
ipa_modem_tables: modem-tables-sram@3000 {
|
|
reg = <0x3000 0x2000>;
|
|
};
|
|
};
|
|
|
|
apps_smmu: iommu@15000000 {
|
|
compatible = "qcom,eliza-smmu-500", "qcom,smmu-500", "arm,mmu-500";
|
|
reg = <0x0 0x15000000 0x0 0x100000>;
|
|
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
#iommu-cells = <2>;
|
|
#global-interrupts = <1>;
|
|
|
|
dma-coherent;
|
|
};
|
|
|
|
intc: interrupt-controller@17100000 {
|
|
compatible = "arm,gic-v3";
|
|
reg = <0x0 0x17100000 0x0 0x10000>,
|
|
<0x0 0x17180000 0x0 0x200000>;
|
|
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
|
|
#redistributor-regions = <1>;
|
|
redistributor-stride = <0x0 0x40000>;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
gic_its: msi-controller@17140000 {
|
|
compatible = "arm,gic-v3-its";
|
|
reg = <0x0 0x17140000 0x0 0x40000>;
|
|
|
|
msi-controller;
|
|
#msi-cells = <1>;
|
|
};
|
|
};
|
|
|
|
apps_rsc: rsc@17a00000 {
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0x0 0x17a00000 0x0 0x10000>,
|
|
<0x0 0x17a10000 0x0 0x10000>,
|
|
<0x0 0x17a20000 0x0 0x10000>;
|
|
reg-names = "drv-0",
|
|
"drv-1",
|
|
"drv-2";
|
|
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
power-domains = <&cluster_pd>;
|
|
label = "apps_rsc";
|
|
|
|
qcom,tcs-offset = <0xd00>;
|
|
qcom,drv-id = <2>;
|
|
qcom,tcs-config = <ACTIVE_TCS 3>,
|
|
<SLEEP_TCS 2>,
|
|
<WAKE_TCS 2>,
|
|
<CONTROL_TCS 0>;
|
|
|
|
apps_bcm_voter: bcm-voter {
|
|
compatible = "qcom,bcm-voter";
|
|
};
|
|
|
|
rpmhcc: clock-controller {
|
|
compatible = "qcom,eliza-rpmh-clk";
|
|
#clock-cells = <1>;
|
|
clocks = <&xo_board>;
|
|
clock-names = "xo";
|
|
};
|
|
|
|
rpmhpd: power-controller {
|
|
compatible = "qcom,eliza-rpmhpd";
|
|
|
|
operating-points-v2 = <&rpmhpd_opp_table>;
|
|
|
|
#power-domain-cells = <1>;
|
|
|
|
rpmhpd_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
rpmhpd_opp_ret: opp-16 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
|
};
|
|
|
|
rpmhpd_opp_min_svs: opp-48 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_low_svs_d3: opp-50 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
|
|
};
|
|
|
|
rpmhpd_opp_low_svs_d2: opp-52 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
|
|
};
|
|
|
|
rpmhpd_opp_low_svs_d1: opp-56 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
|
|
};
|
|
|
|
rpmhpd_opp_low_svs_d0: opp-60 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
|
|
};
|
|
|
|
rpmhpd_opp_low_svs: opp-64 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_low_svs_l1: opp-80 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
|
|
};
|
|
|
|
rpmhpd_opp_svs: opp-128 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_svs_l0: opp-144 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
|
|
};
|
|
|
|
rpmhpd_opp_svs_l1: opp-192 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
|
};
|
|
|
|
rpmhpd_opp_svs_l2: opp-224 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
|
|
};
|
|
|
|
rpmhpd_opp_nom: opp-256 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
|
|
};
|
|
|
|
rpmhpd_opp_nom_l1: opp-320 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
|
};
|
|
|
|
rpmhpd_opp_nom_l2: opp-336 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
|
|
};
|
|
|
|
rpmhpd_opp_turbo: opp-384 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
|
};
|
|
|
|
rpmhpd_opp_turbo_l1: opp-416 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
|
};
|
|
|
|
rpmhpd_opp_turbo_l2: opp-432 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
|
|
};
|
|
|
|
rpmhpd_opp_turbo_l3: opp-448 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
|
|
};
|
|
|
|
rpmhpd_opp_turbo_l4: opp-452 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
|
|
};
|
|
|
|
rpmhpd_opp_super_turbo_no_cpr: opp-480 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
epss_l3: interconnect@17d90000 {
|
|
compatible = "qcom,eliza-epss-l3", "qcom,epss-l3";
|
|
reg = <0x0 0x17d90000 0x0 0x1000>;
|
|
|
|
clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
|
|
clock-names = "xo", "alternate";
|
|
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
cpufreq_hw: cpufreq@17d91000 {
|
|
compatible = "qcom,eliza-cpufreq-epss", "qcom,cpufreq-epss";
|
|
reg = <0x0 0x17d91000 0x0 0x1000>,
|
|
<0x0 0x17d92000 0x0 0x1000>,
|
|
<0x0 0x17d93000 0x0 0x1000>;
|
|
reg-names = "freq-domain0",
|
|
"freq-domain1",
|
|
"freq-domain2";
|
|
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "dcvsh-irq-0",
|
|
"dcvsh-irq-1",
|
|
"dcvsh-irq-2";
|
|
|
|
clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
|
|
clock-names = "xo", "alternate";
|
|
|
|
#freq-domain-cells = <1>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
gem_noc: interconnect@24100000 {
|
|
compatible = "qcom,eliza-gem-noc";
|
|
reg = <0x0 0x24100000 0x0 0x163080>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
#interconnect-cells = <2>;
|
|
};
|
|
|
|
system-cache-controller@24800000 {
|
|
compatible = "qcom,eliza-llcc";
|
|
reg = <0x0 0x24800000 0x0 0x200000>,
|
|
<0x0 0x24c00000 0x0 0x200000>,
|
|
<0x0 0x26800000 0x0 0x200000>,
|
|
<0x0 0x26c00000 0x0 0x200000>;
|
|
reg-names = "llcc0_base",
|
|
"llcc2_base",
|
|
"llcc_broadcast_base",
|
|
"llcc_broadcast_and_base";
|
|
|
|
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
nsp_noc: interconnect@320c0000 {
|
|
compatible = "qcom,eliza-nsp-noc";
|
|
reg = <0x0 0x320c0000 0x0 0xe080>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
#interconnect-cells = <2>;
|
|
};
|
|
};
|
|
|
|
thermal-zones {
|
|
aoss0-thermal {
|
|
thermal-sensors = <&tsens0 0>;
|
|
|
|
trips {
|
|
aoss-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
aoss-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
aoss1-thermal {
|
|
thermal-sensors = <&tsens1 0>;
|
|
|
|
trips {
|
|
aoss-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
aoss-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
aoss2-thermal {
|
|
thermal-sensors = <&tsens2 0>;
|
|
|
|
trips {
|
|
aoss-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
aoss-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
camera0-thermal {
|
|
thermal-sensors = <&tsens1 12>;
|
|
|
|
trips {
|
|
camera-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
camera-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
camera1-thermal {
|
|
thermal-sensors = <&tsens1 13>;
|
|
|
|
trips {
|
|
camera-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
camera-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu0-thermal {
|
|
thermal-sensors = <&tsens1 1>;
|
|
|
|
trips {
|
|
cpu-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu1-thermal {
|
|
thermal-sensors = <&tsens1 2>;
|
|
|
|
trips {
|
|
cpu-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu2-thermal {
|
|
thermal-sensors = <&tsens1 3>;
|
|
|
|
trips {
|
|
cpu-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu3-top-thermal {
|
|
thermal-sensors = <&tsens0 3>;
|
|
|
|
trips {
|
|
cpu-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu3-bottom-thermal {
|
|
thermal-sensors = <&tsens0 4>;
|
|
|
|
trips {
|
|
cpu-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu4-top-thermal {
|
|
thermal-sensors = <&tsens0 5>;
|
|
|
|
trips {
|
|
cpu-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu4-bottom-thermal {
|
|
thermal-sensors = <&tsens0 6>;
|
|
|
|
trips {
|
|
cpu-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu5-top-thermal {
|
|
thermal-sensors = <&tsens0 7>;
|
|
|
|
trips {
|
|
cpu-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu5-bottom-thermal {
|
|
thermal-sensors = <&tsens0 8>;
|
|
|
|
trips {
|
|
cpu-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu6-top-thermal {
|
|
thermal-sensors = <&tsens0 9>;
|
|
|
|
trips {
|
|
cpu-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu6-bottom-thermal {
|
|
thermal-sensors = <&tsens0 10>;
|
|
|
|
trips {
|
|
cpu-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu7-top-thermal {
|
|
thermal-sensors = <&tsens0 11>;
|
|
|
|
trips {
|
|
cpu-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu7-bottom-thermal {
|
|
thermal-sensors = <&tsens0 12>;
|
|
|
|
trips {
|
|
cpu-critical {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpuss0-thermal {
|
|
thermal-sensors = <&tsens0 1>;
|
|
|
|
trips {
|
|
cpuss-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
cpuss-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpuss1-thermal {
|
|
thermal-sensors = <&tsens0 2>;
|
|
|
|
trips {
|
|
cpuss-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
cpuss-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
ddr-thermal {
|
|
thermal-sensors = <&tsens1 11>;
|
|
|
|
trips {
|
|
ddr-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
ddr-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss0-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens1 8>;
|
|
|
|
trips {
|
|
gpu-alert {
|
|
temperature = <95000>;
|
|
hysteresis = <1000>;
|
|
type = "passive";
|
|
};
|
|
|
|
gpu-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
gpu-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss1-thermal {
|
|
polling-delay-passive = <10>;
|
|
|
|
thermal-sensors = <&tsens1 9>;
|
|
|
|
trips {
|
|
gpu-alert {
|
|
temperature = <95000>;
|
|
hysteresis = <1000>;
|
|
type = "passive";
|
|
};
|
|
|
|
gpu-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
gpu-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
modem0-thermal {
|
|
thermal-sensors = <&tsens2 1>;
|
|
|
|
trips {
|
|
modem-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
modem-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
modem1-thermal {
|
|
thermal-sensors = <&tsens2 2>;
|
|
|
|
trips {
|
|
modem-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
modem-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
modem2-thermal {
|
|
thermal-sensors = <&tsens2 3>;
|
|
|
|
trips {
|
|
modem-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
modem-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
modem3-thermal {
|
|
thermal-sensors = <&tsens2 4>;
|
|
|
|
trips {
|
|
modem-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
modem-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsphmx0-thermal {
|
|
thermal-sensors = <&tsens1 6>;
|
|
|
|
trips {
|
|
nsphmx-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
nsphmx-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsphmx1-thermal {
|
|
thermal-sensors = <&tsens1 7>;
|
|
|
|
trips {
|
|
nsphmx-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
nsphmx-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsphvx0-thermal {
|
|
thermal-sensors = <&tsens1 4>;
|
|
|
|
trips {
|
|
nsphvx-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
nsphvx-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsphvx1-thermal {
|
|
thermal-sensors = <&tsens1 5>;
|
|
|
|
trips {
|
|
nsphvx-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
nsphvx-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
video-thermal {
|
|
thermal-sensors = <&tsens1 10>;
|
|
|
|
trips {
|
|
video-hot {
|
|
temperature = <110000>;
|
|
hysteresis = <1000>;
|
|
type = "hot";
|
|
};
|
|
|
|
video-critical {
|
|
temperature = <115000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
|
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
};
|