187 lines
4.0 KiB
Devicetree
187 lines
4.0 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0
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/*
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* Realtek Kent SoC family
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*
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* Copyright (c) 2024 Realtek Semiconductor Corp.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &uart0;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a78";
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reg = <0x0>;
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enable-method = "psci";
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next-level-cache = <&l2_0>;
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dynamic-power-coefficient = <454>;
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#cooling-cells = <2>;
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l2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-line-size = <64>;
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cache-sets = <256>;
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cache-size = <0x40000>;
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cache-unified;
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next-level-cache = <&l3>;
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};
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a78";
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reg = <0x100>;
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enable-method = "psci";
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next-level-cache = <&l2_1>;
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dynamic-power-coefficient = <454>;
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#cooling-cells = <2>;
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l2_1: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-line-size = <64>;
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cache-sets = <256>;
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cache-size = <0x40000>;
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cache-unified;
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next-level-cache = <&l3>;
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};
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a78";
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reg = <0x200>;
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enable-method = "psci";
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next-level-cache = <&l2_2>;
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dynamic-power-coefficient = <454>;
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#cooling-cells = <2>;
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l2_2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-line-size = <64>;
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cache-sets = <256>;
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cache-size = <0x40000>;
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cache-unified;
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next-level-cache = <&l3>;
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};
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a78";
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reg = <0x300>;
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enable-method = "psci";
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next-level-cache = <&l2_3>;
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dynamic-power-coefficient = <454>;
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#cooling-cells = <2>;
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l2_3: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-line-size = <64>;
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cache-sets = <256>;
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cache-size = <0x40000>;
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cache-unified;
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next-level-cache = <&l3>;
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};
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};
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l3: l3-cache {
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compatible = "cache";
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cache-level = <3>;
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cache-line-size = <64>;
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cache-sets = <512>;
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cache-size = <0x200000>;
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cache-unified;
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};
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};
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psci: psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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soc@0 {
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compatible = "simple-bus";
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ranges = <0x0 0x0 0x0 0x40000>, /* boot code */
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<0x98000000 0x0 0x98000000 0xef0000>, /* rbus */
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<0xa0000000 0x0 0xa0000000 0x10000000>, /* PCIE */
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<0xff000000 0x0 0xff000000 0x200000>; /* GIC */
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#address-cells = <1>;
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#size-cells = <1>;
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rbus: bus@98000000 {
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compatible = "simple-bus";
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ranges = <0x0 0x98000000 0xef0000>,
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<0xa0000000 0xa0000000 0x10000000>; /* PCIE */
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#address-cells = <1>;
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#size-cells = <1>;
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uart0: serial@7800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x7800 0x100>;
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clock-frequency = <432000000>;
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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iso_pinctrl: pinctrl@4e000 {
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compatible = "realtek,rtd1625-iso-pinctrl";
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reg = <0x4e000 0x1a4>;
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};
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main2_pinctrl: pinctrl@4f200 {
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compatible = "realtek,rtd1625-main2-pinctrl";
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reg = <0x4f200 0x50>;
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};
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isom_pinctrl: pinctrl@146200 {
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compatible = "realtek,rtd1625-isom-pinctrl";
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reg = <0x146200 0x34>;
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};
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ve4_pinctrl: pinctrl@14e000 {
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compatible = "realtek,rtd1625-ve4-pinctrl";
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reg = <0x14e000 0x84>;
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};
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};
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gic: interrupt-controller@ff100000 {
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compatible = "arm,gic-v3";
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reg = <0xff100000 0x10000>,
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<0xff140000 0x80000>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#interrupt-cells = <3>;
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#size-cells = <1>;
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};
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};
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};
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