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ad2088d178afb6207a6760fb70142d87f48aeda4
linux-kernel/linux-7.2.3/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
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lastdragon ad2088d178 Resguardo inicial
2026-09-06 12:53:21 -06:00

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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G3L SoC
*
* Copyright (C) 2026 Renesas Electronics Corp.
*/
#include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "renesas,r9a08g046";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
audio_clk1: audio1-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by boards that provide it. */
clock-frequency = <0>;
};
audio_clk2: audio2-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by boards that provide it. */
clock-frequency = <0>;
};
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-37500000 {
opp-hz = /bits/ 64 <37500000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
opp-75000000 {
opp-hz = /bits/ 64 <75000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
opp-150000000 {
opp-hz = /bits/ 64 <150000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
opp-suspend;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A08G046_CLK_IC0>;
operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@100 {
compatible = "arm,cortex-a55";
reg = <0x100>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A08G046_CLK_IC1>;
operating-points-v2 = <&cluster0_opp>;
};
cpu2: cpu@200 {
compatible = "arm,cortex-a55";
reg = <0x200>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A08G046_CLK_IC2>;
operating-points-v2 = <&cluster0_opp>;
};
cpu3: cpu@300 {
compatible = "arm,cortex-a55";
reg = <0x300>;
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A08G046_CLK_IC3>;
operating-points-v2 = <&cluster0_opp>;
};
L3_CA55: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-size = <0x80000>;
cache-level = <3>;
};
};
eth0_txc_tx_clk: eth0-txc-tx-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
eth0_rxc_rx_clk: eth0-rxc-rx-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
eth1_txc_tx_clk: eth1-txc-tx-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
eth1_rxc_rx_clk: eth1-rxc-rx-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
extal_clk: extal-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
scif0: serial@100ac000 {
compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044";
reg = <0 0x100ac000 0 0x400>;
interrupts = <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A08G046_SCIF0_CLK_PCK>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A08G046_SCIF0_RST_SYSTEM_N>;
status = "disabled";
};
scif1: serial@100ac400 {
compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044";
reg = <0 0x100ac400 0 0x400>;
interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A08G046_SCIF1_CLK_PCK>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A08G046_SCIF1_RST_SYSTEM_N>;
status = "disabled";
};
scif2: serial@1004c000 {
compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044";
reg = <0 0x1004c000 0 0x400>;
interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A08G046_SCIF2_CLK_PCK>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A08G046_SCIF2_RST_SYSTEM_N>;
status = "disabled";
};
scif3: serial@1004c400 {
compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044";
reg = <0 0x1004c400 0 0x400>;
interrupts = <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A08G046_SCIF3_CLK_PCK>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A08G046_SCIF3_RST_SYSTEM_N>;
status = "disabled";
};
scif4: serial@1004c800 {
compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044";
reg = <0 0x1004c800 0 0x400>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A08G046_SCIF4_CLK_PCK>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A08G046_SCIF4_RST_SYSTEM_N>;
status = "disabled";
};
scif5: serial@1004e000 {
compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044";
reg = <0 0x1004e000 0 0x400>;
interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A08G046_SCIF5_CLK_PCK>;
clock-names = "fck";
power-domains = <&cpg>;
resets = <&cpg R9A08G046_SCIF5_RST_SYSTEM_N>;
status = "disabled";
};
i2c0: i2c@100ae000 {
compatible = "renesas,riic-r9a08g046", "renesas,riic-r9a09g057";
reg = <0 0x100ae000 0 0x400>;
interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 329 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A08G046_I2C0_PCLK>;
clock-frequency = <100000>;
resets = <&cpg R9A08G046_I2C0_MRST>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@10090400 {
compatible = "renesas,riic-r9a08g046", "renesas,riic-r9a09g057";
reg = <0 0x10090400 0 0x400>;
interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 337 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A08G046_I2C1_PCLK>;
clock-frequency = <100000>;
resets = <&cpg R9A08G046_I2C1_MRST>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@10090800 {
compatible = "renesas,riic-r9a08g046", "renesas,riic-r9a09g057";
reg = <0 0x10090800 0 0x400>;
interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 345 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A08G046_I2C2_PCLK>;
clock-frequency = <100000>;
resets = <&cpg R9A08G046_I2C2_MRST>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@10090c00 {
compatible = "renesas,riic-r9a08g046", "renesas,riic-r9a09g057";
reg = <0 0x10090c00 0 0x400>;
interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 352 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 353 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A08G046_I2C3_PCLK>;
clock-frequency = <100000>;
resets = <&cpg R9A08G046_I2C3_MRST>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
rsci0: serial@100b8000 {
compatible = "renesas,r9a08g046-rsci";
reg = <0 0x100b8000 0 0x1000>;
interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 417 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 418 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 420 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei",
"aed", "bfd";
clocks = <&cpg CPG_MOD R9A08G046_RSCI0_TCLK>,
<&cpg CPG_MOD R9A08G046_RSCI0_PCLK>;
clock-names = "operation", "bus";
power-domains = <&cpg>;
resets = <&cpg R9A08G046_RSCI0_PRESETN>,
<&cpg R9A08G046_RSCI0_TRESETN>;
reset-names = "presetn", "tresetn";
status = "disabled";
};
rsci1: serial@100f1000 {
compatible = "renesas,r9a08g046-rsci";
reg = <0 0x100f1000 0 0x1000>;
interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 423 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 424 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 426 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei",
"aed", "bfd";
clocks = <&cpg CPG_MOD R9A08G046_RSCI1_TCLK>,
<&cpg CPG_MOD R9A08G046_RSCI1_PCLK>;
clock-names = "operation", "bus";
power-domains = <&cpg>;
resets = <&cpg R9A08G046_RSCI1_PRESETN>,
<&cpg R9A08G046_RSCI1_TRESETN>;
reset-names = "presetn", "tresetn";
status = "disabled";
};
rsci2: serial@100f2000 {
compatible = "renesas,r9a08g046-rsci";
reg = <0 0x100f2000 0 0x1000>;
interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 429 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 430 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 432 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei",
"aed", "bfd";
clocks = <&cpg CPG_MOD R9A08G046_RSCI2_TCLK>,
<&cpg CPG_MOD R9A08G046_RSCI2_PCLK>;
clock-names = "operation", "bus";
power-domains = <&cpg>;
resets = <&cpg R9A08G046_RSCI2_PRESETN>,
<&cpg R9A08G046_RSCI2_TRESETN>;
reset-names = "presetn", "tresetn";
status = "disabled";
};
rsci3: serial@100f3000 {
compatible = "renesas,r9a08g046-rsci";
reg = <0 0x100f3000 0 0x1000>;
interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 435 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 438 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei",
"aed", "bfd";
clocks = <&cpg CPG_MOD R9A08G046_RSCI3_TCLK>,
<&cpg CPG_MOD R9A08G046_RSCI3_PCLK>;
clock-names = "operation", "bus";
power-domains = <&cpg>;
resets = <&cpg R9A08G046_RSCI3_PRESETN>,
<&cpg R9A08G046_RSCI3_TRESETN>;
reset-names = "presetn", "tresetn";
status = "disabled";
};
canfd: can@100c0000 {
reg = <0 0x100c0000 0 0x20000>;
/* placeholder */
};
ssi0: ssi@100e4000 {
compatible = "renesas,r9a08g046-ssi", "renesas,rz-ssi";
reg = <0 0x100e4000 0 0x400>;
interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A08G046_SSI0_PCLK2>,
<&cpg CPG_MOD R9A08G046_SSI0_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
resets = <&cpg R9A08G046_SSI0_RST_M2_REG>;
dmas = <&dmac 0x2665>, <&dmac 0x2666>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
#sound-dai-cells = <0>;
status = "disabled";
};
ssi1: ssi@100e4400 {
compatible = "renesas,r9a08g046-ssi", "renesas,rz-ssi";
reg = <0 0x100e4400 0 0x400>;
interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 310 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A08G046_SSI1_PCLK2>,
<&cpg CPG_MOD R9A08G046_SSI1_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
resets = <&cpg R9A08G046_SSI1_RST_M2_REG>;
dmas = <&dmac 0x2669>, <&dmac 0x266a>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
#sound-dai-cells = <0>;
status = "disabled";
};
ssi2: ssi@100e4800 {
compatible = "renesas,r9a08g046-ssi", "renesas,rz-ssi";
reg = <0 0x100e4800 0 0x400>;
interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 312 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 313 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A08G046_SSI2_PCLK2>,
<&cpg CPG_MOD R9A08G046_SSI2_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
resets = <&cpg R9A08G046_SSI2_RST_M2_REG>;
dmas = <&dmac 0x266d>, <&dmac 0x266e>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
#sound-dai-cells = <0>;
status = "disabled";
};
ssi3: ssi@100e4c00 {
compatible = "renesas,r9a08g046-ssi", "renesas,rz-ssi";
reg = <0 0x100e4c00 0 0x400>;
interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 316 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx";
clocks = <&cpg CPG_MOD R9A08G046_SSI3_PCLK2>,
<&cpg CPG_MOD R9A08G046_SSI3_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
resets = <&cpg R9A08G046_SSI3_RST_M2_REG>;
dmas = <&dmac 0x2671>, <&dmac 0x2672>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
#sound-dai-cells = <0>;
status = "disabled";
};
cpg: clock-controller@11010000 {
compatible = "renesas,r9a08g046-cpg";
reg = <0 0x11010000 0 0x10000>;
clocks = <&extal_clk>,
<&eth0_txc_tx_clk>, <&eth0_rxc_rx_clk>,
<&eth1_txc_tx_clk>, <&eth1_rxc_rx_clk>;
clock-names = "extal",
"eth0_txc_tx_clk", "eth0_rxc_rx_clk",
"eth1_txc_tx_clk", "eth1_rxc_rx_clk";
#clock-cells = <2>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
sysc: system-controller@11020000 {
compatible = "renesas,r9a08g046-sysc";
reg = <0 0x11020000 0 0x10000>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "lpm_int", "ca55stbydone_int",
"cm33stbyr_int", "ca55_deny";
};
pinctrl: pinctrl@11030000 {
compatible = "renesas,r9a08g046-pinctrl";
reg = <0 0x11030000 0 0x10000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 232>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&icu>;
clocks = <&cpg CPG_MOD R9A08G046_GPIO_HCLK>;
power-domains = <&cpg>;
resets = <&cpg R9A08G046_GPIO_RSTN>,
<&cpg R9A08G046_GPIO_PORT_RESETN>,
<&cpg R9A08G046_GPIO_SPARE_RESETN>;
reset-names = "rstn", "port", "spare";
renesas,clonech = <&sysc 0xe2c>;
};
icu: interrupt-controller@11050000 {
compatible = "renesas,r9a08g046-irqc";
#interrupt-cells = <2>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0x11050000 0 0x10000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "nmi",
"irq0", "irq1", "irq2", "irq3",
"irq4", "irq5", "irq6", "irq7",
"irq8", "irq9", "irq10", "irq11",
"irq12", "irq13", "irq14", "irq15",
"tint0", "tint1", "tint2", "tint3",
"tint4", "tint5", "tint6", "tint7",
"tint8", "tint9", "tint10", "tint11",
"tint12", "tint13", "tint14", "tint15",
"tint16", "tint17", "tint18", "tint19",
"tint20", "tint21", "tint22", "tint23",
"tint24", "tint25", "tint26", "tint27",
"tint28", "tint29", "tint30", "tint31",
"bus-err", "ec7tie1-0", "ec7tie2-0", "ec7tiovf-0",
"ovfunf0", "ovfunf1", "ovfunf2", "ovfunf3",
"ovfunf4", "ovfunf5", "ovfunf6", "ovfunf7";
clocks = <&cpg CPG_MOD R9A08G046_IA55_CLK>,
<&cpg CPG_MOD R9A08G046_IA55_PCLK>;
clock-names = "clk", "pclk";
power-domains = <&cpg>;
resets = <&cpg R9A08G046_IA55_RESETN>;
};
dmac: dma-controller@11820000 {
compatible = "renesas,r9a08g046-dmac", "renesas,rz-dmac";
reg = <0 0x11820000 0 0x10000>,
<0 0x11830000 0 0x10000>;
interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 154 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 155 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 156 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 157 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 160 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 161 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 163 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 164 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 165 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 168 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD R9A08G046_DMAC_ACLK>,
<&cpg CPG_MOD R9A08G046_DMAC_PCLK>;
clock-names = "main", "register";
power-domains = <&cpg>;
resets = <&cpg R9A08G046_DMAC_ARESETN>,
<&cpg R9A08G046_DMAC_RST_ASYNC>;
reset-names = "arst", "rst_async";
#dma-cells = <1>;
dma-channels = <16>;
};
sdhi1: mmc@11c10000 {
reg = <0x0 0x11c10000 0 0x10000>;
/* placeholder */
};
eth0: ethernet@11c30000 {
compatible = "renesas,r9a08g046-gbeth", "snps,dwmac-5.30a";
reg = <0 0x11c30000 0 0x10000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 86 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 87 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 88 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 81 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 82 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 83 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 84 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 90 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 91 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 92 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
"rx-queue-0", "rx-queue-1", "rx-queue-2",
"rx-queue-3", "tx-queue-0", "tx-queue-1",
"tx-queue-2", "tx-queue-3", "ptp-pps-0",
"ptp-pps-1", "ptp-pps-2", "ptp-pps-3";
clocks = <&cpg CPG_MOD R9A08G046_ETH0_CLK_AXI>,
<&cpg CPG_MOD R9A08G046_ETH0_CLK_CHI>,
<&cpg CPG_MOD R9A08G046_ETH0_CLK_PTP_REF_I>,
<&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_I>,
<&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_I>,
<&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_180_I>,
<&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_180_I>,
<&cpg CPG_MOD R9A08G046_ETH0_CLK_RMII_I>,
<&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_I_RMII>,
<&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_I_RMII>;
clock-names = "stmmaceth", "pclk", "ptp_ref",
"tx", "rx", "tx-180", "rx-180",
"rmii", "rmii_tx", "rmii_rx";
resets = <&cpg R9A08G046_ETH0_ARESET_N>;
power-domains = <&cpg>;
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
rx-fifo-depth = <8192>;
tx-fifo-depth = <8192>;
snps,fixed-burst;
snps,no-pbl-x8;
snps,force_thresh_dma_mode;
snps,axi-config = <&stmmac_axi_setup>;
snps,mtl-rx-config = <&mtl_rx_setup0>;
snps,mtl-tx-config = <&mtl_tx_setup0>;
snps,txpbl = <32>;
snps,rxpbl = <32>;
status = "disabled";
mdio0: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
mtl_rx_setup0: rx-queues-config {
snps,rx-queues-to-use = <4>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,priority = <0x1>;
snps,map-to-dma-channel = <0>;
};
queue1 {
snps,dcb-algorithm;
snps,priority = <0x2>;
snps,map-to-dma-channel = <1>;
};
queue2 {
snps,dcb-algorithm;
snps,priority = <0x4>;
snps,map-to-dma-channel = <2>;
};
queue3 {
snps,dcb-algorithm;
snps,priority = <0x8>;
snps,map-to-dma-channel = <3>;
};
};
mtl_tx_setup0: tx-queues-config {
snps,tx-queues-to-use = <4>;
snps,tx-sched-wrr;
queue0 {
snps,weight = <0x10>;
snps,dcb-algorithm;
snps,priority = <0x1>;
};
queue1 {
snps,weight = <0x12>;
snps,dcb-algorithm;
snps,priority = <0x2>;
};
queue2 {
snps,weight = <0x14>;
snps,dcb-algorithm;
snps,priority = <0x4>;
};
queue3 {
snps,weight = <0x18>;
snps,dcb-algorithm;
snps,priority = <0x8>;
};
};
};
eth1: ethernet@11c40000 {
compatible = "renesas,r9a08g046-gbeth", "snps,dwmac-5.30a";
reg = <0 0x11c40000 0 0x10000>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 101 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 102 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 103 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 96 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 97 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 98 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 99 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 104 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 105 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 106 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 107 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi",
"rx-queue-0", "rx-queue-1", "rx-queue-2",
"rx-queue-3", "tx-queue-0", "tx-queue-1",
"tx-queue-2", "tx-queue-3", "ptp-pps-0",
"ptp-pps-1", "ptp-pps-2", "ptp-pps-3";
clocks = <&cpg CPG_MOD R9A08G046_ETH1_CLK_AXI>,
<&cpg CPG_MOD R9A08G046_ETH1_CLK_CHI>,
<&cpg CPG_MOD R9A08G046_ETH1_CLK_PTP_REF_I>,
<&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_I>,
<&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_I>,
<&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_180_I>,
<&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_180_I>,
<&cpg CPG_MOD R9A08G046_ETH1_CLK_RMII_I>,
<&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_I_RMII>,
<&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_I_RMII>;
clock-names = "stmmaceth", "pclk", "ptp_ref",
"tx", "rx", "tx-180", "rx-180",
"rmii", "rmii_tx", "rmii_rx";
resets = <&cpg R9A08G046_ETH1_ARESET_N>;
power-domains = <&cpg>;
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
rx-fifo-depth = <8192>;
tx-fifo-depth = <8192>;
snps,fixed-burst;
snps,no-pbl-x8;
snps,force_thresh_dma_mode;
snps,axi-config = <&stmmac_axi_setup>;
snps,mtl-rx-config = <&mtl_rx_setup1>;
snps,mtl-tx-config = <&mtl_tx_setup1>;
snps,txpbl = <32>;
snps,rxpbl = <32>;
status = "disabled";
mdio1: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
mtl_rx_setup1: rx-queues-config {
snps,rx-queues-to-use = <4>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,priority = <0x1>;
snps,map-to-dma-channel = <0>;
};
queue1 {
snps,dcb-algorithm;
snps,priority = <0x2>;
snps,map-to-dma-channel = <1>;
};
queue2 {
snps,dcb-algorithm;
snps,priority = <0x4>;
snps,map-to-dma-channel = <2>;
};
queue3 {
snps,dcb-algorithm;
snps,priority = <0x8>;
snps,map-to-dma-channel = <3>;
};
};
mtl_tx_setup1: tx-queues-config {
snps,tx-queues-to-use = <4>;
snps,tx-sched-wrr;
queue0 {
snps,weight = <0x10>;
snps,dcb-algorithm;
snps,priority = <0x1>;
};
queue1 {
snps,weight = <0x12>;
snps,dcb-algorithm;
snps,priority = <0x2>;
};
queue2 {
snps,weight = <0x14>;
snps,dcb-algorithm;
snps,priority = <0x4>;
};
queue3 {
snps,weight = <0x18>;
snps,dcb-algorithm;
snps,priority = <0x8>;
};
};
};
pcie: pcie@11e40000 {
reg = <0 0x11e40000 0 0x10000>;
ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
/* placeholder */
pcie_port0: pcie@0,0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
ranges;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
/* placeholder */
};
};
gic: interrupt-controller@12400000 {
compatible = "arm,gic-v3";
reg = <0x0 0x12400000 0 0x20000>,
<0x0 0x12440000 0 0x80000>;
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
wdt0: watchdog@12800800 {
compatible = "renesas,r9a08g046-wdt", "renesas,rzg2l-wdt";
reg = <0 0x12800800 0 0x400>;
clocks = <&cpg CPG_MOD R9A08G046_WDT0_PCLK>,
<&cpg CPG_MOD R9A08G046_WDT0_CLK>;
clock-names = "pclk", "oscclk";
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A08G046_WDT0_PRESETN>;
power-domains = <&cpg>;
status = "disabled";
};
};
stmmac_axi_setup: stmmac-axi-config {
snps,lpi_en;
snps,wr_osr_lmt = <0xf>;
snps,rd_osr_lmt = <0xf>;
snps,blen = <16 8 4 0 0 0 0>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
};
};
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