495 lines
13 KiB
Devicetree
495 lines
13 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
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*/
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/dts-v1/;
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#include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
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#include <dt-bindings/clock/sophgo,sg2042-pll.h>
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#include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/pinctrl-sg2042.h>
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#include <dt-bindings/reset/sophgo,sg2042-reset.h>
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#include "sg2042-cpus.dtsi"
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/ {
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compatible = "sophgo,sg2042";
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#address-cells = <2>;
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#size-cells = <2>;
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dma-noncoherent;
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distance-map {
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compatible = "numa-distance-map-v1";
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distance-matrix = <0 0 10>,
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<0 1 15>,
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<0 2 25>,
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<0 3 30>,
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<1 0 15>,
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<1 1 10>,
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<1 2 30>,
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<1 3 25>,
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<2 0 25>,
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<2 1 30>,
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<2 2 10>,
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<2 3 15>,
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<3 0 30>,
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<3 1 25>,
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<3 2 15>,
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<3 3 10>;
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};
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aliases {
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serial0 = &uart0;
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};
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cgi_main: oscillator0 {
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compatible = "fixed-clock";
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clock-output-names = "cgi_main";
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#clock-cells = <0>;
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};
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cgi_dpll0: oscillator1 {
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compatible = "fixed-clock";
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clock-output-names = "cgi_dpll0";
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#clock-cells = <0>;
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};
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cgi_dpll1: oscillator2 {
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compatible = "fixed-clock";
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clock-output-names = "cgi_dpll1";
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#clock-cells = <0>;
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&intc>;
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ranges;
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spifmc0: spi@7000180000 {
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compatible = "sophgo,sg2042-spifmc-nor";
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reg = <0x70 0x00180000 0x0 0x1000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clkgen GATE_CLK_AHB_SF>;
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interrupt-parent = <&intc>;
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interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rstgen RST_SF0>;
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status = "disabled";
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};
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spifmc1: spi@7002180000 {
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compatible = "sophgo,sg2042-spifmc-nor";
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reg = <0x70 0x02180000 0x0 0x1000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clkgen GATE_CLK_AHB_SF>;
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interrupt-parent = <&intc>;
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interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rstgen RST_SF1>;
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status = "disabled";
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};
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i2c0: i2c@7030005000 {
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compatible = "snps,designware-i2c";
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reg = <0x70 0x30005000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clkgen GATE_CLK_APB_I2C>;
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clock-names = "ref";
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clock-frequency = <100000>;
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interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rstgen RST_I2C0>;
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status = "disabled";
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};
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i2c1: i2c@7030006000 {
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compatible = "snps,designware-i2c";
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reg = <0x70 0x30006000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clkgen GATE_CLK_APB_I2C>;
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clock-names = "ref";
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clock-frequency = <100000>;
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interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rstgen RST_I2C1>;
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status = "disabled";
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};
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i2c2: i2c@7030007000 {
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compatible = "snps,designware-i2c";
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reg = <0x70 0x30007000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clkgen GATE_CLK_APB_I2C>;
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clock-names = "ref";
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clock-frequency = <100000>;
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interrupts = <103 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rstgen RST_I2C2>;
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status = "disabled";
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};
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i2c3: i2c@7030008000 {
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compatible = "snps,designware-i2c";
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reg = <0x70 0x30008000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clkgen GATE_CLK_APB_I2C>;
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clock-names = "ref";
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clock-frequency = <100000>;
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interrupts = <104 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rstgen RST_I2C3>;
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status = "disabled";
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};
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gpio0: gpio@7030009000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x70 0x30009000 0x0 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clkgen GATE_CLK_APB_GPIO>,
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<&clkgen GATE_CLK_GPIO_DB>;
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clock-names = "bus", "db";
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port0a: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <96 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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gpio1: gpio@703000a000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x70 0x3000a000 0x0 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clkgen GATE_CLK_APB_GPIO>,
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<&clkgen GATE_CLK_GPIO_DB>;
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clock-names = "bus", "db";
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port1a: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <97 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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gpio2: gpio@703000b000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x70 0x3000b000 0x0 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clkgen GATE_CLK_APB_GPIO>,
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<&clkgen GATE_CLK_GPIO_DB>;
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clock-names = "bus", "db";
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port2a: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <98 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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pwm: pwm@703000c000 {
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compatible = "sophgo,sg2042-pwm";
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reg = <0x70 0x3000c000 0x0 0x20>;
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#pwm-cells = <3>;
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clocks = <&clkgen GATE_CLK_APB_PWM>;
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clock-names = "apb";
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resets = <&rstgen RST_PWM>;
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};
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pllclk: clock-controller@70300100c0 {
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compatible = "sophgo,sg2042-pll";
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reg = <0x70 0x300100c0 0x0 0x40>;
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clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>;
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clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1";
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#clock-cells = <1>;
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};
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msi: msi-controller@7030010304 {
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compatible = "sophgo,sg2042-msi";
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reg = <0x70 0x30010304 0x0 0x4>,
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<0x70 0x30010300 0x0 0x4>;
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reg-names = "clr", "doorbell";
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msi-controller;
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#msi-cells = <0>;
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msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 16>;
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};
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rpgate: clock-controller@7030010368 {
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compatible = "sophgo,sg2042-rpgate";
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reg = <0x70 0x30010368 0x0 0x98>;
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clocks = <&clkgen GATE_CLK_RP_CPU_NORMAL>;
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clock-names = "rpgate";
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#clock-cells = <1>;
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};
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pinctrl: pinctrl@7030011000 {
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compatible = "sophgo,sg2042-pinctrl";
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reg = <0x70 0x30011000 0x0 0x1000>;
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};
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clkgen: clock-controller@7030012000 {
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compatible = "sophgo,sg2042-clkgen";
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reg = <0x70 0x30012000 0x0 0x1000>;
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clocks = <&pllclk MPLL_CLK>,
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<&pllclk FPLL_CLK>,
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<&pllclk DPLL0_CLK>,
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<&pllclk DPLL1_CLK>;
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clock-names = "mpll",
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"fpll",
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"dpll0",
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"dpll1";
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#clock-cells = <1>;
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};
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rstgen: reset-controller@7030013000 {
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compatible = "sophgo,sg2042-reset";
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reg = <0x00000070 0x30013000 0x00000000 0x0000000c>;
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#reset-cells = <1>;
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};
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uart0: serial@7040000000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
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interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <500000000>;
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clocks = <&clkgen GATE_CLK_UART_500M>,
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<&clkgen GATE_CLK_APB_UART>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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resets = <&rstgen RST_UART0>;
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status = "disabled";
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};
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spi0: spi@7040004000 {
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compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi";
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reg = <0x70 0x40004000 0x00 0x1000>;
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clocks = <&clkgen GATE_CLK_APB_SPI>;
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interrupt-parent = <&intc>;
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interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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num-cs = <2>;
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resets = <&rstgen RST_SPI0>;
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status = "disabled";
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};
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spi1: spi@7040005000 {
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compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi";
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reg = <0x70 0x40005000 0x00 0x1000>;
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clocks = <&clkgen GATE_CLK_APB_SPI>;
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interrupt-parent = <&intc>;
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interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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num-cs = <2>;
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resets = <&rstgen RST_SPI1>;
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status = "disabled";
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};
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gmac0: ethernet@7040026000 {
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compatible = "sophgo,sg2042-dwmac", "snps,dwmac-5.00a";
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reg = <0x70 0x40026000 0x0 0x4000>;
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clocks = <&clkgen GATE_CLK_AXI_ETH0>,
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<&clkgen GATE_CLK_PTP_REF_I_ETH0>,
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<&clkgen GATE_CLK_TX_ETH0>;
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clock-names = "stmmaceth", "ptp_ref", "tx";
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dma-noncoherent;
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interrupt-parent = <&intc>;
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interrupts = <132 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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resets = <&rstgen RST_ETH0>;
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reset-names = "stmmaceth";
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snps,multicast-filter-bins = <0>;
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snps,perfect-filter-entries = <1>;
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snps,aal;
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snps,tso;
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snps,txpbl = <32>;
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snps,rxpbl = <32>;
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snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
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snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
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snps,axi-config = <&gmac0_stmmac_axi_setup>;
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status = "disabled";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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gmac0_mtl_rx_setup: rx-queues-config {
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snps,rx-queues-to-use = <8>;
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queue0 {};
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queue1 {};
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queue2 {};
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queue3 {};
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queue4 {};
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queue5 {};
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queue6 {};
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queue7 {};
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};
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gmac0_mtl_tx_setup: tx-queues-config {
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snps,tx-queues-to-use = <8>;
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queue0 {};
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queue1 {};
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queue2 {};
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queue3 {};
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queue4 {};
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queue5 {};
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queue6 {};
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queue7 {};
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};
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gmac0_stmmac_axi_setup: stmmac-axi-config {
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snps,blen = <16 8 4 0 0 0 0>;
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snps,wr_osr_lmt = <1>;
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snps,rd_osr_lmt = <2>;
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};
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};
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emmc: mmc@704002a000 {
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compatible = "sophgo,sg2042-dwcmshc";
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reg = <0x70 0x4002a000 0x0 0x1000>;
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interrupt-parent = <&intc>;
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interrupts = <134 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkgen GATE_CLK_EMMC_100M>,
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<&clkgen GATE_CLK_AXI_EMMC>,
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<&clkgen GATE_CLK_100K_EMMC>;
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clock-names = "core",
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"bus",
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"timer";
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status = "disabled";
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};
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sd: mmc@704002b000 {
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compatible = "sophgo,sg2042-dwcmshc";
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reg = <0x70 0x4002b000 0x0 0x1000>;
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interrupt-parent = <&intc>;
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interrupts = <136 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkgen GATE_CLK_SD_100M>,
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<&clkgen GATE_CLK_AXI_SD>,
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<&clkgen GATE_CLK_100K_SD>;
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clock-names = "core",
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"bus",
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"timer";
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status = "disabled";
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};
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pcie_rc0: pcie@7060000000 {
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compatible = "sophgo,sg2042-pcie-host";
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device_type = "pci";
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reg = <0x70 0x60000000 0x0 0x00800000>,
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<0x40 0x00000000 0x0 0x00001000>;
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reg-names = "reg", "cfg";
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>,
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<0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>,
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<0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>,
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<0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
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<0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
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bus-range = <0x0 0xff>;
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vendor-id = <0x1f1c>;
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device-id = <0x2042>;
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cdns,no-bar-match-nbits = <48>;
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dma-coherent;
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msi-parent = <&msi>;
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status = "disabled";
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};
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pcie_rc1: pcie@7060800000 {
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compatible = "sophgo,sg2042-pcie-host";
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device_type = "pci";
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reg = <0x70 0x60800000 0x0 0x00800000>,
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<0x44 0x00000000 0x0 0x00001000>;
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reg-names = "reg", "cfg";
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linux,pci-domain = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>,
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<0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>,
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<0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>,
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<0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>,
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<0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>;
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bus-range = <0x0 0xff>;
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vendor-id = <0x1f1c>;
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device-id = <0x2042>;
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cdns,no-bar-match-nbits = <48>;
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dma-coherent;
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msi-parent = <&msi>;
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status = "disabled";
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};
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pcie_rc2: pcie@7062000000 {
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compatible = "sophgo,sg2042-pcie-host";
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device_type = "pci";
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reg = <0x70 0x62000000 0x0 0x00800000>,
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<0x48 0x00000000 0x0 0x00001000>;
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reg-names = "reg", "cfg";
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linux,pci-domain = <2>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>,
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<0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>,
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<0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>,
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<0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>,
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<0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>;
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bus-range = <0x0 0xff>;
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vendor-id = <0x1f1c>;
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device-id = <0x2042>;
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cdns,no-bar-match-nbits = <48>;
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dma-coherent;
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msi-parent = <&msi>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie_rc3: pcie@7062800000 {
|
|
compatible = "sophgo,sg2042-pcie-host";
|
|
device_type = "pci";
|
|
reg = <0x70 0x62800000 0x0 0x00800000>,
|
|
<0x4c 0x00000000 0x0 0x00001000>;
|
|
reg-names = "reg", "cfg";
|
|
linux,pci-domain = <3>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>,
|
|
<0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>,
|
|
<0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>,
|
|
<0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>,
|
|
<0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>;
|
|
bus-range = <0x0 0xff>;
|
|
vendor-id = <0x1f1c>;
|
|
device-id = <0x2042>;
|
|
cdns,no-bar-match-nbits = <48>;
|
|
dma-coherent;
|
|
msi-parent = <&msi>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|