39 lines
1.3 KiB
C
39 lines
1.3 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2025 MediaTek Inc.
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* Author: Qiqi Wang <qiqi.wang@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_POWER_MT8189_POWER_H
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#define _DT_BINDINGS_POWER_MT8189_POWER_H
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/* SPM */
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#define MT8189_POWER_DOMAIN_CONN 0
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#define MT8189_POWER_DOMAIN_AUDIO 1
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#define MT8189_POWER_DOMAIN_ADSP_TOP_DORMANT 2
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#define MT8189_POWER_DOMAIN_ADSP_INFRA 3
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#define MT8189_POWER_DOMAIN_ADSP_AO 4
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#define MT8189_POWER_DOMAIN_MM_INFRA 5
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#define MT8189_POWER_DOMAIN_ISP_IMG1 6
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#define MT8189_POWER_DOMAIN_ISP_IMG2 7
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#define MT8189_POWER_DOMAIN_ISP_IPE 8
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#define MT8189_POWER_DOMAIN_VDE0 9
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#define MT8189_POWER_DOMAIN_VEN0 10
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#define MT8189_POWER_DOMAIN_CAM_MAIN 11
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#define MT8189_POWER_DOMAIN_CAM_SUBA 12
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#define MT8189_POWER_DOMAIN_CAM_SUBB 13
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#define MT8189_POWER_DOMAIN_MDP0 14
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#define MT8189_POWER_DOMAIN_DISP 15
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#define MT8189_POWER_DOMAIN_DP_TX 16
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#define MT8189_POWER_DOMAIN_CSI_RX 17
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#define MT8189_POWER_DOMAIN_SSUSB 18
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#define MT8189_POWER_DOMAIN_MFG0 19
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#define MT8189_POWER_DOMAIN_MFG1 20
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#define MT8189_POWER_DOMAIN_MFG2 21
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#define MT8189_POWER_DOMAIN_MFG3 22
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#define MT8189_POWER_DOMAIN_EDP_TX_DORMANT 23
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#define MT8189_POWER_DOMAIN_PCIE 24
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#define MT8189_POWER_DOMAIN_PCIE_PHY 25
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#endif /* _DT_BINDINGS_POWER_MT8189_POWER_H */
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