50 lines
1.6 KiB
C
50 lines
1.6 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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#ifndef __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_
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#define __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_
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#define EN751221_XPON_PHY_RST 0
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#define EN751221_PCM1_ZSI_ISI_RST 1
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#define EN751221_FE_QDMA1_RST 2
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#define EN751221_FE_QDMA2_RST 3
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#define EN751221_FE_UNZIP_RST 4
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#define EN751221_PCM2_RST 5
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#define EN751221_PTM_MAC_RST 6
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#define EN751221_CRYPTO_RST 7
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#define EN751221_SAR_RST 8
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#define EN751221_TIMER_RST 9
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#define EN751221_INTC_RST 10
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#define EN751221_BONDING_RST 11
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#define EN751221_PCM1_RST 12
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#define EN751221_UART_RST 13
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#define EN751221_GPIO_RST 14
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#define EN751221_GDMA_RST 15
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#define EN751221_I2C_MASTER_RST 16
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#define EN751221_PCM2_ZSI_ISI_RST 17
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#define EN751221_SFC_RST 18
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#define EN751221_UART2_RST 19
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#define EN751221_GDMP_RST 20
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#define EN751221_FE_RST 21
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#define EN751221_USB_HOST_P0_RST 22
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#define EN751221_GSW_RST 23
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#define EN751221_SFC2_PCM_RST 24
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#define EN751221_PCIE0_RST 25
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#define EN751221_PCIE1_RST 26
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#define EN751221_CPU_TIMER_RST 27
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#define EN751221_PCIE_HB_RST 28
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#define EN751221_SIMIF_RST 29
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#define EN751221_XPON_MAC_RST 30
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#define EN751221_GFAST_RST 31
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#define EN751221_CPU_TIMER2_RST 32
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#define EN751221_UART3_RST 33
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#define EN751221_UART4_RST 34
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#define EN751221_UART5_RST 35
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#define EN751221_I2C2_RST 36
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#define EN751221_XSI_MAC_RST 37
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#define EN751221_XSI_PHY_RST 38
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#define EN751221_DMT_RST 39
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#define EN751221_USB_PHY_P0_RST 40
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#define EN751221_USB_PHY_P1_RST 41
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#endif /* __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_ */
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