65 lines
1.9 KiB
C
65 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* mt8196-afe-clk.h -- Mediatek MT8196 AFE Clock Control definitions
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*
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* Copyright (c) 2025 MediaTek Inc.
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* Author: Darren Ye <darren.ye@mediatek.com>
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*/
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#ifndef _MT8196_AFE_CLOCK_CTRL_H_
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#define _MT8196_AFE_CLOCK_CTRL_H_
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#define MT8196_AFE_26M 26000000
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#define MT8196_AUD_ENG1_CLK 45158400
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#define MT8196_AUD_ENG2_CLK 49152000
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/* APLL */
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#define APLL1_W_NAME "APLL1"
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#define APLL2_W_NAME "APLL2"
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enum {
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MT8196_APLL1 = 0,
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MT8196_APLL2,
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};
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enum {
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/* vlp clk */
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MT8196_CLK_VLP_MUX_AUDIOINTBUS,
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MT8196_CLK_VLP_MUX_AUD_ENG1,
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MT8196_CLK_VLP_MUX_AUD_ENG2,
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MT8196_CLK_VLP_MUX_AUDIO_H,
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/* pll */
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MT8196_CLK_TOP_APLL1_CK,
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MT8196_CLK_TOP_APLL2_CK,
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/* divider */
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MT8196_CLK_TOP_APLL12_DIV_I2SIN0,
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MT8196_CLK_TOP_APLL12_DIV_I2SIN1,
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MT8196_CLK_TOP_APLL12_DIV_FMI2S,
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MT8196_CLK_TOP_APLL12_DIV_TDMOUT_M,
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MT8196_CLK_TOP_APLL12_DIV_TDMOUT_B,
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/* mux */
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MT8196_CLK_TOP_ADSP_SEL,
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MT8196_CLK_NUM,
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};
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struct mtk_base_afe;
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int mt8196_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate);
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int mt8196_mck_disable(struct mtk_base_afe *afe, int mck_id);
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int mt8196_get_apll_rate(struct mtk_base_afe *afe, int apll);
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int mt8196_get_apll_by_rate(struct mtk_base_afe *afe, int rate);
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int mt8196_get_apll_by_name(struct mtk_base_afe *afe, const char *name);
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int mt8196_init_clock(struct mtk_base_afe *afe);
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int mt8196_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk);
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void mt8196_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);
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int mt8196_apll1_enable(struct mtk_base_afe *afe);
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void mt8196_apll1_disable(struct mtk_base_afe *afe);
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int mt8196_apll2_enable(struct mtk_base_afe *afe);
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void mt8196_apll2_disable(struct mtk_base_afe *afe);
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int mt8196_afe_enable_main_clock(struct mtk_base_afe *afe);
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int mt8196_afe_disable_main_clock(struct mtk_base_afe *afe);
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int mt8196_afe_enable_reg_rw_clk(struct mtk_base_afe *afe);
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int mt8196_afe_disable_reg_rw_clk(struct mtk_base_afe *afe);
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#endif
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