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2026-09-06 12:53:21 -06:00
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linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/arm,pl172.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/arm,pl172.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM PL172/PL175/PL176 MultiPort Memory Controller
maintainers:
- Frank Li <Frank.Li@nxp.com>
# We need a select here so we don't match all nodes with 'arm,primecell'
select:
properties:
compatible:
contains:
enum:
- arm,pl172
- arm,pl175
- arm,pl176
required:
- compatible
properties:
compatible:
items:
- enum:
- arm,pl172
- arm,pl175
- arm,pl176
- const: arm,primecell
reg:
maxItems: 1
'#address-cells':
const: 2
'#size-cells':
const: 1
ranges: true
clocks:
maxItems: 2
clock-names:
items:
- const: mpmcclk
- const: apb_pclk
clock-ranges: true
resets:
maxItems: 1
patternProperties:
"^cs[0-9]$":
type: object
additionalProperties: false
patternProperties:
"^flash@[0-9],[0-9a-f]+$":
type: object
$ref: /schemas/mtd/mtd-physmap.yaml#
unevaluatedProperties: false
"^(gpio|sram)@[0-9],[0-9a-f]+$":
type: object
additionalProperties: true
properties:
'#address-cells':
const: 2
'#size-cells':
const: 1
ranges: true
clocks:
maxItems: 2
clock-ranges: true
mpmc,cs:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Chip select number. Indicates to the pl0172 driver
which chipselect is used for accessing the memory.
mpmc,memory-width:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [8, 16, 32]
description:
Width of the chip select memory. Must be equal to either 8, 16 or 32.
mpmc,async-page-mode:
$ref: /schemas/types.yaml#/definitions/flag
description:
Enable asynchronous page mode.
mpmc,cs-active-high:
$ref: /schemas/types.yaml#/definitions/flag
description:
Set chip select polarity to active high.
mpmc,byte-lane-low:
$ref: /schemas/types.yaml#/definitions/flag
description:
Set byte lane state to low.
mpmc,extended-wait:
$ref: /schemas/types.yaml#/definitions/flag
description:
Enable extended wait.
mpmc,buffer-enable:
$ref: /schemas/types.yaml#/definitions/flag
description:
Enable write buffer, option is not supported by
PL175 and PL176 controllers.
mpmc,write-protect:
$ref: /schemas/types.yaml#/definitions/flag
description:
Enable write protect.
mpmc,read-enable-delay:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Delay from chip select assertion to read
enable (RE signal) in nano seconds.
mpmc,write-enable-delay:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Delay from chip select assertion to write
enable (WE signal) in nano seconds.
mpmc,output-enable-delay:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Delay from chip select assertion to output
enable (OE signal) in nano seconds.
mpmc,write-access-delay:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Delay from chip select assertion to write
access in nano seconds.
mpmc,read-access-delay:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Delay from chip select assertion to read
access in nano seconds.
mpmc,page-mode-read-delay:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Delay for asynchronous page mode sequential
accesses in nano seconds.
mpmc,turn-round-delay:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Delay between access to memory banks in nano
seconds.
required:
- compatible
- reg
- '#address-cells'
- '#size-cells'
- ranges
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/lpc18xx-ccu.h>
memory-controller@40005000 {
compatible = "arm,pl172", "arm,primecell";
reg = <0x40005000 0x1000>;
clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
clock-names = "mpmcclk", "apb_pclk";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x1c000000 0x1000000
1 0 0x1d000000 0x1000000
2 0 0x1e000000 0x1000000
3 0 0x1f000000 0x1000000>;
cs0 {
#address-cells = <2>;
#size-cells = <1>;
ranges;
mpmc,cs = <0>;
mpmc,memory-width = <16>;
mpmc,byte-lane-low;
mpmc,write-enable-delay = <0>;
mpmc,output-enable-delay = <0>;
mpmc,read-enable-delay = <70>;
mpmc,page-mode-read-delay = <70>;
flash@0,0 {
compatible = "sst,sst39vf320", "cfi-flash";
reg = <0 0 0x400000>;
bank-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "data";
reg = <0 0x400000>;
};
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/arm,pl35x-smc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/arm,pl35x-smc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm PL35x Series Static Memory Controller (SMC)
maintainers:
- Miquel Raynal <miquel.raynal@bootlin.com>
description: |
The PL35x Static Memory Controller is a bus where you can connect two kinds
of memory interfaces, which are NAND and memory mapped interfaces (such as
SRAM or NOR) depending on the specific configuration.
The TRM is available here:
https://documentation-service.arm.com/static/5e8e2524fd977155116a58aa
# We need a select here so we don't match all nodes with 'arm,primecell'
select:
properties:
compatible:
contains:
enum:
- arm,pl353-smc-r2p1
- arm,pl354
required:
- compatible
properties:
$nodename:
pattern: "^memory-controller@[0-9a-f]+$"
compatible:
items:
- enum:
- arm,pl353-smc-r2p1
- arm,pl354
- const: arm,primecell
"#address-cells":
const: 2
"#size-cells":
const: 1
reg:
items:
- description:
Configuration registers for the host and sub-controllers.
The three chip select regions are defined in 'ranges'.
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
maxItems: 2
ranges:
minItems: 1
maxItems: 8
interrupts:
minItems: 1
items:
- description: Combined or Memory interface 0 IRQ
- description: Memory interface 1 IRQ
patternProperties:
"@[0-7],[a-f0-9]+$":
type: object
additionalProperties: true
description: |
The child device node represents the controller connected to the SMC
bus. The controller can be a NAND controller or a pair of any memory
mapped controllers such as NOR and SRAM controllers.
properties:
compatible:
description:
Compatible of memory controller.
reg:
items:
- items:
- description: |
Chip-select ID, as in the parent range property.
minimum: 0
maximum: 7
- description: |
Offset of the memory region requested by the device.
- description: |
Length of the memory region requested by the device.
required:
- compatible
- reg
required:
- compatible
- reg
- clock-names
- clocks
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
const: arm,pl354
then:
properties:
clocks:
# According to TRM, really should be 3 clocks
maxItems: 1
clock-names:
const: apb_pclk
else:
properties:
clocks:
items:
- description: clock for the memory device bus
- description: main clock of the SMC
clock-names:
items:
- const: memclk
- const: apb_pclk
examples:
- |
smcc: memory-controller@e000e000 {
compatible = "arm,pl353-smc-r2p1", "arm,primecell";
reg = <0xe000e000 0x0001000>;
clock-names = "memclk", "apb_pclk";
clocks = <&clkc 11>, <&clkc 44>;
ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
#address-cells = <2>;
#size-cells = <1>;
nfc0: nand-controller@0,0 {
compatible = "arm,pl353-nand-r2p1";
reg = <0 0 0x1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt
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* Device tree bindings for Atmel EBI
The External Bus Interface (EBI) controller is a bus where you can connect
asynchronous (NAND, NOR, SRAM, ....) and synchronous memories (SDR/DDR SDRAMs).
The EBI provides a glue-less interface to asynchronous memories through the SMC
(Static Memory Controller).
Required properties:
- compatible: "atmel,at91sam9260-ebi"
"atmel,at91sam9261-ebi"
"atmel,at91sam9263-ebi0"
"atmel,at91sam9263-ebi1"
"atmel,at91sam9rl-ebi"
"atmel,at91sam9g45-ebi"
"atmel,at91sam9x5-ebi"
"atmel,sama5d3-ebi"
"microchip,sam9x60-ebi"
- reg: Contains offset/length value for EBI memory mapping.
This property might contain several entries if the EBI
memory range is not contiguous
- #address-cells: Must be 2.
The first cell encodes the CS.
The second cell encode the offset into the CS memory
range.
- #size-cells: Must be set to 1.
- ranges: Encodes CS to memory region association.
- clocks: Clock feeding the EBI controller.
See clock-bindings.txt
Children device nodes are representing device connected to the EBI bus.
Required device node properties:
- reg: Contains the chip-select id, the offset and the length
of the memory region requested by the device.
EBI bus configuration will be defined directly in the device subnode.
Optional EBI/SMC properties:
- atmel,smc-bus-width: width of the asynchronous device's data bus
8, 16 or 32.
Default to 8 when undefined.
- atmel,smc-byte-access-type "write" or "select" (see Atmel datasheet).
Default to "select" when undefined.
- atmel,smc-read-mode "nrd" or "ncs".
Default to "ncs" when undefined.
- atmel,smc-write-mode "nwe" or "ncs".
Default to "ncs" when undefined.
- atmel,smc-exnw-mode "disabled", "frozen" or "ready".
Default to "disabled" when undefined.
- atmel,smc-page-mode enable page mode if present. The provided value
defines the page size (supported values: 4, 8,
16 and 32).
- atmel,smc-tdf-mode: "normal" or "optimized". When set to
"optimized" the data float time is optimized
depending on the next device being accessed
(next device setup time is subtracted to the
current device data float time).
Default to "normal" when undefined.
If at least one atmel,smc- property is defined the following SMC timing
properties become mandatory. In the other hand, if none of the atmel,smc-
properties are specified, we assume that the EBI bus configuration will be
handled by the sub-device driver, and none of those properties should be
defined.
All the timings are expressed in nanoseconds (see Atmel datasheet for a full
description).
- atmel,smc-ncs-rd-setup-ns
- atmel,smc-nrd-setup-ns
- atmel,smc-ncs-wr-setup-ns
- atmel,smc-nwe-setup-ns
- atmel,smc-ncs-rd-pulse-ns
- atmel,smc-nrd-pulse-ns
- atmel,smc-ncs-wr-pulse-ns
- atmel,smc-nwe-pulse-ns
- atmel,smc-nwe-cycle-ns
- atmel,smc-nrd-cycle-ns
- atmel,smc-tdf-ns
Example:
ebi: ebi@10000000 {
compatible = "atmel,sama5d3-ebi";
#address-cells = <2>;
#size-cells = <1>;
atmel,smc = <&hsmc>;
atmel,matrix = <&matrix>;
reg = <0x10000000 0x10000000
0x40000000 0x30000000>;
ranges = <0x0 0x0 0x10000000 0x10000000
0x1 0x0 0x40000000 0x10000000
0x2 0x0 0x50000000 0x10000000
0x3 0x0 0x60000000 0x10000000>;
clocks = <&mck>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ebi_addr>;
nor: flash@0,0 {
compatible = "cfi-flash";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0 0x0 0x1000000>;
bank-width = <2>;
atmel,smc-read-mode = "nrd";
atmel,smc-write-mode = "nwe";
atmel,smc-bus-width = <16>;
atmel,smc-ncs-rd-setup-ns = <0>;
atmel,smc-ncs-wr-setup-ns = <0>;
atmel,smc-nwe-setup-ns = <8>;
atmel,smc-nrd-setup-ns = <16>;
atmel,smc-ncs-rd-pulse-ns = <84>;
atmel,smc-ncs-wr-pulse-ns = <84>;
atmel,smc-nrd-pulse-ns = <76>;
atmel,smc-nwe-pulse-ns = <76>;
atmel,smc-nrd-cycle-ns = <107>;
atmel,smc-nwe-cycle-ns = <84>;
atmel,smc-tdf-ns = <16>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/brcm,brcmstb-memc-ddr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Memory controller (MEMC) for Broadcom STB
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
properties:
compatible:
oneOf:
- description: Revision > 2.1 controllers
items:
- enum:
- brcm,brcmstb-memc-ddr-rev-b.2.2
- brcm,brcmstb-memc-ddr-rev-b.2.3
- brcm,brcmstb-memc-ddr-rev-b.2.5
- brcm,brcmstb-memc-ddr-rev-b.2.6
- brcm,brcmstb-memc-ddr-rev-b.2.7
- brcm,brcmstb-memc-ddr-rev-b.2.8
- brcm,brcmstb-memc-ddr-rev-b.3.0
- brcm,brcmstb-memc-ddr-rev-b.3.1
- brcm,brcmstb-memc-ddr-rev-c.1.0
- brcm,brcmstb-memc-ddr-rev-c.1.1
- brcm,brcmstb-memc-ddr-rev-c.1.2
- brcm,brcmstb-memc-ddr-rev-c.1.3
- brcm,brcmstb-memc-ddr-rev-c.1.4
- const: brcm,brcmstb-memc-ddr-rev-b.2.1
- const: brcm,brcmstb-memc-ddr
- description: Revision 2.1 controllers
items:
- const: brcm,brcmstb-memc-ddr-rev-b.2.1
- const: brcm,brcmstb-memc-ddr
- description: Revision 2.0 controllers
items:
- const: brcm,brcmstb-memc-ddr-rev-b.2.0
- const: brcm,brcmstb-memc-ddr
- description: Revision 1.x controllers
items:
- const: brcm,brcmstb-memc-ddr-rev-b.1.x
- const: brcm,brcmstb-memc-ddr
- description: Revision 0.x controllers
items:
- const: brcm,brcmstb-memc-ddr-rev-a.0.0
- const: brcm,brcmstb-memc-ddr
reg:
maxItems: 1
clock-frequency:
description: DDR PHY frequency in Hz
required:
- compatible
- reg
additionalProperties: false
examples:
- |
memory-controller@9902000 {
compatible = "brcm,brcmstb-memc-ddr-rev-c.1.1",
"brcm,brcmstb-memc-ddr-rev-b.2.1",
"brcm,brcmstb-memc-ddr";
reg = <0x9902000 0x600>;
clock-frequency = <2133000000>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/brcm,dpfe-cpu.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/brcm,dpfe-cpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: DDR PHY Front End (DPFE) for Broadcom STB
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
- Markus Mayer <mmayer@broadcom.com>
properties:
compatible:
items:
- enum:
- brcm,bcm7271-dpfe-cpu
- brcm,bcm7268-dpfe-cpu
- const: brcm,dpfe-cpu
reg:
items:
- description: DCPU register space
- description: DCPU data memory space
- description: DCPU instruction memory space
reg-names:
items:
- const: dpfe-cpu
- const: dpfe-dmem
- const: dpfe-imem
required:
- compatible
- reg
- reg-names
additionalProperties: false
examples:
- |
dpfe-cpu@f1132000 {
compatible = "brcm,bcm7271-dpfe-cpu", "brcm,dpfe-cpu";
reg = <0xf1132000 0x180>,
<0xf1134000 0x1000>,
<0xf1138000 0x4000>;
reg-names = "dpfe-cpu", "dpfe-dmem", "dpfe-imem";
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Calxeda DDR memory controller
description: |
The Calxeda DDR memory controller is initialised and programmed by the
firmware, but an OS might want to read its registers for error reporting
purposes and to learn about the DRAM topology.
maintainers:
- Andre Przywara <andre.przywara@arm.com>
properties:
compatible:
enum:
- calxeda,hb-ddr-ctrl
- calxeda,ecx-2000-ddr-ctrl
reg:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
memory-controller@fff00000 {
compatible = "calxeda,hb-ddr-ctrl";
reg = <0xfff00000 0x1000>;
interrupts = <0 91 4>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/canaan,k210-sram.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/canaan,k210-sram.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Canaan K210 SRAM memory controller
description:
The Canaan K210 SRAM memory controller is responsible for the system's 8 MiB
of SRAM. The controller is initialised by the bootloader, which configures
its clocks, before OS bringup.
maintainers:
- Conor Dooley <conor@kernel.org>
properties:
compatible:
enum:
- canaan,k210-sram
clocks:
minItems: 1
items:
- description: sram0 clock
- description: sram1 clock
- description: aisram clock
clock-names:
minItems: 1
items:
- const: sram0
- const: sram1
- const: aisram
required:
- compatible
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/k210-clk.h>
memory-controller {
compatible = "canaan,k210-sram";
clocks = <&sysclk K210_CLK_SRAM0>,
<&sysclk K210_CLK_SRAM1>,
<&sysclk K210_CLK_AI>;
clock-names = "sram0", "sram1", "aisram";
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,ddr4.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,ddr4.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: DDR4 SDRAM compliant to JEDEC JESD79-4D
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
allOf:
- $ref: jedec,sdram-props.yaml#
properties:
compatible:
items:
- pattern: "^ddr4-[0-9a-f]{4},[a-z]{1,20}-[0-9a-f]{2}$"
- const: jedec,ddr4
required:
- compatible
- density
- io-width
unevaluatedProperties: false
examples:
- |
ddr {
compatible = "ddr4-00ff,azaz-ff", "jedec,ddr4";
density = <8192>;
io-width = <8>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:
const: jedec,lpddr2-timings
max-freq:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Maximum DDR clock frequency for the speed-bin, in Hz.
min-freq:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Minimum DDR clock frequency for the speed-bin, in Hz.
tCKESR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
CKE minimum pulse width during SELF REFRESH (low pulse width during
SELF REFRESH) in pico seconds.
tDQSCK-max:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
DQS output data access time from CK_t/CK_c in pico seconds.
tDQSCK-max-derated:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
DQS output data access time from CK_t/CK_c, temperature de-rated, in pico
seconds.
tFAW:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Four-bank activate window in pico seconds.
tRAS-max-ns:
description: |
Row active time in nano seconds.
tRAS-min:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Row active time in pico seconds.
tRCD:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
RAS-to-CAS delay in pico seconds.
tRPab:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Row precharge time (all banks) in pico seconds.
tRRD:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Active bank A to active bank B in pico seconds.
tRTP:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Internal READ to PRECHARGE command delay in pico seconds.
tWR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
WRITE recovery time in pico seconds.
tWTR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Internal WRITE-to-READ command delay in pico seconds.
tXP:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Exit power-down to next valid command delay in pico seconds.
tZQCL:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Long calibration time in pico seconds.
tZQCS:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Short calibration time in pico seconds.
tZQinit:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Initialization calibration time in pico seconds.
required:
- compatible
- min-freq
- max-freq
additionalProperties: false
examples:
- |
timings {
compatible = "jedec,lpddr2-timings";
min-freq = <10000000>;
max-freq = <400000000>;
tCKESR = <15000>;
tDQSCK-max = <5500>;
tFAW = <50000>;
tRAS-max-ns = <70000>;
tRAS-min = <42000>;
tRPab = <21000>;
tRCD = <18000>;
tRRD = <10000>;
tRTP = <7500>;
tWR = <15000>;
tWTR = <7500>;
tXP = <7500>;
tZQCL = <360000>;
tZQCS = <90000>;
tZQinit = <1000000>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
allOf:
- $ref: jedec,sdram-props.yaml#
properties:
compatible:
oneOf:
- items:
- enum:
- elpida,ECB240ABACN
- elpida,B8132B2PB-6D-F
- enum:
- jedec,lpddr2-nvm
- jedec,lpddr2-s2
- jedec,lpddr2-s4
- items:
- pattern: "^lpddr2-[0-9a-f]{2},[0-9a-f]{4}$"
- enum:
- jedec,lpddr2-nvm
- jedec,lpddr2-s2
- jedec,lpddr2-s4
revision-id1:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 255
description: |
Revision 1 value of SDRAM chip. Obtained from device datasheet.
Property is deprecated, use revision-id instead.
deprecated: true
revision-id2:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 255
description: |
Revision 2 value of SDRAM chip. Obtained from device datasheet.
Property is deprecated, use revision-id instead.
deprecated: true
tRRD-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
Active bank a to active bank b in terms of number of clock cycles.
Obtained from device datasheet.
tWTR-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
Internal WRITE-to-READ command delay in terms of number of clock cycles.
Obtained from device datasheet.
tXP-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
Exit power-down to next valid command delay in terms of number of clock
cycles. Obtained from device datasheet.
tRTP-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
Internal READ to PRECHARGE command delay in terms of number of clock
cycles. Obtained from device datasheet.
tCKE-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
of clock cycles. Obtained from device datasheet.
tRPab-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
Row precharge time (all banks) in terms of number of clock cycles.
Obtained from device datasheet.
tRCD-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
RAS-to-CAS delay in terms of number of clock cycles. Obtained from
device datasheet.
tWR-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
WRITE recovery time in terms of number of clock cycles. Obtained from
device datasheet.
tRASmin-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
Row active time in terms of number of clock cycles. Obtained from device
datasheet.
tCKESR-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
CKE minimum pulse width during SELF REFRESH (low pulse width during
SELF REFRESH) in terms of number of clock cycles. Obtained from device
datasheet.
tFAW-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
Four-bank activate window in terms of number of clock cycles. Obtained
from device datasheet.
patternProperties:
"^lpddr2-timings":
$ref: jedec,lpddr2-timings.yaml
description: |
The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
"lpddr2-timings" provides AC timing parameters of the device for
a given speed-bin. The user may provide the timings for as many
speed-bins as is required.
required:
- compatible
- density
- io-width
unevaluatedProperties: false
examples:
- |
elpida_ECB240ABACN: lpddr2 {
compatible = "elpida,ECB240ABACN", "jedec,lpddr2-s4";
density = <2048>;
io-width = <32>;
revision-id = <1 0>;
tRPab-min-tck = <3>;
tRCD-min-tck = <3>;
tWR-min-tck = <3>;
tRASmin-min-tck = <3>;
tRRD-min-tck = <2>;
tWTR-min-tck = <2>;
tXP-min-tck = <2>;
tRTP-min-tck = <2>;
tCKE-min-tck = <3>;
tCKESR-min-tck = <3>;
tFAW-min-tck = <8>;
timings_elpida_ECB240ABACN_400mhz: lpddr2-timings0 {
compatible = "jedec,lpddr2-timings";
min-freq = <10000000>;
max-freq = <400000000>;
tRPab = <21000>;
tRCD = <18000>;
tWR = <15000>;
tRAS-min = <42000>;
tRRD = <10000>;
tWTR = <7500>;
tXP = <7500>;
tRTP = <7500>;
tCKESR = <15000>;
tDQSCK-max = <5500>;
tFAW = <50000>;
tZQCS = <90000>;
tZQCL = <360000>;
tZQinit = <1000000>;
tRAS-max-ns = <70000>;
};
timings_elpida_ECB240ABACN_200mhz: lpddr2-timings1 {
compatible = "jedec,lpddr2-timings";
min-freq = <10000000>;
max-freq = <200000000>;
tRPab = <21000>;
tRCD = <18000>;
tWR = <15000>;
tRAS-min = <42000>;
tRRD = <10000>;
tWTR = <10000>;
tXP = <7500>;
tRTP = <7500>;
tCKESR = <15000>;
tDQSCK-max = <5500>;
tFAW = <50000>;
tZQCS = <90000>;
tZQCL = <360000>;
tZQinit = <1000000>;
tRAS-max-ns = <70000>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:
const: jedec,lpddr3-timings
reg:
maxItems: 1
description: |
Maximum DDR clock frequency for the speed-bin, in Hz.
Property is deprecated, use max-freq.
deprecated: true
max-freq:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Maximum DDR clock frequency for the speed-bin, in Hz.
min-freq:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Minimum DDR clock frequency for the speed-bin, in Hz.
tCKE:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
CKE minimum pulse width (HIGH and LOW pulse width) in pico seconds.
tCKESR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
CKE minimum pulse width during SELF REFRESH (low pulse width during
SELF REFRESH) in pico seconds.
tFAW:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Four-bank activate window in pico seconds.
tMRD:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Mode register set command delay in pico seconds.
tR2R-C2C:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Additional READ-to-READ delay in chip-to-chip cases in pico seconds.
tRAS:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Row active time in pico seconds.
tRC:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
ACTIVATE-to-ACTIVATE command period in pico seconds.
tRCD:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
RAS-to-CAS delay in pico seconds.
tRFC:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Refresh Cycle time in pico seconds.
tRPab:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Row precharge time (all banks) in pico seconds.
tRPpb:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Row precharge time (single banks) in pico seconds.
tRRD:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Active bank A to active bank B in pico seconds.
tRTP:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Internal READ to PRECHARGE command delay in pico seconds.
tW2W-C2C:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Additional WRITE-to-WRITE delay in chip-to-chip cases in pico seconds.
tWR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
WRITE recovery time in pico seconds.
tWTR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Internal WRITE-to-READ command delay in pico seconds.
tXP:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Exit power-down to next valid command delay in pico seconds.
tXSR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
SELF REFRESH exit to next valid command delay in pico seconds.
required:
- compatible
- min-freq
- max-freq
additionalProperties: false
examples:
- |
lpddr3 {
timings {
compatible = "jedec,lpddr3-timings";
max-freq = <800000000>;
min-freq = <100000000>;
tCKE = <3750>;
tCKESR = <3750>;
tFAW = <25000>;
tMRD = <7000>;
tR2R-C2C = <0>;
tRAS = <23000>;
tRC = <33750>;
tRCD = <10000>;
tRFC = <65000>;
tRPab = <12000>;
tRPpb = <12000>;
tRRD = <6000>;
tRTP = <3750>;
tW2W-C2C = <0>;
tWR = <7500>;
tWTR = <3750>;
tXP = <3750>;
tXSR = <70000>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
allOf:
- $ref: jedec,sdram-props.yaml#
properties:
compatible:
oneOf:
- items:
- enum:
- samsung,K3QF2F20DB
- const: jedec,lpddr3
- items:
- pattern: "^lpddr3-[0-9a-f]{2},[0-9a-f]{4}$"
- const: jedec,lpddr3
'#address-cells':
const: 1
deprecated: true
manufacturer-id:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Manufacturer ID value read from Mode Register 5. The property is
deprecated, manufacturer should be derived from the compatible.
deprecated: true
'#size-cells':
const: 0
deprecated: true
tCKE-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
of clock cycles.
tCKESR-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
CKE minimum pulse width during SELF REFRESH (low pulse width during
SELF REFRESH) in terms of number of clock cycles.
tDQSCK-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
DQS output data access time from CK_t/CK_c in terms of number of clock
cycles.
tFAW-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 63
description: |
Four-bank activate window in terms of number of clock cycles.
tMRD-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
Mode register set command delay in terms of number of clock cycles.
tR2R-C2C-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description: |
Additional READ-to-READ delay in chip-to-chip cases in terms of number
of clock cycles.
tRAS-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 63
description: |
Row active time in terms of number of clock cycles.
tRC-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 63
description: |
ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles.
tRCD-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
RAS-to-CAS delay in terms of number of clock cycles.
tRFC-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 255
description: |
Refresh Cycle time in terms of number of clock cycles.
tRL-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
READ data latency in terms of number of clock cycles.
tRPab-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
Row precharge time (all banks) in terms of number of clock cycles.
tRPpb-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
Row precharge time (single banks) in terms of number of clock cycles.
tRRD-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
Active bank A to active bank B in terms of number of clock cycles.
tRTP-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
Internal READ to PRECHARGE command delay in terms of number of clock
cycles.
tW2W-C2C-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description: |
Additional WRITE-to-WRITE delay in chip-to-chip cases in terms of number
of clock cycles.
tWL-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
WRITE data latency in terms of number of clock cycles.
tWR-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
WRITE recovery time in terms of number of clock cycles.
tWTR-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
Internal WRITE-to-READ command delay in terms of number of clock cycles.
tXP-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 255
description: |
Exit power-down to next valid command delay in terms of number of clock
cycles.
tXSR-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 1023
description: |
SELF REFRESH exit to next valid command delay in terms of number of clock
cycles.
patternProperties:
"^timings((-[0-9])+|(@[0-9a-f]+))?$":
$ref: jedec,lpddr3-timings.yaml
description: |
The lpddr3 node may have one or more child nodes with timings.
Each timing node provides AC timing parameters of the device for a given
speed-bin. The user may provide the timings for as many speed-bins as is
required.
required:
- compatible
- density
- io-width
unevaluatedProperties: false
examples:
- |
lpddr3 {
compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
density = <16384>;
io-width = <32>;
tCKE-min-tck = <2>;
tCKESR-min-tck = <2>;
tDQSCK-min-tck = <5>;
tFAW-min-tck = <5>;
tMRD-min-tck = <5>;
tR2R-C2C-min-tck = <0>;
tRAS-min-tck = <5>;
tRC-min-tck = <6>;
tRCD-min-tck = <3>;
tRFC-min-tck = <17>;
tRL-min-tck = <14>;
tRPab-min-tck = <2>;
tRPpb-min-tck = <2>;
tRRD-min-tck = <2>;
tRTP-min-tck = <2>;
tW2W-C2C-min-tck = <0>;
tWL-min-tck = <8>;
tWR-min-tck = <7>;
tWTR-min-tck = <2>;
tXP-min-tck = <2>;
tXSR-min-tck = <12>;
timings {
compatible = "jedec,lpddr3-timings";
max-freq = <800000000>;
min-freq = <100000000>;
tCKE = <3750>;
tCKESR = <3750>;
tFAW = <25000>;
tMRD = <7000>;
tR2R-C2C = <0>;
tRAS = <23000>;
tRC = <33750>;
tRCD = <10000>;
tRFC = <65000>;
tRPab = <12000>;
tRPpb = <12000>;
tRRD = <6000>;
tRTP = <3750>;
tW2W-C2C = <0>;
tWR = <7500>;
tWTR = <3750>;
tXP = <3750>;
tXSR = <70000>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr4.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr4.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LPDDR4 SDRAM compliant to JEDEC JESD209-4
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
allOf:
- $ref: jedec,sdram-props.yaml#
properties:
compatible:
items:
- pattern: "^lpddr4-[0-9a-f]{2},[0-9a-f]{4}$"
- const: jedec,lpddr4
required:
- compatible
- density
- io-width
unevaluatedProperties: false
examples:
- |
lpddr {
compatible = "lpddr4-ff,0100", "jedec,lpddr4";
density = <8192>;
io-width = <16>;
revision-id = <1 0>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr5.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr5.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LPDDR5 SDRAM compliant to JEDEC JESD209-5
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
allOf:
- $ref: jedec,sdram-props.yaml#
properties:
compatible:
items:
- pattern: "^lpddr5-[0-9a-f]{2},[0-9a-f]{4}$"
- const: jedec,lpddr5
serial-id:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
Serial IDs read from Mode Registers 47 through 54. One byte per uint32
cell (i.e. <MR47 MR48 MR49 MR50 MR51 MR52 MR53 MR54>).
maxItems: 8
items:
minimum: 0
maximum: 255
required:
- compatible
- density
- io-width
unevaluatedProperties: false
examples:
- |
lpddr {
compatible = "lpddr5-01,0200", "jedec,lpddr5";
density = <8192>;
io-width = <8>;
revision-id = <2 0>;
serial-id = <3 1 0 0 0 0 0 0>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-channel.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,sdram-channel.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SDRAM channel with chip/rank topology description
description:
A memory channel of SDRAM memory like DDR SDRAM or LPDDR SDRAM is a completely
independent set of pins (DQ, CA, CS, CK, etc.) that connect one or more memory
chips to a host system. The main purpose of this node is to overall memory
topology of the system, including the amount of individual memory chips and
the ranks per chip.
maintainers:
- Julius Werner <jwerner@chromium.org>
properties:
$nodename:
pattern: "sdram-channel-[0-9]+$"
compatible:
enum:
- jedec,ddr4-channel
- jedec,lpddr2-channel
- jedec,lpddr3-channel
- jedec,lpddr4-channel
- jedec,lpddr5-channel
io-width:
description:
The number of DQ pins in the channel. If this number is different
from (a multiple of) the io-width of the SDRAM chip, that means that
multiple instances of that type of chip are wired in parallel on this
channel (with the channel's DQ pins split up between the different
chips, and the CA, CS, etc. pins of the different chips all shorted
together). This means that the total physical memory controlled by a
channel is equal to the sum of the densities of each rank on the
connected SDRAM chip, times the io-width of the channel divided by
the io-width of the SDRAM chip.
enum:
- 8
- 16
- 32
- 64
- 128
"#address-cells":
const: 1
"#size-cells":
const: 0
patternProperties:
"^rank@[0-9]+$":
type: object
description:
Each physical SDRAM chip may have one or more ranks. Ranks are
internal but fully independent sub-units of the chip. Each SDRAM bus
transaction on the channel targets exactly one rank, based on the
state of the CS pins. Different ranks may have different densities and
timing requirements.
required:
- reg
allOf:
- if:
properties:
compatible:
contains:
const: jedec,ddr4-channel
then:
patternProperties:
"^rank@[0-9]+$":
$ref: /schemas/memory-controllers/ddr/jedec,ddr4.yaml#
- if:
properties:
compatible:
contains:
const: jedec,lpddr2-channel
then:
patternProperties:
"^rank@[0-9]+$":
$ref: /schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
- if:
properties:
compatible:
contains:
const: jedec,lpddr3-channel
then:
patternProperties:
"^rank@[0-9]+$":
$ref: /schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
- if:
properties:
compatible:
contains:
const: jedec,lpddr4-channel
then:
patternProperties:
"^rank@[0-9]+$":
$ref: /schemas/memory-controllers/ddr/jedec,lpddr4.yaml#
- if:
properties:
compatible:
contains:
const: jedec,lpddr5-channel
then:
patternProperties:
"^rank@[0-9]+$":
$ref: /schemas/memory-controllers/ddr/jedec,lpddr5.yaml#
required:
- compatible
- io-width
- "#address-cells"
- "#size-cells"
additionalProperties: false
examples:
- |
sdram-channel-0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "jedec,lpddr3-channel";
io-width = <32>;
rank@0 {
compatible = "lpddr3-ff,0100", "jedec,lpddr3";
reg = <0>;
density = <8192>;
io-width = <16>;
revision-id = <1 0>;
};
};
sdram-channel-1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "jedec,lpddr4-channel";
io-width = <32>;
rank@0 {
compatible = "lpddr4-05,0301", "jedec,lpddr4";
reg = <0>;
density = <4096>;
io-width = <32>;
revision-id = <3 1>;
};
rank@1 {
compatible = "lpddr4-05,0301", "jedec,lpddr4";
reg = <1>;
density = <2048>;
io-width = <32>;
revision-id = <3 1>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-props.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,sdram-props.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Common properties for SDRAM types
description:
Different SDRAM types generally use the same properties and only differ in the
range of legal values for each. This file defines the common parts that can be
reused for each type. Nodes using this schema should generally be nested under
a SDRAM channel node.
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:
description: |
Compatible strings can be either explicit vendor names and part numbers
(e.g. elpida,ECB240ABACN), or generated strings of the form
lpddrX-YY,ZZZZ or ddrX-YYYY,AAAA...-ZZ where X, Y, and Z are lowercase
hexadecimal with leading zeroes, and A is lowercase ASCII.
For LPDDR and DDR SDRAM, X is the SDRAM version (2, 3, 4, etc.).
For LPDDR SDRAM:
- YY is the manufacturer ID (from MR5), 1 byte
- ZZZZ is the revision ID (from MR6 and MR7), 2 bytes
For DDR4 SDRAM with SPD, according to JEDEC SPD4.1.2.L-6:
- YYYY is the manufacturer ID, 2 bytes, from bytes 320 and 321
- AAAA... is the part number, 20 bytes (20 chars) from bytes 329 to 348
without trailing spaces
- ZZ is the revision ID, 1 byte, from byte 349
The former form is useful when the SDRAM vendor and part number are
known, for example, when memory is soldered on the board. The latter
form is useful when SDRAM nodes are created at runtime by boot firmware
that doesn't have access to static part number information.
reg:
description:
The rank number of this memory rank when used as a subnode to an memory
channel.
minimum: 0
maximum: 3
revision-id:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: |
SDRAM revision ID:
- LPDDR SDRAM, decoded from Mode Registers 6 and 7, always 2 bytes.
- DDR4 SDRAM, decoded from the SPD from byte 349 according to
JEDEC SPD4.1.2.L-6, always 1 byte.
One byte per uint32 cell (e.g., <MR6 MR7>).
maxItems: 2
items:
minimum: 0
maximum: 255
density:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Density of the SDRAM chip in megabits:
- LPDDR SDRAM, decoded from Mode Register 8.
- DDR4 SDRAM, decoded from the SPD from bits 3-0 of byte 4 according to
JEDEC SPD4.1.2.L-6.
enum:
- 64
- 128
- 256
- 512
- 1024
- 2048
- 3072
- 4096
- 6144
- 8192
- 12288
- 16384
- 24576
- 32768
io-width:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
I/O bus width in bits of the SDRAM chip:
- LPDDR SDRAM, decoded from Mode Register 8.
- DDR4 SDRAM, decoded from the SPD from bits 2-0 of byte 12 according to
JEDEC SPD4.1.2.L-6.
enum:
- 8
- 16
- 32
additionalProperties: true
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos SoC SROM Controller driver
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
description: |+
The SROM controller can be used to attach external peripherals. In this case
extra properties, describing the bus behind it, should be specified.
properties:
compatible:
items:
- const: samsung,exynos4210-srom
reg:
maxItems: 1
"#address-cells":
const: 2
"#size-cells":
const: 1
ranges:
minItems: 1
maxItems: 4
description: |
Reflects the memory layout with four integer values per bank. Format:
<bank-number> 0 <parent address of bank> <size>
Up to four banks are supported.
patternProperties:
"^.*@[0-3],[a-f0-9]+$":
type: object
$ref: mc-peripheral-props.yaml#
additionalProperties: true
properties:
reg-io-width:
enum: [1, 2]
description:
Data width in bytes (1 or 2). If omitted, default of 1 is used.
required:
- samsung,srom-timing
required:
- compatible
- reg
additionalProperties: false
examples:
- |
// Example: basic definition, no banks are configured
memory-controller@12560000 {
compatible = "samsung,exynos4210-srom";
reg = <0x12560000 0x14>;
};
- |
// Example: SROMc with SMSC911x ethernet chip on bank 3
memory-controller@12570000 {
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x04000000 0x20000 // Bank0
1 0 0x05000000 0x20000 // Bank1
2 0 0x06000000 0x20000 // Bank2
3 0 0x07000000 0x20000>; // Bank3
compatible = "samsung,exynos4210-srom";
reg = <0x12570000 0x14>;
ethernet@3,0 {
compatible = "smsc,lan9115";
reg = <3 0 0x10000>; // Bank 3, offset = 0
phy-mode = "mii";
interrupt-parent = <&gpx0>;
interrupts = <5 8>;
reg-io-width = <2>;
smsc,irq-push-pull;
smsc,force-internal-phy;
samsung,srom-page-mode;
samsung,srom-timing = <9 12 1 9 1 1>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ddr.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ddr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale DDR memory controller
maintainers:
- Borislav Petkov <bp@alien8.de>
- York Sun <york.sun@nxp.com>
properties:
$nodename:
pattern: "^memory-controller@[0-9a-f]+$"
compatible:
oneOf:
- items:
- enum:
- fsl,qoriq-memory-controller-v4.4
- fsl,qoriq-memory-controller-v4.5
- fsl,qoriq-memory-controller-v4.7
- fsl,qoriq-memory-controller-v5.0
- const: fsl,qoriq-memory-controller
- enum:
- fsl,bsc9132-memory-controller
- fsl,mpc8536-memory-controller
- fsl,mpc8540-memory-controller
- fsl,mpc8541-memory-controller
- fsl,mpc8544-memory-controller
- fsl,mpc8548-memory-controller
- fsl,mpc8555-memory-controller
- fsl,mpc8560-memory-controller
- fsl,mpc8568-memory-controller
- fsl,mpc8569-memory-controller
- fsl,mpc8572-memory-controller
- fsl,mpc8349-memory-controller
- fsl,p1020-memory-controller
- fsl,p1021-memory-controller
- fsl,p2020-memory-controller
- fsl,qoriq-memory-controller
- nxp,imx9-memory-controller
interrupts:
maxItems: 1
little-endian:
description:
Specifies little-endian access to registers. If omitted, big-endian will
be used.
type: boolean
reg:
items:
- description: Controller register space
- description: Inject register space
minItems: 1
reg-names:
items:
- const: ctrl
- const: inject
minItems: 1
required:
- compatible
- interrupts
- reg
allOf:
- if:
properties:
compatible:
contains:
enum:
- nxp,imx9-memory-controller
then:
properties:
reg:
minItems: 2
reg-names:
minItems: 2
else:
properties:
reg:
maxItems: 1
reg-names: false
additionalProperties: false
examples:
- |
memory-controller@2000 {
compatible = "fsl,bsc9132-memory-controller";
reg = <0x2000 0x1000>;
interrupts = <16 2 1 8>;
};
- |
memory-controller@8000 {
compatible = "fsl,qoriq-memory-controller-v4.7",
"fsl,qoriq-memory-controller";
reg = <0x8000 0x1000>;
interrupts = <16 2 1 23>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ifc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ifc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: FSL/NXP Integrated Flash Controller
maintainers:
- Shawn Guo <shawnguo@kernel.org>
description: |
NXP's integrated flash controller (IFC) is an advanced version of the
enhanced local bus controller which includes similar programming and signal
interfaces with an extended feature set. The IFC provides access to multiple
external memory types, such as NAND flash (SLC and MLC), NOR flash, EPROM,
SRAM and other memories where address and data are shared on a bus.
properties:
$nodename:
pattern: "^memory-controller@[0-9a-f]+$"
compatible:
const: fsl,ifc
"#address-cells":
enum: [2, 3]
description: |
Should be either two or three. The first cell is the chipselect
number, and the remaining cells are the offset into the chipselect.
"#size-cells":
enum: [1, 2]
description: |
Either one or two, depending on how large each chipselect can be.
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 2
description: |
IFC may have one or two interrupts. If two interrupt specifiers are
present, the first is the "common" interrupt (CM_EVTER_STAT), and the
second is the NAND interrupt (NAND_EVTER_STAT). If there is only one,
that interrupt reports both types of event.
little-endian:
type: boolean
description: |
If this property is absent, the big-endian mode will be in use as default
for registers.
ranges:
description: |
Each range corresponds to a single chipselect, and covers the entire
access window as configured.
patternProperties:
"^nand@[a-f0-9]+(,[a-f0-9]+)+$":
type: object
properties:
compatible:
const: fsl,ifc-nand
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
patternProperties:
"^partition@[0-9a-f]+":
$ref: /schemas/mtd/partitions/partition.yaml#
deprecated: true
required:
- compatible
- reg
additionalProperties: false
"(flash|fpga|board-control|cpld)@[a-f0-9]+(,[a-f0-9]+)+$":
type: object
oneOf:
- $ref: /schemas/board/fsl,fpga-qixis.yaml#
- $ref: /schemas/mtd/mtd-physmap.yaml#
unevaluatedProperties: false
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
memory-controller@ffe1e000 {
compatible = "fsl,ifc";
#address-cells = <2>;
#size-cells = <1>;
reg = <0x0 0xffe1e000 0 0x2000>;
interrupts = <16 2 19 2>;
little-endian;
/* NOR, NAND Flashes and CPLD on board */
ranges = <0x0 0x0 0x0 0xee000000 0x02000000>,
<0x1 0x0 0x0 0xffa00000 0x00010000>,
<0x3 0x0 0x0 0xffb00000 0x00020000>;
flash@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x2000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
/* 32MB for user data */
reg = <0x0 0x02000000>;
label = "NOR Data";
};
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,imx-weim-peripherals.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,imx-weim-peripherals.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: i.MX WEIM Bus Peripheral Nodes
maintainers:
- Shawn Guo <shawnguo@kernel.org>
- Sascha Hauer <s.hauer@pengutronix.de>
description:
This binding is meant for the child nodes of the WEIM node. The node
represents any device connected to the WEIM bus. It may be a Flash chip,
RAM chip or Ethernet controller, etc. These properties are meant for
configuring the WEIM settings/timings and will accompany the bindings
supported by the respective device.
properties:
reg: true
fsl,weim-cs-timing:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
Timing values for the child node.
minItems: 2
maxItems: 6
# the WEIM child will have its own native properties
additionalProperties: true
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,imx-weim.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,imx-weim.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: i.MX Wireless External Interface Module (WEIM)
maintainers:
- Shawn Guo <shawnguo@kernel.org>
- Sascha Hauer <s.hauer@pengutronix.de>
description:
The term "wireless" does not imply that the WEIM is literally an interface
without wires. It simply means that this module was originally designed for
wireless and mobile applications that use low-power technology. The actual
devices are instantiated from the child nodes of a WEIM node.
properties:
$nodename:
pattern: "^memory-controller@[0-9a-f]+$"
compatible:
oneOf:
- enum:
- fsl,imx1-weim
- fsl,imx27-weim
- fsl,imx50-weim
- fsl,imx51-weim
- fsl,imx6q-weim
- items:
- enum:
- fsl,imx31-weim
- fsl,imx35-weim
- const: fsl,imx27-weim
- items:
- enum:
- fsl,imx6sx-weim
- fsl,imx6ul-weim
- const: fsl,imx6q-weim
"#address-cells":
const: 2
"#size-cells":
const: 1
reg:
maxItems: 1
clocks:
maxItems: 1
interrupts:
maxItems: 1
ranges: true
fsl,weim-cs-gpr:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
Phandle to the system General Purpose Register controller that contains
WEIM CS GPR register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0]
should be set up as one of the following 4 possible values depending on
the CS space configuration.
IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3
---------------------------------------------
05 128M 0M 0M 0M
033 64M 64M 0M 0M
0113 64M 32M 32M 0M
01111 32M 32M 32M 32M
In case that the property is absent, the reset value or what bootloader
sets up in IOMUXC_GPR1[11:0] will be used.
fsl,burst-clk-enable:
type: boolean
description:
The presence of this property indicates that the weim bus should operate
in Burst Clock Mode.
fsl,continuous-burst-clk:
type: boolean
description:
Make Burst Clock to output continuous clock. Without this option Burst
Clock will output clock only when necessary.
patternProperties:
"^.*@[0-7],[0-9a-f]+$":
type: object
description: Devices attached to chip selects are represented as subnodes.
$ref: fsl,imx-weim-peripherals.yaml
additionalProperties: true
required:
- fsl,weim-cs-timing
required:
- compatible
- reg
- clocks
- "#address-cells"
- "#size-cells"
- ranges
allOf:
- if:
properties:
compatible:
not:
contains:
enum:
- fsl,imx50-weim
- fsl,imx6q-weim
then:
properties:
fsl,weim-cs-gpr: false
fsl,burst-clk-enable: false
- if:
not:
required:
- fsl,burst-clk-enable
then:
properties:
fsl,continuous-burst-clk: false
- if:
properties:
compatible:
contains:
const: fsl,imx1-weim
then:
patternProperties:
"^.*@[0-7],[0-9a-f]+$":
properties:
fsl,weim-cs-timing:
items:
- description: CSxU
- description: CSxL
- if:
properties:
compatible:
contains:
enum:
- fsl,imx27-weim
- fsl,imx31-weim
- fsl,imx35-weim
then:
patternProperties:
"^.*@[0-7],[0-9a-f]+$":
properties:
fsl,weim-cs-timing:
items:
- description: CSCRxU
- description: CSCRxL
- description: CSCRxA
- if:
properties:
compatible:
contains:
enum:
- fsl,imx50-weim
- fsl,imx51-weim
- fsl,imx6q-weim
- fsl,imx6sx-weim
- fsl,imx6ul-weim
then:
patternProperties:
"^.*@[0-7],[0-9a-f]+$":
properties:
fsl,weim-cs-timing:
items:
- description: CSxGCR1
- description: CSxGCR2
- description: CSxRCR1
- description: CSxRCR2
- description: CSxWCR1
- description: CSxWCR2
additionalProperties: false
examples:
- |
memory-controller@21b8000 {
compatible = "fsl,imx6q-weim";
reg = <0x021b8000 0x4000>;
clocks = <&clks 196>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x08000000 0x08000000>;
fsl,weim-cs-gpr = <&gpr>;
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x02000000>;
#address-cells = <1>;
#size-cells = <1>;
bank-width = <2>;
fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
0x0000c000 0x1404a38e 0x00000000>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: i.MX8M DDR Controller
maintainers:
- Peng Fan <peng.fan@nxp.com>
description:
The DDRC block is integrated in i.MX8M for interfacing with DDR based
memories.
It supports switching between different frequencies at runtime but during
this process RAM itself becomes briefly inaccessible so actual frequency
switching is implemented by TF-A code which runs from a SRAM area.
The Linux driver for the DDRC doesn't even map registers (they're included
for the sake of "describing hardware"), it mostly just exposes firmware
capabilities through standard Linux mechanism like devfreq and OPP tables.
properties:
compatible:
items:
- enum:
- fsl,imx8mn-ddrc
- fsl,imx8mm-ddrc
- fsl,imx8mq-ddrc
- const: fsl,imx8m-ddrc
reg:
maxItems: 1
description:
Base address and size of DDRC CTL area.
This is not currently mapped by the imx8m-ddrc driver.
clocks:
maxItems: 4
clock-names:
items:
- const: core
- const: pll
- const: alt
- const: apb
operating-points-v2: true
opp-table:
type: object
required:
- reg
- compatible
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8mm-clock.h>
ddrc: memory-controller@3d400000 {
compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
reg = <0x3d400000 0x400000>;
clock-names = "core", "pll", "alt", "apb";
clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
<&clk IMX8MM_DRAM_PLL>,
<&clk IMX8MM_CLK_DRAM_ALT>,
<&clk IMX8MM_CLK_DRAM_APB>;
operating-points-v2 = <&ddrc_opp_table>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/fsl/mmdc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/fsl/mmdc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Multi Mode DDR controller (MMDC)
maintainers:
- Shawn Guo <shawnguo@kernel.org>
- Sascha Hauer <s.hauer@pengutronix.de>
- Fabio Estevam <festevam@gmail.com>
properties:
compatible:
oneOf:
- const: fsl,imx6q-mmdc
- items:
- enum:
- fsl,imx6qp-mmdc
- fsl,imx6sl-mmdc
- fsl,imx6sll-mmdc
- fsl,imx6sx-mmdc
- fsl,imx6ul-mmdc
- fsl,imx7ulp-mmdc
- const: fsl,imx6q-mmdc
reg:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx6qdl-clock.h>
memory-controller@21b0000 {
compatible = "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
};
memory-controller@21b4000 {
compatible = "fsl,imx6q-mmdc";
reg = <0x021b4000 0x4000>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc-peripherals.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ingenic,nemc-peripherals.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ingenic SoCs NAND / External Memory Controller (NEMC)
maintainers:
- Paul Cercueil <paul@crapouillou.net>
properties:
reg:
minItems: 1
maxItems: 255
ingenic,nemc-bus-width:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [8, 16]
description: Specifies the bus width in bits.
ingenic,nemc-tAS:
$ref: /schemas/types.yaml#/definitions/uint32
description: Address setup time in nanoseconds.
ingenic,nemc-tAH:
$ref: /schemas/types.yaml#/definitions/uint32
description: Address hold time in nanoseconds.
ingenic,nemc-tBP:
$ref: /schemas/types.yaml#/definitions/uint32
description: Burst pitch time in nanoseconds.
ingenic,nemc-tAW:
$ref: /schemas/types.yaml#/definitions/uint32
description: Address wait time in nanoseconds.
ingenic,nemc-tSTRV:
$ref: /schemas/types.yaml#/definitions/uint32
description: Static memory recovery time in nanoseconds.
required:
- reg
additionalProperties: true
...
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ingenic,nemc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ingenic SoCs NAND / External Memory Controller (NEMC)
maintainers:
- Paul Cercueil <paul@crapouillou.net>
properties:
$nodename:
pattern: "^memory-controller@[0-9a-f]+$"
compatible:
oneOf:
- enum:
- ingenic,jz4740-nemc
- ingenic,jz4780-nemc
- items:
- const: ingenic,jz4725b-nemc
- const: ingenic,jz4740-nemc
"#address-cells":
const: 2
"#size-cells":
const: 1
ranges: true
reg:
maxItems: 1
clocks:
maxItems: 1
patternProperties:
".*@[0-9]+$":
type: object
$ref: mc-peripheral-props.yaml#
additionalProperties: true
required:
- compatible
- "#address-cells"
- "#size-cells"
- ranges
- reg
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/ingenic,jz4780-cgu.h>
#include <dt-bindings/gpio/gpio.h>
nemc: memory-controller@13410000 {
compatible = "ingenic,jz4780-nemc";
reg = <0x13410000 0x10000>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <1 0 0x1b000000 0x1000000>,
<2 0 0x1a000000 0x1000000>,
<3 0 0x19000000 0x1000000>,
<4 0 0x18000000 0x1000000>,
<5 0 0x17000000 0x1000000>,
<6 0 0x16000000 0x1000000>;
clocks = <&cgu JZ4780_CLK_NEMC>;
ethernet@6 {
compatible = "davicom,dm9000";
davicom,no-eeprom;
pinctrl-names = "default";
pinctrl-0 = <&pins_nemc_cs6>;
reg = <6 0 1>, /* addr */
<6 2 1>; /* data */
ingenic,nemc-tAS = <15>;
ingenic,nemc-tAH = <10>;
ingenic,nemc-tBP = <20>;
ingenic,nemc-tAW = <50>;
ingenic,nemc-tSTRV = <100>;
reset-gpios = <&gpf 12 GPIO_ACTIVE_HIGH>;
vcc-supply = <&eth0_power>;
interrupt-parent = <&gpe>;
interrupts = <19 4>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel IXP4xx Expansion Bus Controller
description: |
The IXP4xx expansion bus controller handles access to devices on the
memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
including IXP42x, IXP43x, IXP45x and IXP46x.
maintainers:
- Linus Walleij <linusw@kernel.org>
properties:
$nodename:
pattern: '^bus@[0-9a-f]+$'
compatible:
items:
- enum:
- intel,ixp42x-expansion-bus-controller
- intel,ixp43x-expansion-bus-controller
- intel,ixp45x-expansion-bus-controller
- intel,ixp46x-expansion-bus-controller
- const: syscon
reg:
description: Control registers for the expansion bus, these are not
inside the memory range handled by the expansion bus.
maxItems: 1
native-endian:
$ref: /schemas/types.yaml#/definitions/flag
description: The IXP4xx has a peculiar MMIO access scheme, as it changes
the access pattern for words (swizzling) on the bus depending on whether
the SoC is running in big-endian or little-endian mode. Thus the
registers must always be accessed using native endianness.
"#address-cells":
description: |
The first cell is the chip select number.
The second cell is the address offset within the bank.
const: 2
"#size-cells":
const: 1
ranges: true
dma-ranges: true
patternProperties:
"^.*@[0-7],[0-9a-f]+$":
description: Devices attached to chip selects are represented as
subnodes.
type: object
$ref: /schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#
additionalProperties: true
required:
- compatible
- reg
- native-endian
- "#address-cells"
- "#size-cells"
- ranges
- dma-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
bus@50000000 {
compatible = "intel,ixp42x-expansion-bus-controller", "syscon";
reg = <0xc4000000 0x28>;
native-endian;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0x0 0x50000000 0x01000000>,
<1 0x0 0x51000000 0x01000000>;
dma-ranges = <0 0x0 0x50000000 0x01000000>,
<1 0x0 0x51000000 0x01000000>;
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
reg = <0 0x00000000 0x1000000>;
intel,ixp4xx-eb-t3 = <3>;
intel,ixp4xx-eb-cycle-type = <0>;
intel,ixp4xx-eb-byte-access-on-halfword = <1>;
intel,ixp4xx-eb-write-enable = <1>;
intel,ixp4xx-eb-byte-access = <0>;
};
serial@1,0 {
compatible = "exar,xr16l2551", "ns8250";
reg = <1 0x00000000 0x10>;
interrupt-parent = <&gpio0>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <1843200>;
intel,ixp4xx-eb-t3 = <3>;
intel,ixp4xx-eb-cycle-type = <1>;
intel,ixp4xx-eb-write-enable = <1>;
intel,ixp4xx-eb-byte-access = <1>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Peripheral properties for Intel IXP4xx Expansion Bus
description:
The IXP4xx expansion bus controller handles access to devices on the
memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
including IXP42x, IXP43x, IXP45x and IXP46x.
maintainers:
- Linus Walleij <linusw@kernel.org>
properties:
intel,ixp4xx-eb-t1:
description: Address timing, extend address phase with n cycles.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 3
intel,ixp4xx-eb-t2:
description: Setup chip select timing, extend setup phase with n cycles.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 3
intel,ixp4xx-eb-t3:
description: Strobe timing, extend strobe phase with n cycles.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
intel,ixp4xx-eb-t4:
description: Hold timing, extend hold phase with n cycles.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 3
intel,ixp4xx-eb-t5:
description: Recovery timing, extend recovery phase with n cycles.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
intel,ixp4xx-eb-cycle-type:
description: The type of cycles to use on the expansion bus for this
chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2]
intel,ixp4xx-eb-byte-access-on-halfword:
description: Allow byte read access on half word devices.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
intel,ixp4xx-eb-hpi-hrdy-pol-high:
description: Set HPI HRDY polarity to active high when using HPI.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
intel,ixp4xx-eb-mux-address-and-data:
description: Multiplex address and data on the data bus.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
intel,ixp4xx-eb-ahb-split-transfers:
description: Enable AHB split transfers.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
intel,ixp4xx-eb-write-enable:
description: Enable write cycles.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
intel,ixp4xx-eb-byte-access:
description: Expansion bus uses only 8 bits. The default is to use
16 bits.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
additionalProperties: true
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/marvell,mvebu-sdram-controller.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/marvell,mvebu-sdram-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell MVEBU SDRAM controller
maintainers:
- Jan Luebbe <jlu@pengutronix.de>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:
const: marvell,armada-xp-sdram-controller
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
memory-controller@1400 {
compatible = "marvell,armada-xp-sdram-controller";
reg = <0x1400 0x500>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/mc-peripheral-props.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Peripheral-specific properties for a Memory Controller bus.
description:
Many Memory Controllers need to add properties to peripheral devices.
They could be common properties like reg or they could be controller
specific like delay in clock or data lines, etc. These properties need
to be defined in the peripheral node because they are per-peripheral
and there can be multiple peripherals attached to a controller. All
those properties are listed here. The controller specific properties
should go in their own separate schema that should be referenced
from here.
maintainers:
- Marek Vasut <marex@denx.de>
properties:
reg:
description: Bank number, base address and size of the device.
bank-width:
$ref: /schemas/types.yaml#/definitions/uint32
description: Bank width of the device, in bytes.
enum: [1, 2, 4]
required:
- reg
# The controller specific properties go here.
allOf:
- $ref: st,stm32-fmc2-ebi-props.yaml#
- $ref: ingenic,nemc-peripherals.yaml#
- $ref: intel,ixp4xx-expansion-peripheral-props.yaml#
- $ref: qcom,ebi2-peripheral-props.yaml#
- $ref: samsung,exynos4210-srom-peripheral-props.yaml#
- $ref: ti,gpmc-child.yaml#
- $ref: fsl/fsl,imx-weim-peripherals.yaml
additionalProperties: true
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/mediatek,mt7621-memc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/mediatek,mt7621-memc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MT7621 SDRAM controller
maintainers:
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
properties:
compatible:
items:
- const: mediatek,mt7621-memc
- const: syscon
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
memory-controller@5000 {
compatible = "mediatek,mt7621-memc", "syscon";
reg = <0x5000 0x1000>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2020 MediaTek Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SMI (Smart Multimedia Interface) Common
maintainers:
- Yong Wu <yong.wu@mediatek.com>
description: |
The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
MediaTek SMI have two generations of HW architecture, here is the list
which generation the SoCs use:
generation 1: mt2701 and mt7623.
generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8188, mt8192 and mt8195.
There's slight differences between the two SMI, for generation 2, the
register which control the iommu port is at each larb's register base. But
for generation 1, the register is at smi ao base(smi always on register
base). Besides that, the smi async clock should be prepared and enabled for
SMI generation 1 to transform the smi clock into emi clock domain, but that is
not needed for SMI generation 2.
properties:
compatible:
oneOf:
- enum:
- mediatek,mt2701-smi-common
- mediatek,mt2712-smi-common
- mediatek,mt6779-smi-common
- mediatek,mt6795-smi-common
- mediatek,mt6893-smi-common
- mediatek,mt8167-smi-common
- mediatek,mt8173-smi-common
- mediatek,mt8183-smi-common
- mediatek,mt8186-smi-common
- mediatek,mt8188-smi-common-vdo
- mediatek,mt8188-smi-common-vpp
- mediatek,mt8192-smi-common
- mediatek,mt8195-smi-common-vdo
- mediatek,mt8195-smi-common-vpp
- mediatek,mt8195-smi-sub-common
- mediatek,mt8365-smi-common
- description: for mt7623
items:
- const: mediatek,mt7623-smi-common
- const: mediatek,mt2701-smi-common
reg:
maxItems: 1
power-domains:
maxItems: 1
clocks:
description: |
apb and smi are mandatory. the async is only for generation 1 smi HW.
gals(global async local sync) also is optional, see below.
minItems: 2
items:
- description: apb is Advanced Peripheral Bus clock, It's the clock for
setting the register.
- description: smi is the clock for transfer data and command.
- description: Either asynchronous clock to help transform the smi clock
into the emi clock domain on Gen1 h/w, or the path0 clock of gals.
- description: gals1 is the path1 clock of gals.
clock-names:
minItems: 2
maxItems: 4
mediatek,smi:
$ref: /schemas/types.yaml#/definitions/phandle
description: a phandle to the smi-common node above. Only for sub-common.
required:
- compatible
- reg
- power-domains
- clocks
- clock-names
allOf:
- if: # only for gen1 HW
properties:
compatible:
contains:
enum:
- mediatek,mt2701-smi-common
then:
properties:
clocks:
minItems: 3
maxItems: 3
clock-names:
items:
- const: apb
- const: smi
- const: async
- if: # only for sub common
properties:
compatible:
contains:
enum:
- mediatek,mt8195-smi-sub-common
then:
required:
- mediatek,smi
properties:
clocks:
minItems: 3
maxItems: 3
clock-names:
items:
- const: apb
- const: smi
- const: gals0
else:
properties:
mediatek,smi: false
- if: # for gen2 HW that have gals
properties:
compatible:
enum:
- mediatek,mt6779-smi-common
- mediatek,mt8183-smi-common
- mediatek,mt8186-smi-common
- mediatek,mt8192-smi-common
- mediatek,mt8195-smi-common-vdo
- mediatek,mt8195-smi-common-vpp
- mediatek,mt8365-smi-common
then:
properties:
clocks:
minItems: 4
maxItems: 4
clock-names:
items:
- const: apb
- const: smi
- const: gals0
- const: gals1
- if: # for gen2 HW that don't have gals
properties:
compatible:
enum:
- mediatek,mt2712-smi-common
- mediatek,mt6795-smi-common
- mediatek,mt8167-smi-common
- mediatek,mt8173-smi-common
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: apb
- const: smi
additionalProperties: false
examples:
- |+
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/power/mt8173-power.h>
smi_common: smi@14022000 {
compatible = "mediatek,mt8173-smi-common";
reg = <0x14022000 0x1000>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_SMI_COMMON>;
clock-names = "apb", "smi";
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2020 MediaTek Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-larb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SMI (Smart Multimedia Interface) Local Arbiter
maintainers:
- Yong Wu <yong.wu@mediatek.com>
description: |
The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
properties:
compatible:
oneOf:
- enum:
- mediatek,mt2701-smi-larb
- mediatek,mt2712-smi-larb
- mediatek,mt6779-smi-larb
- mediatek,mt6795-smi-larb
- mediatek,mt6893-smi-larb
- mediatek,mt8167-smi-larb
- mediatek,mt8173-smi-larb
- mediatek,mt8183-smi-larb
- mediatek,mt8186-smi-larb
- mediatek,mt8188-smi-larb
- mediatek,mt8192-smi-larb
- mediatek,mt8195-smi-larb
- description: for mt7623
items:
- const: mediatek,mt7623-smi-larb
- const: mediatek,mt2701-smi-larb
- items:
- const: mediatek,mt8365-smi-larb
- const: mediatek,mt8186-smi-larb
reg:
maxItems: 1
clocks:
description: |
apb and smi are mandatory. gals(global async local sync) is optional.
minItems: 2
items:
- description: apb is Advanced Peripheral Bus clock, It's the clock for
setting the register.
- description: smi is the clock for transfer data and command.
- description: the clock for gals.
clock-names:
minItems: 2
maxItems: 3
power-domains:
maxItems: 1
mediatek,smi:
$ref: /schemas/types.yaml#/definitions/phandle
description: a phandle to the smi_common node.
mediatek,larb-id:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 31
description: the hardware id of this larb. It's only required when this
hardware id is not consecutive from its M4U point of view.
required:
- compatible
- reg
- clocks
- clock-names
- power-domains
allOf:
- if: # HW has gals
properties:
compatible:
enum:
- mediatek,mt8183-smi-larb
- mediatek,mt8186-smi-larb
- mediatek,mt8188-smi-larb
- mediatek,mt8195-smi-larb
then:
properties:
clocks:
minItems: 2
maxItems: 3
clock-names:
minItems: 2
items:
- const: apb
- const: smi
- const: gals
else:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: apb
- const: smi
- if:
properties:
compatible:
contains:
enum:
- mediatek,mt2701-smi-larb
- mediatek,mt2712-smi-larb
- mediatek,mt6779-smi-larb
- mediatek,mt8186-smi-larb
- mediatek,mt8188-smi-larb
- mediatek,mt8192-smi-larb
- mediatek,mt8195-smi-larb
then:
required:
- mediatek,larb-id
additionalProperties: false
examples:
- |+
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/power/mt8173-power.h>
larb1: larb@16010000 {
compatible = "mediatek,mt8173-smi-larb";
reg = <0x16010000 0x1000>;
mediatek,smi = <&smi_common>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
clocks = <&vdecsys CLK_VDEC_CKEN>,
<&vdecsys CLK_VDEC_LARB_CKEN>;
clock-names = "apb", "smi";
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/mvebu-devbus.txt
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Device tree bindings for MVEBU Device Bus controllers
The Device Bus controller available in some Marvell's SoC allows to control
different types of standard memory and I/O devices such as NOR, NAND, and FPGA.
The actual devices are instantiated from the child nodes of a Device Bus node.
Required properties:
- compatible: Armada 370/XP SoC are supported using the
"marvell,mvebu-devbus" compatible string.
Orion5x SoC are supported using the
"marvell,orion-devbus" compatible string.
- reg: A resource specifier for the register space.
This is the base address of a chip select within
the controller's register space.
(see the example below)
- #address-cells: Must be set to 1
- #size-cells: Must be set to 1
- ranges: Must be set up to reflect the memory layout with four
integer values for each chip-select line in use:
0 <physical address of mapping> <size>
Optional properties:
- devbus,keep-config This property can optionally be used to keep
using the timing parameters set by the
bootloader. It makes all the timing properties
described below unused.
Timing properties for child nodes:
Read parameters:
- devbus,turn-off-ps: Defines the time during which the controller does not
drive the AD bus after the completion of a device read.
This prevents contentions on the Device Bus after a read
cycle from a slow device.
Mandatory, except if devbus,keep-config is used.
- devbus,bus-width: Defines the bus width, in bits (e.g. <16>).
Mandatory, except if devbus,keep-config is used.
- devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
to read data sample. This parameter is useful for
synchronous pipelined devices, where the address
precedes the read data by one or two cycles.
Mandatory, except if devbus,keep-config is used.
- devbus,acc-first-ps: Defines the time delay from the negation of
ALE[0] to the cycle that the first read data is sampled
by the controller.
Mandatory, except if devbus,keep-config is used.
- devbus,acc-next-ps: Defines the time delay between the cycle that
samples data N and the cycle that samples data N+1
(in burst accesses).
Mandatory, except if devbus,keep-config is used.
- devbus,rd-setup-ps: Defines the time delay between DEV_CSn assertion to
DEV_OEn assertion. If set to 0 (default),
DEV_OEn and DEV_CSn are asserted at the same cycle.
This parameter has no affect on <acc-first-ps> parameter
(no affect on first data sample). Set <rd-setup-ps>
to a value smaller than <acc-first-ps>.
Mandatory for "marvell,mvebu-devbus" compatible string,
except if devbus,keep-config is used.
- devbus,rd-hold-ps: Defines the time between the last data sample to the
de-assertion of DEV_CSn. If set to 0 (default),
DEV_OEn and DEV_CSn are de-asserted at the same cycle
(the cycle of the last data sample).
This parameter has no affect on DEV_OEn de-assertion.
DEV_OEn is always de-asserted the next cycle after
last data sampled. Also this parameter has no
affect on <turn-off-ps> parameter.
Set <rd-hold-ps> to a value smaller than <turn-off-ps>.
Mandatory for "marvell,mvebu-devbus" compatible string,
except if devbus,keep-config is used.
Write parameters:
- devbus,ale-wr-ps: Defines the time delay from the ALE[0] negation cycle
to the DEV_WEn assertion.
Mandatory.
- devbus,wr-low-ps: Defines the time during which DEV_WEn is active.
A[2:0] and Data are kept valid as long as DEV_WEn
is active. This parameter defines the setup time of
address and data to DEV_WEn rise.
Mandatory.
- devbus,wr-high-ps: Defines the time during which DEV_WEn is kept
inactive (high) between data beats of a burst write.
DEV_A[2:0] and Data are kept valid (do not toggle) for
<wr-high-ps> - <tick> ps.
This parameter defines the hold time of address and
data after DEV_WEn rise.
Mandatory.
- devbus,sync-enable: Synchronous device enable.
1: True
0: False
Mandatory for "marvell,mvebu-devbus" compatible string,
except if devbus,keep-config is used.
An example for an Armada XP GP board, with a 16 MiB NOR device as child
is showed below. Note that the Device Bus driver is in charge of allocating
the mbus address decoding window for each of its child devices.
The window is created using the chip select specified in the child
device node together with the base address and size specified in the ranges
property. For instance, in the example below the allocated decoding window
will start at base address 0xf0000000, with a size 0x1000000 (16 MiB)
for chip select 0 (a.k.a DEV_BOOTCS).
This address window handling is done in this mvebu-devbus only as a temporary
solution. It will be removed when the support for mbus device tree binding is
added.
The reg property implicitly specifies the chip select as this:
0x10400: DEV_BOOTCS
0x10408: DEV_CS0
0x10410: DEV_CS1
0x10418: DEV_CS2
0x10420: DEV_CS3
Example:
devbus-bootcs@d0010400 {
ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf0000000, size 0x1000000 */
#address-cells = <1>;
#size-cells = <1>;
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
flash@0 {
compatible = "cfi-flash";
/* 16 MiB */
reg = <0 0x1000000>;
bank-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
/*
* We split the 16 MiB in two partitions,
* just as an example.
*/
partition@0 {
label = "First";
reg = <0 0x800000>;
};
partition@800000 {
label = "Second";
reg = <0x800000 0x800000>;
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/nuvoton,npcm-memory-controller.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nuvoton,npcm-memory-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Nuvoton NPCM Memory Controller
maintainers:
- Marvin Lin <kflin@nuvoton.com>
- Stanley Chu <yschu@nuvoton.com>
description: |
The Nuvoton BMC SoC supports DDR4 memory with or without ECC (error correction
check).
The memory controller supports single bit error correction, double bit error
detection (in-line ECC in which a section (1/8th) of the memory device used to
store data is used for ECC storage).
Note, the bootloader must configure ECC mode for the memory controller.
properties:
compatible:
enum:
- nuvoton,npcm750-memory-controller
- nuvoton,npcm845-memory-controller
reg:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
mc: memory-controller@f0824000 {
compatible = "nuvoton,npcm750-memory-controller";
reg = <0xf0824000 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra124 SoC External Memory Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
description: |
The EMC interfaces with the off-chip SDRAM to service the request stream
sent from the memory controller.
properties:
compatible:
enum:
- nvidia,tegra114-emc
- nvidia,tegra124-emc
reg:
maxItems: 1
clocks:
items:
- description: external memory clock
clock-names:
items:
- const: emc
interrupts:
maxItems: 1
"#interconnect-cells":
const: 0
nvidia,memory-controller:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle of the memory controller node
power-domains:
maxItems: 1
description:
Phandle of the SoC "core" power domain.
operating-points-v2:
description:
Should contain freqs and voltages and opp-supported-hw property, which
is a bitfield indicating SoC speedo ID mask.
patternProperties:
"^emc-timings-[0-9]+$":
type: object
additionalProperties: false
properties:
nvidia,ram-code:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that
this timing set is used for
patternProperties:
"^timing-[0-9]+$":
type: object
properties:
clock-frequency:
description:
external memory clock rate in Hz
minimum: 1000000
maximum: 1000000000
nvidia,emc-auto-cal-config:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_AUTO_CAL_CONFIG register for this set of
timings
nvidia,emc-auto-cal-config2:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_AUTO_CAL_CONFIG2 register for this set of
timings
nvidia,emc-auto-cal-config3:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_AUTO_CAL_CONFIG3 register for this set of
timings
nvidia,emc-auto-cal-interval:
description:
pad calibration interval in microseconds
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 2097151
nvidia,emc-bgbias-ctl0:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_BGBIAS_CTL0 register for this set of timings
nvidia,emc-cfg:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_CFG register for this set of timings
nvidia,emc-cfg-2:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_CFG_2 register for this set of timings
nvidia,emc-ctt-term-ctrl:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_CTT_TERM_CTRL register for this set of timings
nvidia,emc-mode-1:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_MRW register for this set of timings
nvidia,emc-mode-2:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_MRW2 register for this set of timings
nvidia,emc-mode-4:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_MRW4 register for this set of timings
nvidia,emc-mode-reset:
$ref: /schemas/types.yaml#/definitions/uint32
description:
reset value of the EMC_MRS register for this set of timings
nvidia,emc-mrs-wait-cnt:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMR_MRS_WAIT_CNT register for this set of timings
nvidia,emc-sel-dpd-ctrl:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_SEL_DPD_CTRL register for this set of timings
nvidia,emc-xm2dqspadctrl2:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_XM2DQSPADCTRL2 register for this set of timings
nvidia,emc-zcal-cnt-long:
description:
number of EMC clocks to wait before issuing any commands after
clock change
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 1023
nvidia,emc-zcal-interval:
$ref: /schemas/types.yaml#/definitions/uint32
description:
value of the EMC_ZCAL_INTERVAL register for this set of timings
nvidia,emc-configuration:
description:
EMC timing characterization data. These are the registers (see
section "20.11.2 EMC Registers" in the Tegra114 TRM or section
"15.6.2 EMC Registers" in the Tegra124 TRM) whose values need to
be specified, according to the board documentation.
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 97
maxItems: 143
required:
- clock-frequency
- nvidia,emc-auto-cal-config
- nvidia,emc-auto-cal-config2
- nvidia,emc-auto-cal-config3
- nvidia,emc-auto-cal-interval
- nvidia,emc-cfg
- nvidia,emc-ctt-term-ctrl
- nvidia,emc-mode-1
- nvidia,emc-mode-2
- nvidia,emc-mode-4
- nvidia,emc-mode-reset
- nvidia,emc-mrs-wait-cnt
- nvidia,emc-sel-dpd-ctrl
- nvidia,emc-xm2dqspadctrl2
- nvidia,emc-zcal-cnt-long
- nvidia,emc-zcal-interval
- nvidia,emc-configuration
additionalProperties: false
required:
- compatible
- reg
- clocks
- clock-names
- nvidia,memory-controller
- "#interconnect-cells"
- operating-points-v2
allOf:
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra124-emc
then:
patternProperties:
"^emc-timings-[0-9]+$":
patternProperties:
"^timing-[0-9]+$":
required:
- nvidia,emc-bgbias-ctl0
- nvidia,emc-cfg-2
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra124-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
mc: memory-controller@70019000 {
compatible = "nvidia,tegra124-mc";
reg = <0x70019000 0x1000>;
clocks = <&tegra_car TEGRA124_CLK_MC>;
clock-names = "mc";
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
#reset-cells = <1>;
#interconnect-cells = <1>;
};
external-memory-controller@7001b000 {
compatible = "nvidia,tegra124-emc";
reg = <0x7001b000 0x1000>;
clocks = <&car TEGRA124_CLK_EMC>;
clock-names = "emc";
nvidia,memory-controller = <&mc>;
operating-points-v2 = <&dvfs_opp_table>;
power-domains = <&domain>;
#interconnect-cells = <0>;
emc-timings-0 {
nvidia,ram-code = <3>;
timing-0 {
clock-frequency = <12750000>;
nvidia,emc-auto-cal-config = <0xa1430000>;
nvidia,emc-auto-cal-config2 = <0x00000000>;
nvidia,emc-auto-cal-config3 = <0x00000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-bgbias-ctl0 = <0x00000008>;
nvidia,emc-cfg = <0x73240000>;
nvidia,emc-cfg-2 = <0x000008c5>;
nvidia,emc-ctt-term-ctrl = <0x00000802>;
nvidia,emc-mode-1 = <0x80100003>;
nvidia,emc-mode-2 = <0x80200008>;
nvidia,emc-mode-4 = <0x00000000>;
nvidia,emc-mode-reset = <0x80001221>;
nvidia,emc-mrs-wait-cnt = <0x000e000e>;
nvidia,emc-sel-dpd-ctrl = <0x00040128>;
nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
nvidia,emc-zcal-cnt-long = <0x00000042>;
nvidia,emc-zcal-interval = <0x00000000>;
nvidia,emc-configuration = <
0x00000000 /* EMC_RC */
0x00000003 /* EMC_RFC */
0x00000000 /* EMC_RFC_SLR */
0x00000000 /* EMC_RAS */
0x00000000 /* EMC_RP */
0x00000004 /* EMC_R2W */
0x0000000a /* EMC_W2R */
0x00000003 /* EMC_R2P */
0x0000000b /* EMC_W2P */
0x00000000 /* EMC_RD_RCD */
0x00000000 /* EMC_WR_RCD */
0x00000003 /* EMC_RRD */
0x00000003 /* EMC_REXT */
0x00000000 /* EMC_WEXT */
0x00000006 /* EMC_WDV */
0x00000006 /* EMC_WDV_MASK */
0x00000006 /* EMC_QUSE */
0x00000002 /* EMC_QUSE_WIDTH */
0x00000000 /* EMC_IBDLY */
0x00000005 /* EMC_EINPUT */
0x00000005 /* EMC_EINPUT_DURATION */
0x00010000 /* EMC_PUTERM_EXTRA */
0x00000003 /* EMC_PUTERM_WIDTH */
0x00000000 /* EMC_PUTERM_ADJ */
0x00000000 /* EMC_CDB_CNTL_1 */
0x00000000 /* EMC_CDB_CNTL_2 */
0x00000000 /* EMC_CDB_CNTL_3 */
0x00000004 /* EMC_QRST */
0x0000000c /* EMC_QSAFE */
0x0000000d /* EMC_RDV */
0x0000000f /* EMC_RDV_MASK */
0x00000060 /* EMC_REFRESH */
0x00000000 /* EMC_BURST_REFRESH_NUM */
0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */
0x00000002 /* EMC_PDEX2WR */
0x00000002 /* EMC_PDEX2RD */
0x00000001 /* EMC_PCHG2PDEN */
0x00000000 /* EMC_ACT2PDEN */
0x00000007 /* EMC_AR2PDEN */
0x0000000f /* EMC_RW2PDEN */
0x00000005 /* EMC_TXSR */
0x00000005 /* EMC_TXSRDLL */
0x00000004 /* EMC_TCKE */
0x00000005 /* EMC_TCKESR */
0x00000004 /* EMC_TPD */
0x00000000 /* EMC_TFAW */
0x00000000 /* EMC_TRPAB */
0x00000005 /* EMC_TCLKSTABLE */
0x00000005 /* EMC_TCLKSTOP */
0x00000064 /* EMC_TREFBW */
0x00000000 /* EMC_FBIO_CFG6 */
0x00000000 /* EMC_ODT_WRITE */
0x00000000 /* EMC_ODT_READ */
0x106aa298 /* EMC_FBIO_CFG5 */
0x002c00a0 /* EMC_CFG_DIG_DLL */
0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
0x00064000 /* EMC_DLL_XFORM_DQS0 */
0x00064000 /* EMC_DLL_XFORM_DQS1 */
0x00064000 /* EMC_DLL_XFORM_DQS2 */
0x00064000 /* EMC_DLL_XFORM_DQS3 */
0x00064000 /* EMC_DLL_XFORM_DQS4 */
0x00064000 /* EMC_DLL_XFORM_DQS5 */
0x00064000 /* EMC_DLL_XFORM_DQS6 */
0x00064000 /* EMC_DLL_XFORM_DQS7 */
0x00064000 /* EMC_DLL_XFORM_DQS8 */
0x00064000 /* EMC_DLL_XFORM_DQS9 */
0x00064000 /* EMC_DLL_XFORM_DQS10 */
0x00064000 /* EMC_DLL_XFORM_DQS11 */
0x00064000 /* EMC_DLL_XFORM_DQS12 */
0x00064000 /* EMC_DLL_XFORM_DQS13 */
0x00064000 /* EMC_DLL_XFORM_DQS14 */
0x00064000 /* EMC_DLL_XFORM_DQS15 */
0x00000000 /* EMC_DLL_XFORM_QUSE0 */
0x00000000 /* EMC_DLL_XFORM_QUSE1 */
0x00000000 /* EMC_DLL_XFORM_QUSE2 */
0x00000000 /* EMC_DLL_XFORM_QUSE3 */
0x00000000 /* EMC_DLL_XFORM_QUSE4 */
0x00000000 /* EMC_DLL_XFORM_QUSE5 */
0x00000000 /* EMC_DLL_XFORM_QUSE6 */
0x00000000 /* EMC_DLL_XFORM_QUSE7 */
0x00000000 /* EMC_DLL_XFORM_ADDR0 */
0x00000000 /* EMC_DLL_XFORM_ADDR1 */
0x00000000 /* EMC_DLL_XFORM_ADDR2 */
0x00000000 /* EMC_DLL_XFORM_ADDR3 */
0x00000000 /* EMC_DLL_XFORM_ADDR4 */
0x00000000 /* EMC_DLL_XFORM_ADDR5 */
0x00000000 /* EMC_DLL_XFORM_QUSE8 */
0x00000000 /* EMC_DLL_XFORM_QUSE9 */
0x00000000 /* EMC_DLL_XFORM_QUSE10 */
0x00000000 /* EMC_DLL_XFORM_QUSE11 */
0x00000000 /* EMC_DLL_XFORM_QUSE12 */
0x00000000 /* EMC_DLL_XFORM_QUSE13 */
0x00000000 /* EMC_DLL_XFORM_QUSE14 */
0x00000000 /* EMC_DLL_XFORM_QUSE15 */
0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
0x000fc000 /* EMC_DLL_XFORM_DQ0 */
0x000fc000 /* EMC_DLL_XFORM_DQ1 */
0x000fc000 /* EMC_DLL_XFORM_DQ2 */
0x000fc000 /* EMC_DLL_XFORM_DQ3 */
0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
0x10000280 /* EMC_XM2CMDPADCTRL */
0x00000000 /* EMC_XM2CMDPADCTRL4 */
0x00111111 /* EMC_XM2CMDPADCTRL5 */
0x00000000 /* EMC_XM2DQPADCTRL2 */
0x00000000 /* EMC_XM2DQPADCTRL3 */
0x77ffc081 /* EMC_XM2CLKPADCTRL */
0x00000e0e /* EMC_XM2CLKPADCTRL2 */
0x81f1f108 /* EMC_XM2COMPPADCTRL */
0x07070004 /* EMC_XM2VTTGENPADCTRL */
0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
0x51451400 /* EMC_XM2DQSPADCTRL3 */
0x00514514 /* EMC_XM2DQSPADCTRL4 */
0x00514514 /* EMC_XM2DQSPADCTRL5 */
0x51451400 /* EMC_XM2DQSPADCTRL6 */
0x0000003f /* EMC_DSR_VTTGEN_DRV */
0x00000007 /* EMC_TXDSRVTTGEN */
0x00000000 /* EMC_FBIO_SPARE */
0x00000042 /* EMC_ZCAL_WAIT_CNT */
0x000e000e /* EMC_MRS_WAIT_CNT2 */
0x00000000 /* EMC_CTT */
0x00000003 /* EMC_CTT_DURATION */
0x0000f2f3 /* EMC_CFG_PIPE */
0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */
0x0000000a /* EMC_QPOP */
>;
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml
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# SPDX-License-Identifier: (GPL-2.0)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra124 SoC Memory Controller
maintainers:
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
description: |
Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
These are interleaved to provide high performance with the load shared across
two memory channels. The Tegra124 Memory Controller handles memory requests
from internal clients and arbitrates among them to allocate memory bandwidth
for DDR3L and LPDDR3 SDRAMs.
properties:
compatible:
enum:
- nvidia,tegra114-mc
- nvidia,tegra124-mc
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: mc
interrupts:
maxItems: 1
"#reset-cells":
const: 1
"#iommu-cells":
const: 1
"#interconnect-cells":
const: 1
patternProperties:
"^emc-timings-[0-9]+$":
type: object
properties:
nvidia,ram-code:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Value of RAM_CODE this timing set is used for.
patternProperties:
"^timing-[0-9]+$":
type: object
properties:
clock-frequency:
description:
Memory clock rate in Hz.
minimum: 1000000
maximum: 1066000000
nvidia,emem-configuration:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
Values to be written to the EMEM register block. See section
"20.11.1 MC Registers" in the Tegea114 TRM or
"15.6.1 MC Registers" in the Tegra124 TRM.
minItems: 18
maxItems: 19
required:
- clock-frequency
- nvidia,emem-configuration
additionalProperties: false
required:
- nvidia,ram-code
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- "#reset-cells"
- "#iommu-cells"
- "#interconnect-cells"
additionalProperties: false
examples:
- |
memory-controller@70019000 {
compatible = "nvidia,tegra124-mc";
reg = <0x70019000 0x1000>;
clocks = <&tegra_car 32>;
clock-names = "mc";
interrupts = <0 77 4>;
#iommu-cells = <1>;
#reset-cells = <1>;
#interconnect-cells = <1>;
emc-timings-3 {
nvidia,ram-code = <3>;
timing-12750000 {
clock-frequency = <12750000>;
nvidia,emem-configuration = <
0x40040001 /* MC_EMEM_ARB_CFG */
0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
0x00000001 /* MC_EMEM_ARB_TIMING_RP */
0x00000002 /* MC_EMEM_ARB_TIMING_RC */
0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
0x06030203 /* MC_EMEM_ARB_DA_TURNS */
0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
0x77e30303 /* MC_EMEM_ARB_MISC0 */
0x70000f03 /* MC_EMEM_ARB_MISC1 */
0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
>;
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra186 (and later) SoC Memory Controller
maintainers:
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
description: |
The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC
handles memory requests for 40-bit virtual addresses from internal clients
and arbitrates among them to allocate memory bandwidth.
Up to 15 GiB of physical memory can be supported. Security features such as
encryption of traffic to and from DRAM via general security apertures are
available for video and other secure applications, as well as DRAM ECC for
automotive safety applications (single bit error correction and double bit
error detection).
properties:
$nodename:
pattern: "^memory-controller@[0-9a-f]+$"
compatible:
items:
- enum:
- nvidia,tegra186-mc
- nvidia,tegra194-mc
- nvidia,tegra234-mc
- nvidia,tegra238-mc
- nvidia,tegra264-mc
reg:
minItems: 6
maxItems: 18
reg-names:
minItems: 6
maxItems: 18
interrupts:
minItems: 1
maxItems: 8
interrupt-names:
minItems: 1
maxItems: 8
"#address-cells":
const: 2
"#size-cells":
const: 2
ranges: true
dma-ranges: true
"#interconnect-cells":
const: 1
patternProperties:
"^external-memory-controller@[0-9a-f]+$":
description:
The bulk of the work involved in controlling the external memory
controller on NVIDIA Tegra186 and later is performed on the BPMP. This
coprocessor exposes the EMC clock that is used to set the frequency at
which the external memory is clocked and a remote procedure call that
can be used to obtain the set of available frequencies.
type: object
properties:
compatible:
items:
- enum:
- nvidia,tegra186-emc
- nvidia,tegra194-emc
- nvidia,tegra234-emc
- nvidia,tegra264-emc
reg:
minItems: 1
maxItems: 2
interrupts:
items:
- description: EMC general interrupt
clocks:
items:
- description: external memory clock
- description: data backbone clock
minItems: 1
clock-names:
items:
- const: emc
- const: dbb
minItems: 1
"#interconnect-cells":
const: 0
nvidia,bpmp:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle of the node representing the BPMP
allOf:
- if:
properties:
compatible:
const: nvidia,tegra186-emc
then:
properties:
reg:
maxItems: 1
clocks:
maxItems: 1
- if:
properties:
compatible:
const: nvidia,tegra194-emc
then:
properties:
reg:
minItems: 2
clocks:
maxItems: 1
- if:
properties:
compatible:
const: nvidia,tegra234-emc
then:
properties:
reg:
minItems: 2
clocks:
maxItems: 1
- if:
properties:
compatible:
const: nvidia,tegra264-emc
then:
properties:
reg:
minItems: 2
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- "#interconnect-cells"
- nvidia,bpmp
allOf:
- if:
properties:
compatible:
const: nvidia,tegra186-mc
then:
properties:
reg:
maxItems: 6
description: 5 memory controller channels and 1 for stream-id registers
reg-names:
items:
- const: sid
- const: broadcast
- const: ch0
- const: ch1
- const: ch2
- const: ch3
interrupts:
items:
- description: MC general interrupt
interrupt-names: false
- if:
properties:
compatible:
const: nvidia,tegra194-mc
then:
properties:
reg:
minItems: 18
description: 17 memory controller channels and 1 for stream-id registers
reg-names:
items:
- const: sid
- const: broadcast
- const: ch0
- const: ch1
- const: ch2
- const: ch3
- const: ch4
- const: ch5
- const: ch6
- const: ch7
- const: ch8
- const: ch9
- const: ch10
- const: ch11
- const: ch12
- const: ch13
- const: ch14
- const: ch15
interrupts:
items:
- description: MC general interrupt
interrupt-names: false
- if:
properties:
compatible:
const: nvidia,tegra234-mc
then:
properties:
reg:
minItems: 18
description: 17 memory controller channels and 1 for stream-id registers
reg-names:
items:
- const: sid
- const: broadcast
- const: ch0
- const: ch1
- const: ch2
- const: ch3
- const: ch4
- const: ch5
- const: ch6
- const: ch7
- const: ch8
- const: ch9
- const: ch10
- const: ch11
- const: ch12
- const: ch13
- const: ch14
- const: ch15
interrupts:
items:
- description: MC general interrupt
interrupt-names: false
- if:
properties:
compatible:
const: nvidia,tegra238-mc
then:
properties:
reg:
minItems: 10
maxItems: 10
description: 9 memory controller channels and 1 for stream-id registers
reg-names:
items:
- const: sid
- const: broadcast
- const: ch0
- const: ch1
- const: ch2
- const: ch3
- const: ch4
- const: ch5
- const: ch6
- const: ch7
interrupts:
items:
- description: MC general interrupt
interrupt-names: false
- if:
properties:
compatible:
const: nvidia,tegra264-mc
then:
properties:
reg:
minItems: 17
maxItems: 17
description: 17 memory controller channels
reg-names:
items:
- const: broadcast
- const: ch0
- const: ch1
- const: ch2
- const: ch3
- const: ch4
- const: ch5
- const: ch6
- const: ch7
- const: ch8
- const: ch9
- const: ch10
- const: ch11
- const: ch12
- const: ch13
- const: ch14
- const: ch15
interrupts:
minItems: 8
maxItems: 8
description: One interrupt line for each MC component
interrupt-names:
items:
- const: mcf
- const: hub1
- const: hub2
- const: hub3
- const: hub4
- const: hub5
- const: sbs
- const: channel
additionalProperties: false
required:
- compatible
- reg
- reg-names
- interrupts
- "#address-cells"
- "#size-cells"
examples:
- |
#include <dt-bindings/clock/tegra186-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
bus {
#address-cells = <2>;
#size-cells = <2>;
memory-controller@2c00000 {
compatible = "nvidia,tegra186-mc";
reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
<0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */
<0x0 0x02c20000 0x0 0x10000>, /* MC0 */
<0x0 0x02c30000 0x0 0x10000>, /* MC1 */
<0x0 0x02c40000 0x0 0x10000>, /* MC2 */
<0x0 0x02c50000 0x0 0x10000>; /* MC3 */
reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
/*
* Memory clients have access to all 40 bits that the memory
* controller can address.
*/
dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
external-memory-controller@2c60000 {
compatible = "nvidia,tegra186-emc";
reg = <0x0 0x02c60000 0x0 0x50000>;
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_EMC>;
clock-names = "emc";
#interconnect-cells = <0>;
nvidia,bpmp = <&bpmp>;
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra20 SoC External Memory Controller
maintainers:
- Dmitry Osipenko <digetx@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
description: |
The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
service the request stream sent from Memory Controller. The EMC also has
various performance-affecting settings beyond the obvious SDRAM configuration
parameters and initialization settings. Tegra20 EMC supports multiple JEDEC
standard protocols: DDR1, LPDDR2 and DDR2.
properties:
compatible:
const: nvidia,tegra20-emc
reg:
maxItems: 1
clocks:
maxItems: 1
interrupts:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 0
"#interconnect-cells":
const: 0
nvidia,memory-controller:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle of the Memory Controller node.
power-domains:
maxItems: 1
description:
Phandle of the SoC "core" power domain.
operating-points-v2:
description:
Should contain freqs and voltages and opp-supported-hw property, which
is a bitfield indicating SoC process ID mask.
nvidia,use-ram-code:
type: boolean
description:
If present, the emc-tables@ sub-nodes will be addressed.
$defs:
emc-table:
type: object
properties:
compatible:
const: nvidia,tegra20-emc-table
clock-frequency:
description:
Memory clock rate in kHz.
minimum: 1000
maximum: 900000
reg:
maxItems: 1
description:
Either an opaque enumerator to tell different tables apart, or
the valid frequency for which the table should be used (in kHz).
nvidia,emc-registers:
description:
EMC timing characterization data. These are the registers
(see section "15.4.1 EMC Registers" in the TRM) whose values
need to be specified, according to the board documentation.
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- description: EMC_RC
- description: EMC_RFC
- description: EMC_RAS
- description: EMC_RP
- description: EMC_R2W
- description: EMC_W2R
- description: EMC_R2P
- description: EMC_W2P
- description: EMC_RD_RCD
- description: EMC_WR_RCD
- description: EMC_RRD
- description: EMC_REXT
- description: EMC_WDV
- description: EMC_QUSE
- description: EMC_QRST
- description: EMC_QSAFE
- description: EMC_RDV
- description: EMC_REFRESH
- description: EMC_BURST_REFRESH_NUM
- description: EMC_PDEX2WR
- description: EMC_PDEX2RD
- description: EMC_PCHG2PDEN
- description: EMC_ACT2PDEN
- description: EMC_AR2PDEN
- description: EMC_RW2PDEN
- description: EMC_TXSR
- description: EMC_TCKE
- description: EMC_TFAW
- description: EMC_TRPAB
- description: EMC_TCLKSTABLE
- description: EMC_TCLKSTOP
- description: EMC_TREFBW
- description: EMC_QUSE_EXTRA
- description: EMC_FBIO_CFG6
- description: EMC_ODT_WRITE
- description: EMC_ODT_READ
- description: EMC_FBIO_CFG5
- description: EMC_CFG_DIG_DLL
- description: EMC_DLL_XFORM_DQS
- description: EMC_DLL_XFORM_QUSE
- description: EMC_ZCAL_REF_CNT
- description: EMC_ZCAL_WAIT_CNT
- description: EMC_AUTO_CAL_INTERVAL
- description: EMC_CFG_CLKTRIM_0
- description: EMC_CFG_CLKTRIM_1
- description: EMC_CFG_CLKTRIM_2
required:
- clock-frequency
- compatible
- reg
- nvidia,emc-registers
additionalProperties: false
patternProperties:
"^emc-table@[0-9]+$":
$ref: "#/$defs/emc-table"
"^emc-tables@[a-f0-9-]+$":
type: object
properties:
reg:
maxItems: 1
description:
An opaque enumerator to tell different tables apart.
nvidia,ram-code:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Value of RAM_CODE this timing set is used for.
"#address-cells":
const: 1
"#size-cells":
const: 0
lpddr2:
$ref: ddr/jedec,lpddr2.yaml#
type: object
patternProperties:
"^emc-table@[0-9]+$":
$ref: "#/$defs/emc-table"
oneOf:
- required:
- nvidia,ram-code
- required:
- lpddr2
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- nvidia,memory-controller
- "#interconnect-cells"
- operating-points-v2
additionalProperties: false
examples:
- |
external-memory-controller@7000f400 {
compatible = "nvidia,tegra20-emc";
reg = <0x7000f400 0x400>;
interrupts = <0 78 4>;
clocks = <&clock_controller 57>;
nvidia,memory-controller = <&mc>;
operating-points-v2 = <&dvfs_opp_table>;
power-domains = <&domain>;
#interconnect-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
nvidia,use-ram-code;
emc-tables@0 {
nvidia,ram-code = <0>;
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
emc-table@333000 {
reg = <333000>;
compatible = "nvidia,tegra20-emc-table";
clock-frequency = <333000>;
nvidia,emc-registers = <0x00000018 0x00000033
0x00000012 0x00000004 0x00000004 0x00000005
0x00000003 0x0000000c 0x00000006 0x00000006
0x00000003 0x00000001 0x00000004 0x00000005
0x00000004 0x00000009 0x0000000d 0x00000bff
0x00000000 0x00000003 0x00000003 0x00000006
0x00000006 0x00000001 0x00000011 0x000000c8
0x00000003 0x0000000e 0x00000007 0x00000008
0x00000002 0x00000000 0x00000000 0x00000002
0x00000000 0x00000000 0x00000083 0xf0440303
0x007fe010 0x00001414 0x00000000 0x00000000
0x00000000 0x00000000 0x00000000 0x00000000>;
};
};
emc-tables@1 {
reg = <1>;
lpddr2 {
compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4";
revision-id1 = <1>;
density = <2048>;
io-width = <16>;
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-mc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra20 SoC Memory Controller
maintainers:
- Dmitry Osipenko <digetx@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
description: |
The Tegra20 Memory Controller merges request streams from various client
interfaces into request stream(s) for the various memory target devices,
and returns response data to the various clients. The Memory Controller
has a configurable arbitration algorithm to allow the user to fine-tune
performance among the various clients.
Tegra20 Memory Controller includes the GART (Graphics Address Relocation
Table) which allows Memory Controller to provide a linear view of a
fragmented memory pages.
properties:
compatible:
const: nvidia,tegra20-mc-gart
reg:
items:
- description: controller registers
- description: GART registers
clocks:
maxItems: 1
clock-names:
items:
- const: mc
interrupts:
maxItems: 1
"#reset-cells":
const: 1
"#iommu-cells":
const: 0
"#interconnect-cells":
const: 1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- "#reset-cells"
- "#iommu-cells"
- "#interconnect-cells"
additionalProperties: false
examples:
- |
memory-controller@7000f000 {
compatible = "nvidia,tegra20-mc-gart";
reg = <0x7000f000 0x400>, /* Controller registers */
<0x58000000 0x02000000>; /* GART aperture */
clocks = <&clock_controller 32>;
clock-names = "mc";
interrupts = <0 77 4>;
#iommu-cells = <0>;
#reset-cells = <1>;
#interconnect-cells = <1>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-emc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra210 SoC External Memory Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
description: |
The EMC interfaces with the off-chip SDRAM to service the request stream
sent from the memory controller.
properties:
compatible:
const: nvidia,tegra210-emc
reg:
maxItems: 3
clocks:
items:
- description: external memory clock
clock-names:
items:
- const: emc
interrupts:
items:
- description: EMC general interrupt
"#interconnect-cells":
const: 0
memory-region:
maxItems: 1
description:
phandle to a reserved memory region describing the table of EMC
frequencies trained by the firmware
nvidia,memory-controller:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle of the memory controller node
operating-points-v2:
description:
Should contain freqs and voltages and opp-supported-hw property, which
is a bitfield indicating SoC speedo ID mask.
allOf:
- $ref: /schemas/thermal/thermal-cooling-devices.yaml
required:
- compatible
- reg
- clocks
- clock-names
- nvidia,memory-controller
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
emc_table: emc-table@83400000 {
compatible = "nvidia,tegra210-emc-table";
reg = <0x83400000 0x10000>;
};
};
external-memory-controller@7001b000 {
compatible = "nvidia,tegra210-emc";
reg = <0x7001b000 0x1000>,
<0x7001e000 0x1000>,
<0x7001f000 0x1000>;
clocks = <&tegra_car TEGRA210_CLK_EMC>;
clock-names = "emc";
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
memory-region = <&emc_table>;
nvidia,memory-controller = <&mc>;
operating-points-v2 = <&dvfs_opp_table>;
#interconnect-cells = <0>;
#cooling-cells = <2>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-mc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-mc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra210 SoC Memory Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
description: |
The NVIDIA Tegra210 SoC features a 64 bit memory controller that is split
into two 32 bit channels to support LPDDR3 and LPDDR4 with x16 subpartitions.
The MC handles memory requests for 34-bit virtual addresses from internal
clients and arbitrates among them to allocate memory bandwidth.
Up to 8 GiB of physical memory can be supported. Security features such as
encryption of traffic to and from DRAM via general security apertures are
available for video and other secure applications.
properties:
$nodename:
pattern: "^memory-controller@[0-9a-f]+$"
compatible:
items:
- enum:
- nvidia,tegra210-mc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: module clock
clock-names:
items:
- const: mc
"#iommu-cells":
const: 1
"#reset-cells":
const: 1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- "#iommu-cells"
- "#reset-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
memory-controller@70019000 {
compatible = "nvidia,tegra210-mc";
reg = <0x70019000 0x1000>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_MC>;
clock-names = "mc";
#iommu-cells = <1>;
#reset-cells = <1>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml
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# SPDX-License-Identifier: (GPL-2.0)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra30 SoC External Memory Controller
maintainers:
- Dmitry Osipenko <digetx@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
description: |
The EMC interfaces with the off-chip SDRAM to service the request stream
sent from Memory Controller. The EMC also has various performance-affecting
settings beyond the obvious SDRAM configuration parameters and initialization
settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
LPDDR3, and DDR3.
properties:
compatible:
const: nvidia,tegra30-emc
reg:
maxItems: 1
clocks:
maxItems: 1
interrupts:
maxItems: 1
"#interconnect-cells":
const: 0
nvidia,memory-controller:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle of the Memory Controller node.
power-domains:
maxItems: 1
description:
Phandle of the SoC "core" power domain.
operating-points-v2:
description:
Should contain freqs and voltages and opp-supported-hw property, which
is a bitfield indicating SoC speedo ID mask.
patternProperties:
"^emc-timings-[0-9]+$":
type: object
properties:
nvidia,ram-code:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Value of RAM_CODE this timing set is used for.
patternProperties:
"^timing-[0-9]+$":
type: object
properties:
clock-frequency:
description:
Memory clock rate in Hz.
minimum: 1000000
maximum: 900000000
nvidia,emc-auto-cal-interval:
description:
Pad calibration interval in microseconds.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 2097151
nvidia,emc-mode-1:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Mode Register 1.
nvidia,emc-mode-2:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Mode Register 2.
nvidia,emc-mode-reset:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Mode Register 0.
nvidia,emc-zcal-cnt-long:
description:
Number of EMC clocks to wait before issuing any commands after
sending ZCAL_MRW_CMD.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 1023
nvidia,emc-cfg-dyn-self-ref:
type: boolean
description:
Dynamic self-refresh enabled.
nvidia,emc-cfg-periodic-qrst:
type: boolean
description:
FBIO "read" FIFO periodic resetting enabled.
nvidia,emc-configuration:
description:
EMC timing characterization data. These are the registers
(see section "18.13.2 EMC Registers" in the TRM) whose values
need to be specified, according to the board documentation.
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- description: EMC_RC
- description: EMC_RFC
- description: EMC_RAS
- description: EMC_RP
- description: EMC_R2W
- description: EMC_W2R
- description: EMC_R2P
- description: EMC_W2P
- description: EMC_RD_RCD
- description: EMC_WR_RCD
- description: EMC_RRD
- description: EMC_REXT
- description: EMC_WEXT
- description: EMC_WDV
- description: EMC_QUSE
- description: EMC_QRST
- description: EMC_QSAFE
- description: EMC_RDV
- description: EMC_REFRESH
- description: EMC_BURST_REFRESH_NUM
- description: EMC_PRE_REFRESH_REQ_CNT
- description: EMC_PDEX2WR
- description: EMC_PDEX2RD
- description: EMC_PCHG2PDEN
- description: EMC_ACT2PDEN
- description: EMC_AR2PDEN
- description: EMC_RW2PDEN
- description: EMC_TXSR
- description: EMC_TXSRDLL
- description: EMC_TCKE
- description: EMC_TFAW
- description: EMC_TRPAB
- description: EMC_TCLKSTABLE
- description: EMC_TCLKSTOP
- description: EMC_TREFBW
- description: EMC_QUSE_EXTRA
- description: EMC_FBIO_CFG6
- description: EMC_ODT_WRITE
- description: EMC_ODT_READ
- description: EMC_FBIO_CFG5
- description: EMC_CFG_DIG_DLL
- description: EMC_CFG_DIG_DLL_PERIOD
- description: EMC_DLL_XFORM_DQS0
- description: EMC_DLL_XFORM_DQS1
- description: EMC_DLL_XFORM_DQS2
- description: EMC_DLL_XFORM_DQS3
- description: EMC_DLL_XFORM_DQS4
- description: EMC_DLL_XFORM_DQS5
- description: EMC_DLL_XFORM_DQS6
- description: EMC_DLL_XFORM_DQS7
- description: EMC_DLL_XFORM_QUSE0
- description: EMC_DLL_XFORM_QUSE1
- description: EMC_DLL_XFORM_QUSE2
- description: EMC_DLL_XFORM_QUSE3
- description: EMC_DLL_XFORM_QUSE4
- description: EMC_DLL_XFORM_QUSE5
- description: EMC_DLL_XFORM_QUSE6
- description: EMC_DLL_XFORM_QUSE7
- description: EMC_DLI_TRIM_TXDQS0
- description: EMC_DLI_TRIM_TXDQS1
- description: EMC_DLI_TRIM_TXDQS2
- description: EMC_DLI_TRIM_TXDQS3
- description: EMC_DLI_TRIM_TXDQS4
- description: EMC_DLI_TRIM_TXDQS5
- description: EMC_DLI_TRIM_TXDQS6
- description: EMC_DLI_TRIM_TXDQS7
- description: EMC_DLL_XFORM_DQ0
- description: EMC_DLL_XFORM_DQ1
- description: EMC_DLL_XFORM_DQ2
- description: EMC_DLL_XFORM_DQ3
- description: EMC_XM2CMDPADCTRL
- description: EMC_XM2DQSPADCTRL2
- description: EMC_XM2DQPADCTRL2
- description: EMC_XM2CLKPADCTRL
- description: EMC_XM2COMPPADCTRL
- description: EMC_XM2VTTGENPADCTRL
- description: EMC_XM2VTTGENPADCTRL2
- description: EMC_XM2QUSEPADCTRL
- description: EMC_XM2DQSPADCTRL3
- description: EMC_CTT_TERM_CTRL
- description: EMC_ZCAL_INTERVAL
- description: EMC_ZCAL_WAIT_CNT
- description: EMC_MRS_WAIT_CNT
- description: EMC_AUTO_CAL_CONFIG
- description: EMC_CTT
- description: EMC_CTT_DURATION
- description: EMC_DYN_SELF_REF_CONTROL
- description: EMC_FBIO_SPARE
- description: EMC_CFG_RSV
required:
- clock-frequency
- nvidia,emc-auto-cal-interval
- nvidia,emc-mode-1
- nvidia,emc-mode-2
- nvidia,emc-mode-reset
- nvidia,emc-zcal-cnt-long
- nvidia,emc-configuration
additionalProperties: false
required:
- nvidia,ram-code
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- nvidia,memory-controller
- "#interconnect-cells"
- operating-points-v2
additionalProperties: false
examples:
- |
external-memory-controller@7000f400 {
compatible = "nvidia,tegra30-emc";
reg = <0x7000f400 0x400>;
interrupts = <0 78 4>;
clocks = <&tegra_car 57>;
nvidia,memory-controller = <&mc>;
operating-points-v2 = <&dvfs_opp_table>;
power-domains = <&domain>;
#interconnect-cells = <0>;
emc-timings-1 {
nvidia,ram-code = <1>;
timing-667000000 {
clock-frequency = <667000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x80100002>;
nvidia,emc-mode-2 = <0x80200018>;
nvidia,emc-mode-reset = <0x80000b71>;
nvidia,emc-zcal-cnt-long = <0x00000040>;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = <
0x00000020 /* EMC_RC */
0x0000006a /* EMC_RFC */
0x00000017 /* EMC_RAS */
0x00000007 /* EMC_RP */
0x00000005 /* EMC_R2W */
0x0000000c /* EMC_W2R */
0x00000003 /* EMC_R2P */
0x00000011 /* EMC_W2P */
0x00000007 /* EMC_RD_RCD */
0x00000007 /* EMC_WR_RCD */
0x00000002 /* EMC_RRD */
0x00000001 /* EMC_REXT */
0x00000000 /* EMC_WEXT */
0x00000007 /* EMC_WDV */
0x0000000a /* EMC_QUSE */
0x00000009 /* EMC_QRST */
0x0000000b /* EMC_QSAFE */
0x00000011 /* EMC_RDV */
0x00001412 /* EMC_REFRESH */
0x00000000 /* EMC_BURST_REFRESH_NUM */
0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */
0x00000002 /* EMC_PDEX2WR */
0x0000000e /* EMC_PDEX2RD */
0x00000001 /* EMC_PCHG2PDEN */
0x00000000 /* EMC_ACT2PDEN */
0x0000000c /* EMC_AR2PDEN */
0x00000016 /* EMC_RW2PDEN */
0x00000072 /* EMC_TXSR */
0x00000200 /* EMC_TXSRDLL */
0x00000005 /* EMC_TCKE */
0x00000015 /* EMC_TFAW */
0x00000000 /* EMC_TRPAB */
0x00000006 /* EMC_TCLKSTABLE */
0x00000007 /* EMC_TCLKSTOP */
0x00001453 /* EMC_TREFBW */
0x0000000b /* EMC_QUSE_EXTRA */
0x00000006 /* EMC_FBIO_CFG6 */
0x00000000 /* EMC_ODT_WRITE */
0x00000000 /* EMC_ODT_READ */
0x00005088 /* EMC_FBIO_CFG5 */
0xf00b0191 /* EMC_CFG_DIG_DLL */
0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
0x00000008 /* EMC_DLL_XFORM_DQS0 */
0x00000008 /* EMC_DLL_XFORM_DQS1 */
0x00000008 /* EMC_DLL_XFORM_DQS2 */
0x00000008 /* EMC_DLL_XFORM_DQS3 */
0x0000000a /* EMC_DLL_XFORM_DQS4 */
0x0000000a /* EMC_DLL_XFORM_DQS5 */
0x0000000a /* EMC_DLL_XFORM_DQS6 */
0x0000000a /* EMC_DLL_XFORM_DQS7 */
0x00018000 /* EMC_DLL_XFORM_QUSE0 */
0x00018000 /* EMC_DLL_XFORM_QUSE1 */
0x00018000 /* EMC_DLL_XFORM_QUSE2 */
0x00018000 /* EMC_DLL_XFORM_QUSE3 */
0x00000000 /* EMC_DLL_XFORM_QUSE4 */
0x00000000 /* EMC_DLL_XFORM_QUSE5 */
0x00000000 /* EMC_DLL_XFORM_QUSE6 */
0x00000000 /* EMC_DLL_XFORM_QUSE7 */
0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
0x0000000a /* EMC_DLL_XFORM_DQ0 */
0x0000000a /* EMC_DLL_XFORM_DQ1 */
0x0000000a /* EMC_DLL_XFORM_DQ2 */
0x0000000a /* EMC_DLL_XFORM_DQ3 */
0x000002a0 /* EMC_XM2CMDPADCTRL */
0x0800013d /* EMC_XM2DQSPADCTRL2 */
0x22220000 /* EMC_XM2DQPADCTRL2 */
0x77fff884 /* EMC_XM2CLKPADCTRL */
0x01f1f501 /* EMC_XM2COMPPADCTRL */
0x07077404 /* EMC_XM2VTTGENPADCTRL */
0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
0x080001e8 /* EMC_XM2QUSEPADCTRL */
0x0c000021 /* EMC_XM2DQSPADCTRL3 */
0x00000802 /* EMC_CTT_TERM_CTRL */
0x00020000 /* EMC_ZCAL_INTERVAL */
0x00000100 /* EMC_ZCAL_WAIT_CNT */
0x0155000c /* EMC_MRS_WAIT_CNT */
0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
0x00000000 /* EMC_CTT */
0x00000000 /* EMC_CTT_DURATION */
0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */
0xe8000000 /* EMC_FBIO_SPARE */
0xff00ff49 /* EMC_CFG_RSV */
>;
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml
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# SPDX-License-Identifier: (GPL-2.0)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra30 SoC Memory Controller
maintainers:
- Dmitry Osipenko <digetx@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
description: |
Tegra30 Memory Controller architecturally consists of the following parts:
Arbitration Domains, which can handle a single request or response per
clock from a group of clients. Typically, a system has a single Arbitration
Domain, but an implementation may divide the client space into multiple
Arbitration Domains to increase the effective system bandwidth.
Protocol Arbiter, which manage a related pool of memory devices. A system
may have a single Protocol Arbiter or multiple Protocol Arbiters.
Memory Crossbar, which routes request and responses between Arbitration
Domains and Protocol Arbiters. In the simplest version of the system, the
Memory Crossbar is just a pass through between a single Arbitration Domain
and a single Protocol Arbiter.
Global Resources, which include things like configuration registers which
are shared across the Memory Subsystem.
The Tegra30 Memory Controller handles memory requests from internal clients
and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR2
SDRAMs.
properties:
compatible:
const: nvidia,tegra30-mc
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: mc
interrupts:
maxItems: 1
"#reset-cells":
const: 1
"#iommu-cells":
const: 1
"#interconnect-cells":
const: 1
patternProperties:
"^emc-timings-[0-9]+$":
type: object
properties:
nvidia,ram-code:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Value of RAM_CODE this timing set is used for.
patternProperties:
"^timing-[0-9]+$":
type: object
properties:
clock-frequency:
description:
Memory clock rate in Hz.
minimum: 1000000
maximum: 900000000
nvidia,emem-configuration:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: |
Values to be written to the EMEM register block. See section
"18.13.1 MC Registers" in the TRM.
items:
- description: MC_EMEM_ARB_CFG
- description: MC_EMEM_ARB_OUTSTANDING_REQ
- description: MC_EMEM_ARB_TIMING_RCD
- description: MC_EMEM_ARB_TIMING_RP
- description: MC_EMEM_ARB_TIMING_RC
- description: MC_EMEM_ARB_TIMING_RAS
- description: MC_EMEM_ARB_TIMING_FAW
- description: MC_EMEM_ARB_TIMING_RRD
- description: MC_EMEM_ARB_TIMING_RAP2PRE
- description: MC_EMEM_ARB_TIMING_WAP2PRE
- description: MC_EMEM_ARB_TIMING_R2R
- description: MC_EMEM_ARB_TIMING_W2W
- description: MC_EMEM_ARB_TIMING_R2W
- description: MC_EMEM_ARB_TIMING_W2R
- description: MC_EMEM_ARB_DA_TURNS
- description: MC_EMEM_ARB_DA_COVERS
- description: MC_EMEM_ARB_MISC0
- description: MC_EMEM_ARB_RING1_THROTTLE
required:
- clock-frequency
- nvidia,emem-configuration
additionalProperties: false
required:
- nvidia,ram-code
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- "#reset-cells"
- "#iommu-cells"
- "#interconnect-cells"
additionalProperties: false
examples:
- |
memory-controller@7000f000 {
compatible = "nvidia,tegra30-mc";
reg = <0x7000f000 0x400>;
clocks = <&tegra_car 32>;
clock-names = "mc";
interrupts = <0 77 4>;
#iommu-cells = <1>;
#reset-cells = <1>;
#interconnect-cells = <1>;
emc-timings-1 {
nvidia,ram-code = <1>;
timing-667000000 {
clock-frequency = <667000000>;
nvidia,emem-configuration = <
0x0000000a /* MC_EMEM_ARB_CFG */
0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000003 /* MC_EMEM_ARB_TIMING_RCD */
0x00000004 /* MC_EMEM_ARB_TIMING_RP */
0x00000010 /* MC_EMEM_ARB_TIMING_RC */
0x0000000b /* MC_EMEM_ARB_TIMING_RAS */
0x0000000a /* MC_EMEM_ARB_TIMING_FAW */
0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */
0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
0x08040202 /* MC_EMEM_ARB_DA_TURNS */
0x00130b10 /* MC_EMEM_ARB_DA_COVERS */
0x70ea1f11 /* MC_EMEM_ARB_MISC0 */
0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
>;
};
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/qca,ath79-ddr-controller.yaml
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/qca,ath79-ddr-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
The DDR controller of the AR7xxx and AR9xxx families provides an interface to
flush the FIFO between various devices and the DDR. This is mainly used by
the IRQ controller to flush the FIFO before running the interrupt handler of
such devices.
properties:
compatible:
oneOf:
- items:
- const: qca,ar9132-ddr-controller
- const: qca,ar7240-ddr-controller
- items:
- enum:
- qca,ar7100-ddr-controller
- qca,ar7240-ddr-controller
"#qca,ddr-wb-channel-cells":
description: |
Specifies the number of cells needed to encode the write buffer channel
index.
$ref: /schemas/types.yaml#/definitions/uint32
const: 1
reg:
maxItems: 1
required:
- compatible
- "#qca,ddr-wb-channel-cells"
- reg
additionalProperties: false
examples:
- |
ddr_ctrl: memory-controller@18000000 {
compatible = "qca,ar9132-ddr-controller",
"qca,ar7240-ddr-controller";
reg = <0x18000000 0x100>;
#qca,ddr-wb-channel-cells = <1>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/qcom,ebi2-peripheral-props.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/qcom,ebi2-peripheral-props.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Peripheral Properties for Qualcomm External Bus Interface 2 (EBI2)
maintainers:
- Bjorn Andersson <andersson@kernel.org>
properties:
# SLOW chip selects
qcom,xmem-recovery-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The time the memory continues to drive the data bus after OE
is de-asserted, in order to avoid contention on the data bus.
They are inserted when reading one CS and switching to another
CS or read followed by write on the same CS. Minimum value is
actually 1, so a value of 0 will still yield 1 recovery cycle.
minimum: 0
maximum: 15
qcom,xmem-write-hold-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The extra cycles inserted after every write minimum 1. The
data out is driven from the time WE is asserted until CS is
asserted. With a hold of 1 (value = 0), the CS stays active
for 1 extra cycle, etc.
minimum: 0
maximum: 15
qcom,xmem-write-delta-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The initial latency for write cycles inserted for the first
write to a page or burst memory.
minimum: 0
maximum: 255
qcom,xmem-read-delta-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The initial latency for read cycles inserted for the first
read to a page or burst memory.
minimum: 0
maximum: 255
qcom,xmem-write-wait-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The number of wait cycles for every write access.
minimum: 0
maximum: 15
qcom,xmem-read-wait-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The number of wait cycles for every read access.
minimum: 0
maximum: 15
# FAST chip selects
qcom,xmem-address-hold-enable:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
Holds the address for an extra cycle to meet hold time
requirements with ADV assertion, when set to 1.
enum: [ 0, 1 ]
qcom,xmem-adv-to-oe-recovery-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The number of cycles elapsed before an OE assertion, with
respect to the cycle where ADV (address valid) is asserted.
minimum: 0
maximum: 3
qcom,xmem-read-hold-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The length in cycles of the first segment of a read transfer.
For a single read transfer this will be the time from CS
assertion to OE assertion.
minimum: 0
maximum: 15
additionalProperties: true
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/qcom,ebi2.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/qcom,ebi2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm External Bus Interface 2 (EBI2)
description: |
The EBI2 contains two peripheral blocks: XMEM and LCDC. The XMEM handles any
external memory (such as NAND or other memory-mapped peripherals) whereas
LCDC handles LCD displays.
As it says it connects devices to an external bus interface, meaning address
lines (up to 9 address lines so can only address 1KiB external memory space),
data lines (16 bits), OE (output enable), ADV (address valid, used on some
NOR flash memories), WE (write enable). This on top of 6 different chip selects
(CS0 thru CS5) so that in theory 6 different devices can be connected.
Apparently this bus is clocked at 64MHz. It has dedicated pins on the package
and the bus can only come out on these pins, however if some of the pins are
unused they can be left unconnected or remuxed to be used as GPIO or in some
cases other orthogonal functions as well.
Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
The chip selects have the following memory range assignments. This region of
memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big.
Chip Select Physical address base
CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
The APQ8060 Qualcomm Application Processor User Guide, 80-N7150-14 Rev. A,
August 6, 2012 contains some incomplete documentation of the EBI2.
FIXME: the manual mentions "write precharge cycles" and "precharge cycles".
We have not been able to figure out which bit fields these correspond to
in the hardware, or what valid values exist. The current hypothesis is that
this is something just used on the FAST chip selects and that the SLOW
chip selects are understood fully. There is also a "byte device enable"
flag somewhere for 8bit memories.
FIXME: The chipselects have SLOW and FAST configuration registers. It's a bit
unclear what this means, if they are mutually exclusive or can be used
together, or if some chip selects are hardwired to be FAST and others are SLOW
by design.
The XMEM registers are totally undocumented but could be partially decoded
because the Cypress AN49576 Antioch Westbridge apparently has suspiciously
similar register layout, see: http://www.cypress.com/file/105771/download
maintainers:
- Bjorn Andersson <andersson@kernel.org>
properties:
compatible:
enum:
- qcom,apq8060-ebi2
- qcom,msm8660-ebi2
reg:
items:
- description: EBI2 config region
- description: XMEM config region
reg-names:
items:
- const: ebi2
- const: xmem
ranges: true
clocks:
items:
- description: EBI_2X clock
- description: EBI clock
clock-names:
items:
- const: ebi2x
- const: ebi2
'#address-cells':
const: 2
'#size-cells':
const: 1
required:
- compatible
- reg
- reg-names
- ranges
- clocks
- clock-names
- '#address-cells'
- '#size-cells'
patternProperties:
"^.*@[0-5],[0-9a-f]+$":
type: object
$ref: mc-peripheral-props.yaml#
additionalProperties: true
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-msm8660.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
external-bus@1a100000 {
compatible = "qcom,msm8660-ebi2";
reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
reg-names = "ebi2", "xmem";
ranges = <0 0x0 0x1a800000 0x00800000>,
<1 0x0 0x1b000000 0x00800000>,
<2 0x0 0x1b800000 0x00800000>,
<3 0x0 0x1d000000 0x08000000>,
<4 0x0 0x1c800000 0x00800000>,
<5 0x0 0x1c000000 0x00800000>;
clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
clock-names = "ebi2x", "ebi2";
#address-cells = <2>;
#size-cells = <1>;
ethernet@2,0 {
compatible = "smsc,lan9221", "smsc,lan9115";
reg = <2 0x0 0x100>;
interrupts-extended = <&pm8058_gpio 7 IRQ_TYPE_EDGE_FALLING>,
<&tlmm 29 IRQ_TYPE_EDGE_RISING>;
reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
phy-mode = "mii";
reg-io-width = <2>;
smsc,force-external-phy;
smsc,irq-push-pull;
/* SLOW chipselect config */
qcom,xmem-recovery-cycles = <0>;
qcom,xmem-write-hold-cycles = <3>;
qcom,xmem-write-delta-cycles = <31>;
qcom,xmem-read-delta-cycles = <28>;
qcom,xmem-write-wait-cycles = <9>;
qcom,xmem-read-wait-cycles = <9>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/renesas,dbsc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas DDR Bus Controllers
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
description: |
Renesas SoCs contain one or more memory controllers. These memory
controllers differ from one SoC variant to another, and are called by
different names, e.g. "DDR Bus Controller (DBSC)", "DDR3 Bus State Controller
(DBSC3)", or "SDRAM Bus State Controller (SBSC)").
properties:
compatible:
enum:
- renesas,dbsc-r8a73a4 # R-Mobile APE6
- renesas,dbsc3-r8a7740 # R-Mobile A1
- renesas,sbsc-sh73a0 # SH-Mobile AG5
reg:
maxItems: 1
interrupts:
maxItems: 2
interrupt-names:
items:
- const: sec # secure interrupt
- const: temp # normal (temperature) interrupt
power-domains:
maxItems: 1
required:
- compatible
- reg
- power-domains
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
sbsc1: memory-controller@fe400000 {
compatible = "renesas,sbsc-sh73a0";
reg = <0xfe400000 0x400>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sec", "temp";
power-domains = <&pd_a4bc0>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/renesas,rpc-if.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas Reduced Pin Count Interface (RPC-IF)
maintainers:
- Sergei Shtylyov <sergei.shtylyov@gmail.com>
description: |
Renesas RPC-IF allows a SPI flash or HyperFlash connected to the SoC to
be accessed via the external address space read mode or the manual mode.
The flash chip itself should be represented by a subnode of the RPC-IF node.
The flash interface is selected based on the "compatible" property of this
subnode:
- if it contains "jedec,spi-nor", then SPI is used;
- if it contains "cfi-flash", then HyperFlash is used.
allOf:
- $ref: /schemas/spi/spi-controller.yaml#
properties:
compatible:
oneOf:
- items:
- enum:
- renesas,r8a774a1-rpc-if # RZ/G2M
- renesas,r8a774b1-rpc-if # RZ/G2N
- renesas,r8a774c0-rpc-if # RZ/G2E
- renesas,r8a774e1-rpc-if # RZ/G2H
- renesas,r8a7795-rpc-if # R-Car H3
- renesas,r8a7796-rpc-if # R-Car M3-W
- renesas,r8a77961-rpc-if # R-Car M3-W+
- renesas,r8a77965-rpc-if # R-Car M3-N
- renesas,r8a77970-rpc-if # R-Car V3M
- renesas,r8a77980-rpc-if # R-Car V3H
- renesas,r8a77990-rpc-if # R-Car E3
- renesas,r8a77995-rpc-if # R-Car D3
- renesas,r8a779a0-rpc-if # R-Car V3U
- const: renesas,rcar-gen3-rpc-if # a generic R-Car gen3 or RZ/G2{E,H,M,N} device
- items:
- enum:
- renesas,r8a779g0-rpc-if # R-Car V4H
- renesas,r8a779h0-rpc-if # R-Car V4M
- const: renesas,rcar-gen4-rpc-if # a generic R-Car gen4 device
- items:
- enum:
- renesas,r9a07g043-rpc-if # RZ/G2UL
- renesas,r9a07g044-rpc-if # RZ/G2{L,LC}
- renesas,r9a07g054-rpc-if # RZ/V2L
- const: renesas,rzg2l-rpc-if
reg:
items:
- description: RPC-IF registers
- description: direct mapping read mode area
- description: write buffer area
reg-names:
items:
- const: regs
- const: dirmap
- const: wbuf
clocks:
minItems: 1
maxItems: 2
interrupts:
maxItems: 1
power-domains:
maxItems: 1
resets:
maxItems: 1
patternProperties:
"flash@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
contains:
enum:
- cfi-flash
- jedec,spi-nor
required:
- compatible
- reg
- reg-names
- clocks
- power-domains
- resets
- '#address-cells'
- '#size-cells'
if:
properties:
compatible:
contains:
enum:
- renesas,rzg2l-rpc-if
then:
properties:
clocks:
items:
- description: SPI Multi IO Register access clock (SPI_CLK2)
- description: SPI Multi IO Main clock (SPI_CLK).
else:
properties:
clocks:
maxItems: 1
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/renesas-cpg-mssr.h>
#include <dt-bindings/power/r8a77995-sysc.h>
spi@ee200000 {
compatible = "renesas,r8a77995-rpc-if", "renesas,rcar-gen3-rpc-if";
reg = <0xee200000 0x200>,
<0x08000000 0x4000000>,
<0xee208000 0x100>;
reg-names = "regs", "dirmap", "wbuf";
clocks = <&cpg CPG_MOD 917>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;
#size-cells = <0>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/renesas,rzg3e-xspi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas Expanded Serial Peripheral Interface (xSPI)
maintainers:
- Biju Das <biju.das.jz@bp.renesas.com>
description: |
Renesas xSPI allows a SPI flash connected to the SoC to be accessed via
the memory-mapping or the manual command mode.
The flash chip itself should be represented by a subnode of the XSPI node.
The flash interface is selected based on the "compatible" property of this
subnode:
- "jedec,spi-nor";
allOf:
- $ref: /schemas/spi/spi-controller.yaml#
properties:
compatible:
oneOf:
- const: renesas,r9a09g047-xspi # RZ/G3E
- items:
- enum:
- renesas,r9a09g056-xspi # RZ/V2N
- renesas,r9a09g057-xspi # RZ/V2H(P)
- renesas,r9a09g077-xspi # RZ/T2H
- renesas,r9a09g087-xspi # RZ/N2H
- const: renesas,r9a09g047-xspi
reg:
items:
- description: xSPI registers
- description: direct mapping area
reg-names:
items:
- const: regs
- const: dirmap
interrupts:
items:
- description: Interrupt pulse signal by factors excluding errors
- description: Interrupt pulse signal by error factors
interrupt-names:
items:
- const: pulse
- const: err_pulse
clocks:
oneOf:
- items:
- description: AHB clock
- description: AXI clock
- description: SPI clock
- description: Double speed SPI clock
- items:
- description: AHB clock
- description: SPI clock
clock-names:
oneOf:
- items:
- const: ahb
- const: axi
- const: spi
- const: spix2
- items:
- const: ahb
- const: spi
power-domains:
maxItems: 1
resets:
minItems: 1
items:
- description: Hardware reset
- description: AXI reset
reset-names:
minItems: 1
items:
- const: hresetn
- const: aresetn
renesas,xspi-cs-addr-sys:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
Phandle to the system controller (sys) that allows to configure
xSPI CS0 and CS1 addresses.
patternProperties:
"flash@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
contains:
const: jedec,spi-nor
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-names
- clocks
- clock-names
- power-domains
- resets
- reset-names
- '#address-cells'
- '#size-cells'
if:
properties:
compatible:
contains:
enum:
- renesas,r9a09g077-xspi
- renesas,r9a09g087-xspi
then:
properties:
clocks:
maxItems: 2
clock-names:
maxItems: 2
resets:
maxItems: 1
reset-names:
maxItems: 1
else:
properties:
clocks:
minItems: 4
clock-names:
minItems: 4
resets:
minItems: 2
reset-names:
minItems: 2
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
spi@11030000 {
compatible = "renesas,r9a09g047-xspi";
reg = <0x11030000 0x10000>, <0x20000000 0x10000000>;
reg-names = "regs", "dirmap";
interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "pulse", "err_pulse";
clocks = <&cpg CPG_MOD 0x9f>, <&cpg CPG_MOD 0xa0>,
<&cpg CPG_CORE 9>, <&cpg CPG_MOD 0xa1>;
clock-names = "ahb", "axi", "spi", "spix2";
power-domains = <&cpg>;
resets = <&cpg 0xa3>, <&cpg 0xa4>;
reset-names = "hresetn", "aresetn";
#address-cells = <1>;
#size-cells = <0>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# %YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip rk3399 DMC (Dynamic Memory Controller) device
maintainers:
- Brian Norris <briannorris@chromium.org>
properties:
compatible:
enum:
- rockchip,rk3399-dmc
devfreq-events:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Node to get DDR loading. Refer to
Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml.
clocks:
maxItems: 1
clock-names:
items:
- const: dmc_clk
operating-points-v2: true
center-supply:
description:
DMC regulator supply.
rockchip,pmu:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to the syscon managing the "PMU general register files".
interrupts:
maxItems: 1
description:
The CPU interrupt number. It should be a DCF interrupt. When DDR DVFS
finishes, a DCF interrupt is triggered.
rockchip,ddr3_speed_bin:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
For values, reference include/dt-bindings/clock/rk3399-ddr.h. Selects the
DDR3 cl-trp-trcd type. It must be set according to "Speed Bin" in DDR3
datasheet; DO NOT use a smaller "Speed Bin" than specified for the DDR3
being used.
rockchip,pd_idle:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
Configure the PD_IDLE value. Defines the power-down idle period in which
memories are placed into power-down mode if bus is idle for PD_IDLE DFI
clock cycles.
See also rockchip,pd-idle-ns.
rockchip,sr_idle:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
Configure the SR_IDLE value. Defines the self-refresh idle period in
which memories are placed into self-refresh mode if bus is idle for
SR_IDLE * 1024 DFI clock cycles (DFI clocks freq is half of DRAM clock).
See also rockchip,sr-idle-ns.
default: 0
rockchip,sr_mc_gate_idle:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
Defines the memory self-refresh and controller clock gating idle period.
Memories are placed into self-refresh mode and memory controller clock
arg gating started if bus is idle for sr_mc_gate_idle*1024 DFI clock
cycles.
See also rockchip,sr-mc-gate-idle-ns.
rockchip,srpd_lite_idle:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
Defines the self-refresh power down idle period in which memories are
placed into self-refresh power down mode if bus is idle for
srpd_lite_idle * 1024 DFI clock cycles. This parameter is for LPDDR4
only.
See also rockchip,srpd-lite-idle-ns.
rockchip,standby_idle:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
Defines the standby idle period in which memories are placed into
self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
if bus is idle for standby_idle * DFI clock cycles.
See also rockchip,standby-idle-ns.
rockchip,dram_dll_dis_freq:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
than DRAM_DLL_DISB_FREQ, DDR3 DLL will be bypassed.
Note: if DLL was bypassed, the odt will also stop working.
rockchip,phy_dll_dis_freq:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
is less than DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
Note: PHY DLL and PHY ODT are independent.
rockchip,auto_pd_dis_freq:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
Defines the auto PD disable frequency in MHz.
rockchip,ddr3_odt_dis_freq:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1000000 # In case anyone thought this was MHz.
description:
When the DRAM type is DDR3, this parameter defines the ODT disable
frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
the ODT on the DRAM side and controller side are both disabled.
rockchip,ddr3_drv:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is DDR3, this parameter defines the DRAM side drive
strength in ohms.
default: 40
rockchip,ddr3_odt:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is DDR3, this parameter defines the DRAM side ODT
strength in ohms.
default: 120
rockchip,phy_ddr3_ca_drv:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is DDR3, this parameter defines the phy side CA line
(including command line, address line and clock line) drive strength.
default: 40
rockchip,phy_ddr3_dq_drv:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is DDR3, this parameter defines the PHY side DQ line
(including DQS/DQ/DM line) drive strength.
default: 40
rockchip,phy_ddr3_odt:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is DDR3, this parameter defines the PHY side ODT
strength.
default: 240
rockchip,lpddr3_odt_dis_freq:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1000000 # In case anyone thought this was MHz.
description:
When the DRAM type is LPDDR3, this parameter defines then ODT disable
frequency in Hz. When DDR frequency is less then ddr3_odt_dis_freq, the
ODT on the DRAM side and controller side are both disabled.
rockchip,lpddr3_drv:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR3, this parameter defines the DRAM side drive
strength in ohms.
default: 34
rockchip,lpddr3_odt:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT
strength in ohms.
default: 240
rockchip,phy_lpddr3_ca_drv:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR3, this parameter defines the PHY side CA line
(including command line, address line and clock line) drive strength.
default: 40
rockchip,phy_lpddr3_dq_drv:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line
(including DQS/DQ/DM line) drive strength.
default: 40
rockchip,phy_lpddr3_odt:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When dram type is LPDDR3, this parameter define the phy side odt
strength, default value is 240.
rockchip,lpddr4_odt_dis_freq:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1000000 # In case anyone thought this was MHz.
description:
When the DRAM type is LPDDR4, this parameter defines the ODT disable
frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
the ODT on the DRAM side and controller side are both disabled.
rockchip,lpddr4_drv:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR4, this parameter defines the DRAM side drive
strength in ohms.
default: 60
rockchip,lpddr4_dq_odt:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
DQS/DQ line strength in ohms.
default: 40
rockchip,lpddr4_ca_odt:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
CA line strength in ohms.
default: 40
rockchip,phy_lpddr4_ca_drv:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR4, this parameter defines the PHY side CA line
(including command address line) drive strength.
default: 40
rockchip,phy_lpddr4_ck_cs_drv:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR4, this parameter defines the PHY side clock
line and CS line drive strength.
default: 80
rockchip,phy_lpddr4_dq_drv:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line
(including DQS/DQ/DM line) drive strength.
default: 80
rockchip,phy_lpddr4_odt:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR4, this parameter defines the PHY side ODT
strength.
default: 60
rockchip,pd-idle-ns:
description:
Configure the PD_IDLE value in nanoseconds. Defines the power-down idle
period in which memories are placed into power-down mode if bus is idle
for PD_IDLE nanoseconds.
rockchip,sr-idle-ns:
description:
Configure the SR_IDLE value in nanoseconds. Defines the self-refresh idle
period in which memories are placed into self-refresh mode if bus is idle
for SR_IDLE nanoseconds.
default: 0
rockchip,sr-mc-gate-idle-ns:
description:
Defines the memory self-refresh and controller clock gating idle period in nanoseconds.
Memories are placed into self-refresh mode and memory controller clock
arg gating started if bus is idle for sr_mc_gate_idle nanoseconds.
rockchip,srpd-lite-idle-ns:
description:
Defines the self-refresh power down idle period in which memories are
placed into self-refresh power down mode if bus is idle for
srpd_lite_idle nanoseconds. This parameter is for LPDDR4 only.
rockchip,standby-idle-ns:
description:
Defines the standby idle period in which memories are placed into
self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
if bus is idle for standby_idle nanoseconds.
rockchip,pd-idle-dis-freq-hz:
description:
Defines the power-down idle disable frequency in Hz. When the DDR
frequency is greater than pd-idle-dis-freq, power-down idle is disabled.
See also rockchip,pd-idle-ns.
rockchip,sr-idle-dis-freq-hz:
description:
Defines the self-refresh idle disable frequency in Hz. When the DDR
frequency is greater than sr-idle-dis-freq, self-refresh idle is
disabled. See also rockchip,sr-idle-ns.
rockchip,sr-mc-gate-idle-dis-freq-hz:
description:
Defines the self-refresh and memory-controller clock gating disable
frequency in Hz. When the DDR frequency is greater than
sr-mc-gate-idle-dis-freq, the clock will not be gated when idle. See also
rockchip,sr-mc-gate-idle-ns.
rockchip,srpd-lite-idle-dis-freq-hz:
description:
Defines the self-refresh power down idle disable frequency in Hz. When
the DDR frequency is greater than srpd-lite-idle-dis-freq, memory will
not be placed into self-refresh power down mode when idle. See also
rockchip,srpd-lite-idle-ns.
rockchip,standby-idle-dis-freq-hz:
description:
Defines the standby idle disable frequency in Hz. When the DDR frequency
is greater than standby-idle-dis-freq, standby idle is disabled. See also
rockchip,standby-idle-ns.
required:
- compatible
- devfreq-events
- clocks
- clock-names
- operating-points-v2
- center-supply
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/rk3399-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
memory-controller {
compatible = "rockchip,rk3399-dmc";
devfreq-events = <&dfi>;
rockchip,pmu = <&pmu>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_DDRC>;
clock-names = "dmc_clk";
operating-points-v2 = <&dmc_opp_table>;
center-supply = <&ppvar_centerlogic>;
rockchip,pd-idle-ns = <160>;
rockchip,sr-idle-ns = <10240>;
rockchip,sr-mc-gate-idle-ns = <40960>;
rockchip,srpd-lite-idle-ns = <61440>;
rockchip,standby-idle-ns = <81920>;
rockchip,ddr3_odt_dis_freq = <333000000>;
rockchip,lpddr3_odt_dis_freq = <333000000>;
rockchip,lpddr4_odt_dis_freq = <333000000>;
rockchip,pd-idle-dis-freq-hz = <1000000000>;
rockchip,sr-idle-dis-freq-hz = <1000000000>;
rockchip,sr-mc-gate-idle-dis-freq-hz = <1000000000>;
rockchip,srpd-lite-idle-dis-freq-hz = <0>;
rockchip,standby-idle-dis-freq-hz = <928000000>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/samsung,exynos4210-srom-peripheral-props.yaml
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/samsung,exynos4210-srom-peripheral-props.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Peripheral Properties for Samsung Exynos SoC SROM Controller
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
samsung,srom-page-mode:
description:
If page mode is set, 4 data page mode will be configured,
else normal (1 data) page mode will be set.
type: boolean
samsung,srom-timing:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 6
maxItems: 6
description: |
Array of 6 integers, specifying bank timings in the following order:
Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
Each value is specified in cycles and has the following meaning
and valid range:
Tacp: Page mode access cycle at Page mode (0 - 15)
Tcah: Address holding time after CSn (0 - 15)
Tcoh: Chip selection hold on OEn (0 - 15)
Tacc: Access cycle (0 - 31, the actual time is N + 1)
Tcos: Chip selection set-up before OEn (0 - 15)
Tacs: Address set-up before CSn (0 - 15)
additionalProperties: true
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: |
Samsung Exynos5422 SoC frequency and voltage scaling for Dynamic Memory
Controller device
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
- Lukasz Luba <lukasz.luba@arm.com>
description: |
The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the
DRAM memory chips are connected. The driver is to monitor the controller in
runtime and switch frequency and voltage. To monitor the usage of the
controller in runtime, the driver uses the PPMU (Platform Performance
Monitoring Unit), which is able to measure the current load of the memory.
When 'userspace' governor is used for the driver, an application is able to
switch the DMC and memory frequency.
properties:
compatible:
items:
- const: samsung,exynos5422-dmc
clock-names:
items:
- const: fout_spll
- const: mout_sclk_spll
- const: ff_dout_spll2
- const: fout_bpll
- const: mout_bpll
- const: sclk_bpll
- const: mout_mx_mspll_ccore
- const: mout_mclk_cdrex
clocks:
minItems: 8
maxItems: 8
devfreq-events:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 16
items:
maxItems: 1
description: phandles of the PPMU events used by the controller.
device-handle:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
phandle of the connected DRAM memory device. For more information please
refer to jedec,lpddr3.yaml.
operating-points-v2: true
interrupts:
items:
- description: DMC internal performance event counters in DREX0
- description: DMC internal performance event counters in DREX1
interrupt-names:
items:
- const: drex_0
- const: drex_1
reg:
items:
- description: registers of DREX0
- description: registers of DREX1
samsung,syscon-clk:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
Phandle of the clock register set used by the controller, these registers
are used for enabling a 'pause' feature and are not exposed by clock
framework but they must be used in a safe way. The register offsets are
in the driver code and specyfic for this SoC type.
vdd-supply: true
required:
- compatible
- clock-names
- clocks
- devfreq-events
- device-handle
- reg
- samsung,syscon-clk
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos5420.h>
ppmu_dmc0_0: ppmu@10d00000 {
compatible = "samsung,exynos-ppmu";
reg = <0x10d00000 0x2000>;
clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
clock-names = "ppmu";
events {
ppmu_event_dmc0_0: ppmu-event3-dmc0-0 {
event-name = "ppmu-event3-dmc0_0";
};
};
};
memory-controller@10c20000 {
compatible = "samsung,exynos5422-dmc";
reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
clocks = <&clock CLK_FOUT_SPLL>,
<&clock CLK_MOUT_SCLK_SPLL>,
<&clock CLK_FF_DOUT_SPLL2>,
<&clock CLK_FOUT_BPLL>,
<&clock CLK_MOUT_BPLL>,
<&clock CLK_SCLK_BPLL>,
<&clock CLK_MOUT_MX_MSPLL_CCORE>,
<&clock CLK_MOUT_MCLK_CDREX>;
clock-names = "fout_spll",
"mout_sclk_spll",
"ff_dout_spll2",
"fout_bpll",
"mout_bpll",
"sclk_bpll",
"mout_mx_mspll_ccore",
"mout_mclk_cdrex";
operating-points-v2 = <&dmc_opp_table>;
devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
<&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
device-handle = <&samsung_K3QF2F20DB>;
vdd-supply = <&buck1_reg>;
samsung,syscon-clk = <&clock>;
interrupt-parent = <&combiner>;
interrupts = <16 0>, <16 1>;
interrupt-names = "drex_0", "drex_1";
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/samsung,s5pv210-dmc.yaml
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/samsung,s5pv210-dmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S5Pv210 SoC Dynamic Memory Controller
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
description:
Dynamic Memory Controller interfaces external JEDEC DDR-type SDRAM.
properties:
compatible:
const: samsung,s5pv210-dmc
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
memory-controller@f0000000 {
compatible = "samsung,s5pv210-dmc";
reg = <0xf0000000 0x1000>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synopsys DesignWare Universal Multi-Protocol Memory Controller
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
- Michal Simek <michal.simek@amd.com>
description: |
Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of
working with the memory devices supporting up to (LP)DDR4 protocol. It can
be equipped with SEC/DEC ECC feature if DRAM data bus width is either
16-bits or 32-bits or 64-bits wide.
For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a
controller. It has an optional SEC/DEC ECC support in 64- and 32-bits
bus width configurations.
properties:
compatible:
oneOf:
- deprecated: true
description: Synopsys DW uMCTL2 DDR controller v3.80a
const: snps,ddrc-3.80a
- description: Synopsys DW uMCTL2 DDR controller
const: snps,dw-umctl2-ddrc
- description: Xilinx ZynqMP DDR controller v2.40a
const: xlnx,zynqmp-ddrc-2.40a
interrupts:
description:
DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":"
ECC Corrected Error, ECC Uncorrected Error, ECC Address Protection,
Scrubber-Done signal, DFI Parity/CRC Error. Some platforms may have the
signals merged before they reach the IRQ controller or have some of them
absent in case if the corresponding feature is unavailable/disabled.
minItems: 1
maxItems: 5
interrupt-names:
minItems: 1
maxItems: 5
oneOf:
- description: Common ECC CE/UE/Scrubber/DFI Errors IRQ
items:
- const: ecc
- description: Individual ECC CE/UE/Scrubber/DFI Errors IRQs
items:
enum: [ ecc_ce, ecc_ue, ecc_ap, ecc_sbr, dfi_e ]
reg:
maxItems: 1
clocks:
description:
A standard set of the clock sources contains CSRs bus clock, AXI-ports
reference clock, DDRC core clock, Scrubber standalone clock
(synchronous to the DDRC clock).
minItems: 1
maxItems: 4
clock-names:
minItems: 1
maxItems: 4
items:
enum: [ pclk, aclk, core, sbr ]
resets:
description:
Each clock domain can have separate reset signal.
minItems: 1
maxItems: 4
reset-names:
minItems: 1
maxItems: 4
items:
enum: [ prst, arst, core, sbr ]
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
memory-controller@fd070000 {
compatible = "xlnx,zynqmp-ddrc-2.40a";
reg = <0xfd070000 0x30000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ecc";
};
- |
#include <dt-bindings/interrupt-controller/irq.h>
memory-controller@3d400000 {
compatible = "snps,dw-umctl2-ddrc";
reg = <0x3d400000 0x400000>;
interrupts = <147 IRQ_TYPE_LEVEL_HIGH>, <148 IRQ_TYPE_LEVEL_HIGH>,
<149 IRQ_TYPE_LEVEL_HIGH>, <150 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ecc_ce", "ecc_ue", "ecc_sbr", "dfi_e";
clocks = <&pclk>, <&aclk>, <&core_clk>, <&sbr_clk>;
clock-names = "pclk", "aclk", "core", "sbr";
};
...
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi-props.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Peripheral properties for ST FMC2 Controller
maintainers:
- Christophe Kerello <christophe.kerello@foss.st.com>
- Marek Vasut <marex@denx.de>
properties:
st,fmc2-ebi-cs-transaction-type:
description: |
Select one of the transactions type supported
0: Asynchronous mode 1 SRAM/FRAM.
1: Asynchronous mode 1 PSRAM.
2: Asynchronous mode A SRAM/FRAM.
3: Asynchronous mode A PSRAM.
4: Asynchronous mode 2 NOR.
5: Asynchronous mode B NOR.
6: Asynchronous mode C NOR.
7: Asynchronous mode D NOR.
8: Synchronous read synchronous write PSRAM.
9: Synchronous read asynchronous write PSRAM.
10: Synchronous read synchronous write NOR.
11: Synchronous read asynchronous write NOR.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 11
st,fmc2-ebi-cs-cclk-enable:
description: Continuous clock enable (first bank must be configured
in synchronous mode). The FMC_CLK is generated continuously
during asynchronous and synchronous access. By default, the
FMC_CLK is only generated during synchronous access.
$ref: /schemas/types.yaml#/definitions/flag
st,fmc2-ebi-cs-mux-enable:
description: Address/Data multiplexed on databus (valid only with
NOR and PSRAM transactions type). By default, Address/Data
are not multiplexed.
$ref: /schemas/types.yaml#/definitions/flag
st,fmc2-ebi-cs-buswidth:
description: Data bus width
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 8, 16 ]
default: 16
st,fmc2-ebi-cs-waitpol-high:
description: Wait signal polarity (NWAIT signal active high).
By default, NWAIT is active low.
$ref: /schemas/types.yaml#/definitions/flag
st,fmc2-ebi-cs-waitcfg-enable:
description: The NWAIT signal indicates wheither the data from the
device are valid or if a wait state must be inserted when accessing
the device in synchronous mode. By default, the NWAIT signal is
active one data cycle before wait state.
$ref: /schemas/types.yaml#/definitions/flag
st,fmc2-ebi-cs-wait-enable:
description: The NWAIT signal is enabled (its level is taken into
account after the programmed latency period to insert wait states
if asserted). By default, the NWAIT signal is disabled.
$ref: /schemas/types.yaml#/definitions/flag
st,fmc2-ebi-cs-asyncwait-enable:
description: The NWAIT signal is taken into account during asynchronous
transactions. By default, the NWAIT signal is not taken into account
during asynchronous transactions.
$ref: /schemas/types.yaml#/definitions/flag
st,fmc2-ebi-cs-cpsize:
description: CRAM page size. The controller splits the burst access
when the memory page is reached. By default, no burst split when
crossing page boundary.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 0, 128, 256, 512, 1024 ]
default: 0
st,fmc2-ebi-cs-byte-lane-setup-ns:
description: This property configures the byte lane setup timing
defined in nanoseconds from NBLx low to Chip Select NEx low.
st,fmc2-ebi-cs-address-setup-ns:
description: This property defines the duration of the address setup
phase in nanoseconds used for asynchronous read/write transactions.
st,fmc2-ebi-cs-address-hold-ns:
description: This property defines the duration of the address hold
phase in nanoseconds used for asynchronous multiplexed read/write
transactions.
st,fmc2-ebi-cs-data-setup-ns:
description: This property defines the duration of the data setup phase
in nanoseconds used for asynchronous read/write transactions.
st,fmc2-ebi-cs-bus-turnaround-ns:
description: This property defines the delay in nanoseconds between the
end of current read/write transaction and the next transaction.
st,fmc2-ebi-cs-data-hold-ns:
description: This property defines the duration of the data hold phase
in nanoseconds used for asynchronous read/write transactions.
st,fmc2-ebi-cs-clk-period-ns:
description: This property defines the FMC_CLK output signal period in
nanoseconds.
st,fmc2-ebi-cs-data-latency-ns:
description: This property defines the data latency before reading or
writing the first data in nanoseconds.
st,fmc2-ebi-cs-write-address-setup-ns:
description: This property defines the duration of the address setup
phase in nanoseconds used for asynchronous write transactions.
st,fmc2-ebi-cs-write-address-hold-ns:
description: This property defines the duration of the address hold
phase in nanoseconds used for asynchronous multiplexed write
transactions.
st,fmc2-ebi-cs-write-data-setup-ns:
description: This property defines the duration of the data setup
phase in nanoseconds used for asynchronous write transactions.
st,fmc2-ebi-cs-write-bus-turnaround-ns:
description: This property defines the delay between the end of current
write transaction and the next transaction in nanoseconds.
st,fmc2-ebi-cs-write-data-hold-ns:
description: This property defines the duration of the data hold phase
in nanoseconds used for asynchronous write transactions.
st,fmc2-ebi-cs-max-low-pulse-ns:
description: This property defines the maximum chip select low pulse
duration in nanoseconds for synchronous transactions. When this timing
reaches 0, the controller splits the current access, toggles NE to
allow device refresh and restarts a new access.
additionalProperties: true
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics Flexible Memory Controller 2 (FMC2)
description: |
The FMC2 functional block makes the interface with: synchronous and
asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
peripherals) and NAND flash memories.
Its main purposes are:
- to translate AXI transactions into the appropriate external device
protocol
- to meet the access time requirements of the external devices
All external devices share the addresses, data and control signals with the
controller. Each external device is accessed by means of a unique Chip
Select. The FMC2 performs only one access at a time to an external device.
maintainers:
- Christophe Kerello <christophe.kerello@foss.st.com>
properties:
compatible:
enum:
- st,stm32mp1-fmc2-ebi
- st,stm32mp25-fmc2-ebi
reg:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
power-domains:
maxItems: 1
"#address-cells":
const: 2
"#size-cells":
const: 1
ranges:
description: |
Reflects the memory layout with four integer values per bank. Format:
<bank-number> 0 <address of the bank> <size>
access-controllers:
minItems: 1
maxItems: 2
patternProperties:
"^.*@[0-4],[a-f0-9]+$":
additionalProperties: true
type: object
$ref: mc-peripheral-props.yaml#
required:
- "#address-cells"
- "#size-cells"
- compatible
- reg
- clocks
- ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/reset/stm32mp1-resets.h>
memory-controller@58002000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "st,stm32mp1-fmc2-ebi";
reg = <0x58002000 0x1000>;
clocks = <&rcc FMC_K>;
resets = <&rcc FMC_R>;
ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
<1 0 0x64000000 0x04000000>, /* EBI CS 2 */
<2 0 0x68000000 0x04000000>, /* EBI CS 3 */
<3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
<4 0 0x80000000 0x10000000>; /* NAND */
psram@0,0 {
compatible = "mtd-ram";
reg = <0 0x00000000 0x100000>;
bank-width = <2>;
st,fmc2-ebi-cs-transaction-type = <1>;
st,fmc2-ebi-cs-address-setup-ns = <60>;
st,fmc2-ebi-cs-data-setup-ns = <30>;
st,fmc2-ebi-cs-bus-turnaround-ns = <5>;
};
nand-controller@4,0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32mp1-fmc2-nfc";
reg = <4 0x00000000 0x1000>,
<4 0x08010000 0x1000>,
<4 0x08020000 0x1000>,
<4 0x01000000 0x1000>,
<4 0x09010000 0x1000>,
<4 0x09020000 0x1000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
<&mdma1 20 0x2 0x12000a08 0x0 0x0>,
<&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
dma-names = "tx", "rx", "ecc";
nand@0 {
reg = <0>;
nand-on-flash-bbt;
#address-cells = <1>;
#size-cells = <1>;
};
};
};
...
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/st,stm32mp25-omm.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/st,stm32mp25-omm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STM32 Octo Memory Manager (OMM)
maintainers:
- Patrice Chotard <patrice.chotard@foss.st.com>
description: |
The STM32 Octo Memory Manager is a low-level interface that enables an
efficient OCTOSPI pin assignment with a full I/O matrix (before alternate
function map) and multiplex of single/dual/quad/octal SPI interfaces over
the same bus. It Supports up to:
- Two single/dual/quad/octal SPI interfaces
- Two ports for pin assignment
properties:
compatible:
const: st,stm32mp25-omm
"#address-cells":
const: 2
"#size-cells":
const: 1
ranges:
description: |
Reflects the memory layout per OSPI instance.
Format:
<chip-select> 0 <registers base address> <size>
minItems: 2
maxItems: 2
reg:
items:
- description: OMM registers
- description: OMM memory map area
reg-names:
items:
- const: regs
- const: memory_map
memory-region:
description:
Memory region shared between the 2 OCTOSPI instance.
One or two phandle to a node describing a memory mapped region
depending of child number.
minItems: 1
maxItems: 2
memory-region-names:
description:
Identify to which OSPI instance the memory region belongs to.
items:
enum: [ospi1, ospi2]
minItems: 1
maxItems: 2
clocks:
maxItems: 3
clock-names:
items:
- const: omm
- const: ospi1
- const: ospi2
resets:
maxItems: 3
reset-names:
items:
- const: omm
- const: ospi1
- const: ospi2
access-controllers:
maxItems: 1
power-domains:
maxItems: 1
st,syscfg-amcr:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: |
The Address Mapping Control Register (AMCR) is used to split the 256MB
memory map area shared between the 2 OSPI instance. The Octo Memory
Manager sets the AMCR depending of the memory-region configuration.
The memory split bitmask description is:
- 000: OCTOSPI1 (256 Mbytes), OCTOSPI2 unmapped
- 001: OCTOSPI1 (192 Mbytes), OCTOSPI2 (64 Mbytes)
- 010: OCTOSPI1 (128 Mbytes), OCTOSPI2 (128 Mbytes)
- 011: OCTOSPI1 (64 Mbytes), OCTOSPI2 (192 Mbytes)
- 1xx: OCTOSPI1 unmapped, OCTOSPI2 (256 Mbytes)
items:
- items:
- description: phandle to syscfg
- description: register offset within syscfg
- description: register bitmask for memory split
st,omm-req2ack-ns:
description:
In multiplexed mode (MUXEN = 1), this field defines the time in
nanoseconds between two transactions.
default: 0
st,omm-cssel-ovr:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Configure the chip select selector override for the 2 OCTOSPIs.
- 0: OCTOSPI1 chip select send to NCS1 OCTOSPI2 chip select send to NCS1
- 1: OCTOSPI1 chip select send to NCS2 OCTOSPI2 chip select send to NCS1
- 2: OCTOSPI1 chip select send to NCS1 OCTOSPI2 chip select send to NCS2
- 3: OCTOSPI1 chip select send to NCS2 OCTOSPI2 chip select send to NCS2
minimum: 0
maximum: 3
default: 0
st,omm-mux:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Configure the muxing between the 2 OCTOSPIs busses and the 2 output ports.
- 0: direct mode
- 1: mux OCTOSPI1 and OCTOSPI2 to port 1
- 2: swapped mode
- 3: mux OCTOSPI1 and OCTOSPI2 to port 2
minimum: 0
maximum: 3
default: 0
patternProperties:
^spi@[0-9]:
type: object
$ref: /schemas/spi/st,stm32mp25-ospi.yaml#
description: Required spi child node
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
- clocks
- clock-names
- resets
- reset-names
- st,syscfg-amcr
- ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/st,stm32mp25-rcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/st,stm32mp25-rcc.h>
ommanager@40500000 {
compatible = "st,stm32mp25-omm";
reg = <0x40500000 0x400>, <0x60000000 0x10000000>;
reg-names = "regs", "memory_map";
ranges = <0 0 0x40430000 0x400>,
<1 0 0x40440000 0x400>;
memory-region = <&mm_ospi1>, <&mm_ospi2>;
memory-region-names = "ospi1", "ospi2";
pinctrl-0 = <&ospi_port1_clk_pins_a
&ospi_port1_io03_pins_a
&ospi_port1_cs0_pins_a>;
pinctrl-1 = <&ospi_port1_clk_sleep_pins_a
&ospi_port1_io03_sleep_pins_a
&ospi_port1_cs0_sleep_pins_a>;
pinctrl-names = "default", "sleep";
clocks = <&rcc CK_BUS_OSPIIOM>,
<&scmi_clk CK_SCMI_OSPI1>,
<&scmi_clk CK_SCMI_OSPI2>;
clock-names = "omm", "ospi1", "ospi2";
resets = <&rcc OSPIIOM_R>,
<&scmi_reset RST_SCMI_OSPI1>,
<&scmi_reset RST_SCMI_OSPI2>;
reset-names = "omm", "ospi1", "ospi2";
access-controllers = <&rifsc 111>;
power-domains = <&CLUSTER_PD>;
#address-cells = <2>;
#size-cells = <1>;
st,syscfg-amcr = <&syscfg 0x2c00 0x7>;
st,omm-req2ack-ns = <0>;
st,omm-mux = <0>;
st,omm-cssel-ovr = <0>;
spi@0 {
compatible = "st,stm32mp25-ospi";
reg = <0 0 0x400>;
memory-region = <&mm_ospi1>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&hpdma 2 0x62 0x00003121 0x0>,
<&hpdma 2 0x42 0x00003112 0x0>;
dma-names = "tx", "rx";
clocks = <&scmi_clk CK_SCMI_OSPI1>;
resets = <&scmi_reset RST_SCMI_OSPI1>, <&scmi_reset RST_SCMI_OSPI1DLL>;
access-controllers = <&rifsc 74>;
power-domains = <&CLUSTER_PD>;
#address-cells = <1>;
#size-cells = <0>;
st,syscfg-dlyb = <&syscfg 0x1000>;
};
spi@1 {
compatible = "st,stm32mp25-ospi";
reg = <1 0 0x400>;
memory-region = <&mm_ospi1>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&hpdma 3 0x62 0x00003121 0x0>,
<&hpdma 3 0x42 0x00003112 0x0>;
dma-names = "tx", "rx";
clocks = <&scmi_clk CK_KER_OSPI2>;
resets = <&scmi_reset RST_SCMI_OSPI2>, <&scmi_reset RST_SCMI_OSPI1DLL>;
access-controllers = <&rifsc 75>;
power-domains = <&CLUSTER_PD>;
#address-cells = <1>;
#size-cells = <0>;
st,syscfg-dlyb = <&syscfg 0x1000>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/starfive,jh7110-dmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: StarFive JH7110 DMC
maintainers:
- E Shattow <e@freeshell.de>
description:
JH7110 DDR external memory interface LPDDR4/DDR4/DDR3/LPDDR3 32-bit at
2133Mbps (up to 2800Mbps).
properties:
compatible:
items:
- const: starfive,jh7110-dmc
reg:
items:
- description: controller registers
- description: phy registers
clocks:
maxItems: 1
clock-names:
items:
- const: pll
resets:
items:
- description: axi
- description: osc
- description: apb
reset-names:
items:
- const: axi
- const: osc
- const: apb
required:
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/starfive,jh7110-crg.h>
#include <dt-bindings/reset/starfive,jh7110-crg.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
memory-controller@15700000 {
compatible = "starfive,jh7110-dmc";
reg = <0x0 0x15700000 0x0 0x10000>,
<0x0 0x13000000 0x0 0x10000>;
clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
clock-names = "pll";
resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
<&syscrg JH7110_SYSRST_DDR_OSC>,
<&syscrg JH7110_SYSRST_DDR_APB>;
reset-names = "axi", "osc", "apb";
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/ti,da8xx-ddrctl.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ti,da8xx-ddrctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments da8xx DDR2/mDDR memory controller
maintainers:
- Bartosz Golaszewski <bgolaszewski@baylibre.com>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
Documentation:
OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
properties:
compatible:
const: ti,da850-ddr-controller
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
memory-controller@b0000000 {
compatible = "ti,da850-ddr-controller";
reg = <0xb0000000 0xe8>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/ti,gpmc-child.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments GPMC Bus Child Nodes
maintainers:
- Tony Lindgren <tony@atomide.com>
- Roger Quadros <rogerq@kernel.org>
description:
This binding is meant for the child nodes of the GPMC node. The node
represents any device connected to the GPMC bus. It may be a Flash chip,
RAM chip or Ethernet controller, etc. These properties are meant for
configuring the GPMC settings/timings and will accompany the bindings
supported by the respective device.
properties:
reg: true
# GPMC Timing properties for child nodes. All are optional and default to 0.
gpmc,sync-clk-ps:
description: Minimum clock period for synchronous mode
default: 0
# Chip-select signal timings corresponding to GPMC_CONFIG2:
gpmc,cs-on-ns:
description: Assertion time
default: 0
gpmc,cs-rd-off-ns:
description: Read deassertion time
default: 0
gpmc,cs-wr-off-ns:
description: Write deassertion time
default: 0
# ADV signal timings corresponding to GPMC_CONFIG3:
gpmc,adv-on-ns:
description: Assertion time
default: 0
gpmc,adv-rd-off-ns:
description: Read deassertion time
default: 0
gpmc,adv-wr-off-ns:
description: Write deassertion time
default: 0
gpmc,adv-aad-mux-on-ns:
description: Assertion time for AAD
default: 0
gpmc,adv-aad-mux-rd-off-ns:
description: Read deassertion time for AAD
default: 0
gpmc,adv-aad-mux-wr-off-ns:
description: Write deassertion time for AAD
default: 0
# WE signals timings corresponding to GPMC_CONFIG4:
gpmc,we-on-ns:
description: Assertion time
default: 0
gpmc,we-off-ns:
description: Deassertion time
default: 0
# OE signals timings corresponding to GPMC_CONFIG4:
gpmc,oe-on-ns:
description: Assertion time
default: 0
gpmc,oe-off-ns:
description: Deassertion time
default: 0
gpmc,oe-aad-mux-on-ns:
description: Assertion time for AAD
default: 0
gpmc,oe-aad-mux-off-ns:
description: Deassertion time for AAD
default: 0
# Access time and cycle time timings (in nanoseconds) corresponding to
# GPMC_CONFIG5:
gpmc,page-burst-access-ns:
description: Multiple access word delay
default: 0
gpmc,access-ns:
description: Start-cycle to first data valid delay
default: 0
gpmc,rd-cycle-ns:
description: Total read cycle time
default: 0
gpmc,wr-cycle-ns:
description: Total write cycle time
default: 0
gpmc,bus-turnaround-ns:
description: Turn-around time between successive accesses
default: 0
gpmc,cycle2cycle-delay-ns:
description: Delay between chip-select pulses
default: 0
gpmc,clk-activation-ns:
description: GPMC clock activation time
default: 0
gpmc,wait-monitoring-ns:
description: Start of wait monitoring with regard to valid data
default: 0
# Boolean timing parameters. If property is present, parameter is enabled
# otherwise disabled.
gpmc,adv-extra-delay:
description: ADV signal is delayed by half GPMC clock
type: boolean
gpmc,cs-extra-delay:
description: CS signal is delayed by half GPMC clock
type: boolean
gpmc,cycle2cycle-diffcsen:
description: |
Add "cycle2cycle-delay" between successive accesses
to a different CS
type: boolean
gpmc,cycle2cycle-samecsen:
description: |
Add "cycle2cycle-delay" between successive accesses
to the same CS
type: boolean
gpmc,oe-extra-delay:
description: OE signal is delayed by half GPMC clock
type: boolean
gpmc,we-extra-delay:
description: WE signal is delayed by half GPMC clock
type: boolean
gpmc,time-para-granularity:
description: Multiply all access times by 2
type: boolean
# The following two properties are applicable only to OMAP3+ and AM335x:
gpmc,wr-access-ns:
description: |
In synchronous write mode, for single or
burst accesses, defines the number of
GPMC_FCLK cycles from start access time
to the GPMC_CLK rising edge used by the
memory device for the first data capture.
default: 0
gpmc,wr-data-mux-bus-ns:
description: |
In address-data multiplex mode, specifies
the time when the first data is driven on
the address-data bus.
default: 0
# GPMC chip-select settings properties for child nodes. All are optional.
gpmc,burst-length:
description: Page/burst length.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 4, 8, 16]
default: 0
gpmc,burst-wrap:
description: Enables wrap bursting
type: boolean
gpmc,burst-read:
description: Enables read page/burst mode
type: boolean
gpmc,burst-write:
description: Enables write page/burst mode
type: boolean
gpmc,device-width:
description: |
Total width of device(s) connected to a GPMC
chip-select in bytes. The GPMC supports 8-bit
and 16-bit devices and so this property must be
1 or 2.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2]
default: 1
gpmc,mux-add-data:
description: |
Address and data multiplexing configuration.
Valid values are
0 for Non multiplexed mode
1 for address-address-data multiplexing mode and
2 for address-data multiplexing mode.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2]
gpmc,sync-read:
description: |
Enables synchronous read. Defaults to asynchronous
is this is not set.
type: boolean
gpmc,sync-write:
description: |
Enables synchronous writes. Defaults to asynchronous
is this is not set.
type: boolean
gpmc,wait-pin:
description: |
Wait-pin used by client. Must be less than "gpmc,num-waitpins".
$ref: /schemas/types.yaml#/definitions/uint32
ti,wait-pin-polarity:
description: |
Set the desired polarity for the selected wait pin.
0 for active low, 1 for active high.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
gpmc,wait-on-read:
description: Enables wait monitoring on reads.
type: boolean
gpmc,wait-on-write:
description: Enables wait monitoring on writes.
type: boolean
required:
- reg
# the GPMC child will have its own native properties
additionalProperties: true
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments GPMC Memory Controller
maintainers:
- Tony Lindgren <tony@atomide.com>
- Roger Quadros <rogerq@kernel.org>
description:
The GPMC is a unified memory controller dedicated for interfacing
with external memory devices like
- Asynchronous SRAM-like memories and ASICs
- Asynchronous, synchronous, and page mode burst NOR flash
- NAND flash
- Pseudo-SRAM devices
properties:
compatible:
items:
- enum:
- ti,am3352-gpmc
- ti,am64-gpmc
- ti,omap2420-gpmc
- ti,omap2430-gpmc
- ti,omap3430-gpmc
- ti,omap4430-gpmc
reg:
minItems: 1
maxItems: 2
reg-names:
items:
- const: cfg
- const: data
interrupts:
maxItems: 1
clocks:
maxItems: 1
description: |
Functional clock. Used for bus timing calculations and
GPMC configuration.
clock-names:
items:
- const: fck
power-domains:
maxItems: 1
dmas:
items:
- description: DMA channel for GPMC NAND prefetch
dma-names:
items:
- const: rxtx
"#address-cells": true
"#size-cells": true
gpmc,num-cs:
description: maximum number of supported chip-select lines.
$ref: /schemas/types.yaml#/definitions/uint32
gpmc,num-waitpins:
description: maximum number of supported wait pins.
$ref: /schemas/types.yaml#/definitions/uint32
ranges:
minItems: 1
description: |
Must be set up to reflect the memory layout with four
integer values for each chip-select line in use,
<cs-number> 0 <physical address of mapping> <size>
items:
- description: NAND bank 0
- description: NOR/SRAM bank 0
- description: NOR/SRAM bank 1
'#interrupt-cells':
const: 2
interrupt-controller:
description: |
The GPMC driver implements an interrupt controller for
the NAND events "fifoevent" and "termcount" plus the
rising/falling edges on the GPMC_WAIT pins.
The interrupt number mapping is as follows
0 - NAND_fifoevent
1 - NAND_termcount
2 - GPMC_WAIT0 pin edge
3 - GPMC_WAIT1 pin edge, and so on.
'#gpio-cells':
const: 2
gpio-controller:
description: |
The GPMC driver implements a GPIO controller for the
GPMC WAIT pins that can be used as general purpose inputs.
0 maps to GPMC_WAIT0 pin.
ti,hwmods:
description:
Name of the HWMOD associated with GPMC. This is for legacy
omap2/3 platforms only.
$ref: /schemas/types.yaml#/definitions/string
deprecated: true
ti,no-idle-on-init:
description:
Prevent idling the module at init. This is for legacy omap2/3
platforms only.
type: boolean
deprecated: true
patternProperties:
"@[0-7],[a-f0-9]+$":
type: object
description: |
The child device node represents the device connected to the GPMC
bus. The device can be a NAND chip, SRAM device, NOR device
or an ASIC.
$ref: ti,gpmc-child.yaml
additionalProperties: true
required:
- compatible
- reg
- gpmc,num-cs
- gpmc,num-waitpins
- "#address-cells"
- "#size-cells"
allOf:
- if:
properties:
compatible:
contains:
const: ti,am64-gpmc
then:
required:
- reg-names
- power-domains
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
gpmc: memory-controller@50000000 {
compatible = "ti,am3352-gpmc";
reg = <0x50000000 0x2000>;
interrupts = <100>;
clocks = <&l3s_clkctrl>;
clock-names = "fck";
dmas = <&edma 52 0>;
dma-names = "rxtx";
gpmc,num-cs = <8>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>;
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch16";
ti,elm-id = <&elm>;
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt
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* Device tree bindings for Texas instruments AEMIF controller
The Async External Memory Interface (EMIF16/AEMIF) controller is intended to
provide a glue-less interface to a variety of asynchronous memory devices like
ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories
can be accessed at any given time via four chip selects with 64M byte access
per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM
and Mobile SDR are not supported.
Documentation:
Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
Required properties:
- compatible: "ti,davinci-aemif"
"ti,keystone-aemif"
"ti,da850-aemif"
- reg: contains offset/length value for AEMIF control registers
space.
- #address-cells: Must be 2. The partition number has to be encoded in the
first address cell and it may accept values 0..N-1
(N - total number of partitions). It's recommended to
assign N-1 number for the control partition. The second
cell is the offset into the partition.
- #size-cells: Must be set to 1.
- ranges: Contains memory regions. There are two types of
ranges/partitions:
- CS-specific partition/range. If continuous, must be
set up to reflect the memory layout for 4 chipselects,
if not then additional range/partition can be added and
child device can select the proper one.
- control partition which is common for all CS
interfaces.
- clocks: the clock feeding the controller clock. Required only
if clock tree data present in device tree.
See clock-bindings.txt
- clock-names: clock name. It has to be "aemif". Required only if clock
tree data present in device tree, in another case don't
use it.
See clock-bindings.txt
- clock-ranges: Empty property indicating that child nodes can inherit
named clocks. Required only if clock tree data present
in device tree.
See clock-bindings.txt
Child chip-select (cs) nodes contain the memory devices nodes connected to
such as NOR (e.g. cfi-flash) and NAND (ti,davinci-nand, see davinci-nand.txt).
There might be board specific devices like FPGAs.
Required child cs node properties:
- #address-cells: Must be 2.
- #size-cells: Must be 1.
- ranges: Empty property indicating that child nodes can inherit
memory layout.
- clock-ranges: Empty property indicating that child nodes can inherit
named clocks. Required only if clock tree data present
in device tree.
- ti,cs-chipselect: number of chipselect. Indicates on the aemif driver
which chipselect is used for accessing the memory. For
compatibles "ti,davinci-aemif" and "ti,keystone-aemif"
it can be in range [0-3]. For compatible
"ti,da850-aemif" range is [2-5].
Optional child cs node properties:
- ti,cs-bus-width: width of the asynchronous device's data bus
8 or 16 if not preset 8
- ti,cs-select-strobe-mode: enable/disable select strobe mode
In select strobe mode chip select behaves as
the strobe and is active only during the strobe
period. If present then enable.
- ti,cs-extended-wait-mode: enable/disable extended wait mode
if set, the controller monitors the EMIFWAIT pin
mapped to that chip select to determine if the
device wants to extend the strobe period. If
present then enable.
- ti,cs-min-turnaround-ns: minimum turn around time, ns
Time between the end of one asynchronous memory
access and the start of another asynchronous
memory access. This delay is not incurred
between a read followed by read or a write
followed by a write to same chip select.
- ti,cs-read-setup-ns: read setup width, ns
Time between the beginning of a memory cycle
and the activation of read strobe.
Minimum value is 1 (0 treated as 1).
- ti,cs-read-strobe-ns: read strobe width, ns
Time between the activation and deactivation of
the read strobe.
Minimum value is 1 (0 treated as 1).
- ti,cs-read-hold-ns: read hold width, ns
Time between the deactivation of the read
strobe and the end of the cycle (which may be
either an address change or the deactivation of
the chip select signal.
Minimum value is 1 (0 treated as 1).
- ti,cs-write-setup-ns: write setup width, ns
Time between the beginning of a memory cycle
and the activation of write strobe.
Minimum value is 1 (0 treated as 1).
- ti,cs-write-strobe-ns: write strobe width, ns
Time between the activation and deactivation of
the write strobe.
Minimum value is 1 (0 treated as 1).
- ti,cs-write-hold-ns: write hold width, ns
Time between the deactivation of the write
strobe and the end of the cycle (which may be
either an address change or the deactivation of
the chip select signal.
Minimum value is 1 (0 treated as 1).
If any of the above parameters are absent, current parameter value will be taken
from the corresponding HW reg.
Example for aemif, davinci nand and nor flash chip select shown below.
memory-controller@21000a00 {
compatible = "ti,davinci-aemif";
#address-cells = <2>;
#size-cells = <1>;
clocks = <&clkaemif 0>;
clock-names = "aemif";
clock-ranges;
reg = <0x21000A00 0x00000100>;
ranges = <0 0 0x70000000 0x10000000
1 0 0x21000A00 0x00000100>;
/*
* Partition0: CS-specific memory range which is
* implemented as continuous physical memory region
* Partition1: control memory range
*/
nand:cs2 {
#address-cells = <2>;
#size-cells = <1>;
clock-ranges;
ranges;
ti,cs-chipselect = <2>;
/* all timings in nanoseconds */
ti,cs-min-turnaround-ns = <0>;
ti,cs-read-hold-ns = <7>;
ti,cs-read-strobe-ns = <42>;
ti,cs-read-setup-ns = <14>;
ti,cs-write-hold-ns = <7>;
ti,cs-write-strobe-ns = <42>;
ti,cs-write-setup-ns = <14>;
nand@0,0x8000000 {
compatible = "ti,davinci-nand";
reg = <0 0x8000000 0x4000000
1 0x0000000 0x0000100>;
/*
* Partition0, offset 0x8000000, size 0x4000000
* Partition1, offset 0x0000000, size 0x0000100
*/
.. see davinci-nand.txt
};
};
nor:cs0 {
#address-cells = <2>;
#size-cells = <1>;
clock-ranges;
ranges;
ti,cs-chipselect = <0>;
/* all timings in nanoseconds */
ti,cs-min-turnaround-ns = <0>;
ti,cs-read-hold-ns = <8>;
ti,cs-read-strobe-ns = <40>;
ti,cs-read-setup-ns = <14>;
ti,cs-write-hold-ns = <7>;
ti,cs-write-strobe-ns = <40>;
ti,cs-write-setup-ns = <14>;
ti,cs-bus-width = <16>;
flash@0,0x0000000 {
compatible = "cfi-flash";
reg = <0 0x0000000 0x4000000>;
...
};
};
};
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* EMIF family of TI SDRAM controllers
EMIF - External Memory Interface - is an SDRAM controller used in
TI SoCs. EMIF supports, based on the IP revision, one or more of
DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
of the EMIF IP and memory parts attached to it. Certain revisions
of the EMIF controller also contain optional ECC support, which
corrects one bit errors and detects two bit errors.
Required properties:
- compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
is the IP revision of the specific EMIF instance. For newer controllers,
compatible should be one of the following:
"ti,emif-am3352"
"ti,emif-am4372"
"ti,emif-dra7xx"
"ti,emif-keystone"
- phy-type : <u32> indicating the DDR phy type. Following are the
allowed values
<1> : Attila PHY
<2> : Intelli PHY
- device-handle : phandle to a "lpddr2" node representing the memory part
- ti,hwmods : For TI hwmods processing and omap device creation
the value shall be "emif<n>" where <n> is the number of the EMIF
instance with base 1.
- interrupts : interrupt used by the controller
Required only for "ti,emif-am3352" and "ti,emif-am4372":
- sram : Phandles for generic sram driver nodes,
first should be type 'protect-exec' for the driver to use to copy
and run PM functions, second should be regular pool to be used for
data region for code. See Documentation/devicetree/bindings/sram/sram.yaml
for more details.
Optional properties:
- cs1-used : Have this property if CS1 of this EMIF
instance has a memory part attached to it. If there is a memory
part attached to CS1, it should be the same type as the one on CS0,
so there is no need to give the details of this memory part.
- cal-resistor-per-cs : Have this property if the board has one
calibration resistor per chip-select.
- hw-caps-read-idle-ctrl: Have this property if the controller
supports read idle window programming
- hw-caps-dll-calib-ctrl: Have this property if the controller
supports dll calibration control
- hw-caps-ll-interface : Have this property if the controller
has a low latency interface and corresponding interrupt events
- hw-caps-temp-alert : Have this property if the controller
has capability for generating SDRAM temperature alerts
-Examples:
emif1: emif@4c000000 {
compatible = "ti,emif-4d";
ti,hwmods = "emif2";
phy-type = <1>;
device-handle = <&elpida_ECB240ABACN>;
cs1-used;
hw-caps-read-idle-ctrl;
hw-caps-ll-interface;
hw-caps-temp-alert;
};
/* From am33xx.dtsi */
emif: emif@4c000000 {
compatible = "ti,emif-am3352";
reg = <0x4C000000 0x1000>;
sram = <&pm_sram_code
&pm_sram_data>;
};
emif1: emif@4c000000 {
compatible = "ti,emif-dra7xx";
reg = <0x4c000000 0x200>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Versal DDRMC (Integrated DDR Memory Controller)
maintainers:
- Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
- Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
description:
The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/
4X memory interfaces. Versal DDR memory controller has an optional ECC support
which correct single bit ECC errors and detect double bit ECC errors.
properties:
compatible:
const: xlnx,versal-ddrmc
reg:
items:
- description: DDR Memory Controller registers
- description: NOC registers corresponding to DDR Memory Controller
reg-names:
items:
- const: base
- const: noc
interrupts:
maxItems: 1
required:
- compatible
- reg
- reg-names
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
bus {
#address-cells = <2>;
#size-cells = <2>;
memory-controller@f6150000 {
compatible = "xlnx,versal-ddrmc";
reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>;
reg-names = "base", "noc";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-net-ddrmc5.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-net-ddrmc5.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Versal NET Memory Controller
maintainers:
- Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
description:
The integrated DDR Memory Controllers (DDRMCs) support both DDR5 and LPDDR5
compact and extended memory interfaces. Versal NET DDR memory controller
has an optional ECC support which correct single bit ECC errors and detect
double bit ECC errors. It also has support for reporting other errors like
MMCM (Mixed-Mode Clock Manager) errors and General software errors.
properties:
compatible:
const: xlnx,versal-net-ddrmc5
amd,rproc:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle to the remoteproc_r5 rproc node using which APU interacts
with remote processor. APU primarily communicates with the RPU for
accessing the DDRMC address space and getting error notification.
required:
- compatible
- amd,rproc
additionalProperties: false
examples:
- |
memory-controller {
compatible = "xlnx,versal-net-ddrmc5";
amd,rproc = <&remoteproc_r5>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Zynq A05 DDR Memory Controller
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
- Michal Simek <michal.simek@amd.com>
description:
The Zynq DDR ECC controller has an optional ECC support in half-bus width
(16-bit) configuration. It is capable of correcting single bit ECC errors
and detecting double bit ECC errors.
properties:
compatible:
const: xlnx,zynq-ddrc-a05
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
};
...
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/xlnx,zynqmp-ocmc-1.0.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/xlnx,zynqmp-ocmc-1.0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynqmp OCM(On-Chip Memory) Controller
maintainers:
- Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
- Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
description: |
The OCM supports 64-bit wide ECC functionality to detect multi-bit errors
and recover from a single-bit memory fault.On a write, if all bytes are
being written, the ECC is generated and written into the ECC RAM along with
the write-data that is written into the data RAM. If one or more bytes are
not written, then the read operation results in an correctable error or
uncorrectable error.
properties:
compatible:
const: xlnx,zynqmp-ocmc-1.0
reg:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
memory-controller@ff960000 {
compatible = "xlnx,zynqmp-ocmc-1.0";
reg = <0xff960000 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
};