lastdragon/linux-kernel
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Resguardo inicial

Browse Source
This commit is contained in:
lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,ddr4.yaml
+34
View File
@@ -0,0 +1,34 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,ddr4.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: DDR4 SDRAM compliant to JEDEC JESD79-4D
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
allOf:
- $ref: jedec,sdram-props.yaml#
properties:
compatible:
items:
- pattern: "^ddr4-[0-9a-f]{4},[a-z]{1,20}-[0-9a-f]{2}$"
- const: jedec,ddr4
required:
- compatible
- density
- io-width
unevaluatedProperties: false
examples:
- |
ddr {
compatible = "ddr4-00ff,azaz-ff", "jedec,ddr4";
density = <8192>;
io-width = <8>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml
+135
View File
@@ -0,0 +1,135 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:
const: jedec,lpddr2-timings
max-freq:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Maximum DDR clock frequency for the speed-bin, in Hz.
min-freq:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Minimum DDR clock frequency for the speed-bin, in Hz.
tCKESR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
CKE minimum pulse width during SELF REFRESH (low pulse width during
SELF REFRESH) in pico seconds.
tDQSCK-max:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
DQS output data access time from CK_t/CK_c in pico seconds.
tDQSCK-max-derated:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
DQS output data access time from CK_t/CK_c, temperature de-rated, in pico
seconds.
tFAW:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Four-bank activate window in pico seconds.
tRAS-max-ns:
description: |
Row active time in nano seconds.
tRAS-min:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Row active time in pico seconds.
tRCD:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
RAS-to-CAS delay in pico seconds.
tRPab:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Row precharge time (all banks) in pico seconds.
tRRD:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Active bank A to active bank B in pico seconds.
tRTP:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Internal READ to PRECHARGE command delay in pico seconds.
tWR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
WRITE recovery time in pico seconds.
tWTR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Internal WRITE-to-READ command delay in pico seconds.
tXP:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Exit power-down to next valid command delay in pico seconds.
tZQCL:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Long calibration time in pico seconds.
tZQCS:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Short calibration time in pico seconds.
tZQinit:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Initialization calibration time in pico seconds.
required:
- compatible
- min-freq
- max-freq
additionalProperties: false
examples:
- |
timings {
compatible = "jedec,lpddr2-timings";
min-freq = <10000000>;
max-freq = <400000000>;
tCKESR = <15000>;
tDQSCK-max = <5500>;
tFAW = <50000>;
tRAS-max-ns = <70000>;
tRAS-min = <42000>;
tRPab = <21000>;
tRCD = <18000>;
tRRD = <10000>;
tRTP = <7500>;
tWR = <15000>;
tWTR = <7500>;
tXP = <7500>;
tZQCL = <360000>;
tZQCS = <90000>;
tZQinit = <1000000>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml
+204
View File
@@ -0,0 +1,204 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
allOf:
- $ref: jedec,sdram-props.yaml#
properties:
compatible:
oneOf:
- items:
- enum:
- elpida,ECB240ABACN
- elpida,B8132B2PB-6D-F
- enum:
- jedec,lpddr2-nvm
- jedec,lpddr2-s2
- jedec,lpddr2-s4
- items:
- pattern: "^lpddr2-[0-9a-f]{2},[0-9a-f]{4}$"
- enum:
- jedec,lpddr2-nvm
- jedec,lpddr2-s2
- jedec,lpddr2-s4
revision-id1:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 255
description: |
Revision 1 value of SDRAM chip. Obtained from device datasheet.
Property is deprecated, use revision-id instead.
deprecated: true
revision-id2:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 255
description: |
Revision 2 value of SDRAM chip. Obtained from device datasheet.
Property is deprecated, use revision-id instead.
deprecated: true
tRRD-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
Active bank a to active bank b in terms of number of clock cycles.
Obtained from device datasheet.
tWTR-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
Internal WRITE-to-READ command delay in terms of number of clock cycles.
Obtained from device datasheet.
tXP-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
Exit power-down to next valid command delay in terms of number of clock
cycles. Obtained from device datasheet.
tRTP-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
Internal READ to PRECHARGE command delay in terms of number of clock
cycles. Obtained from device datasheet.
tCKE-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
of clock cycles. Obtained from device datasheet.
tRPab-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
Row precharge time (all banks) in terms of number of clock cycles.
Obtained from device datasheet.
tRCD-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
RAS-to-CAS delay in terms of number of clock cycles. Obtained from
device datasheet.
tWR-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
WRITE recovery time in terms of number of clock cycles. Obtained from
device datasheet.
tRASmin-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
Row active time in terms of number of clock cycles. Obtained from device
datasheet.
tCKESR-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
CKE minimum pulse width during SELF REFRESH (low pulse width during
SELF REFRESH) in terms of number of clock cycles. Obtained from device
datasheet.
tFAW-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 16
description: |
Four-bank activate window in terms of number of clock cycles. Obtained
from device datasheet.
patternProperties:
"^lpddr2-timings":
$ref: jedec,lpddr2-timings.yaml
description: |
The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
"lpddr2-timings" provides AC timing parameters of the device for
a given speed-bin. The user may provide the timings for as many
speed-bins as is required.
required:
- compatible
- density
- io-width
unevaluatedProperties: false
examples:
- |
elpida_ECB240ABACN: lpddr2 {
compatible = "elpida,ECB240ABACN", "jedec,lpddr2-s4";
density = <2048>;
io-width = <32>;
revision-id = <1 0>;
tRPab-min-tck = <3>;
tRCD-min-tck = <3>;
tWR-min-tck = <3>;
tRASmin-min-tck = <3>;
tRRD-min-tck = <2>;
tWTR-min-tck = <2>;
tXP-min-tck = <2>;
tRTP-min-tck = <2>;
tCKE-min-tck = <3>;
tCKESR-min-tck = <3>;
tFAW-min-tck = <8>;
timings_elpida_ECB240ABACN_400mhz: lpddr2-timings0 {
compatible = "jedec,lpddr2-timings";
min-freq = <10000000>;
max-freq = <400000000>;
tRPab = <21000>;
tRCD = <18000>;
tWR = <15000>;
tRAS-min = <42000>;
tRRD = <10000>;
tWTR = <7500>;
tXP = <7500>;
tRTP = <7500>;
tCKESR = <15000>;
tDQSCK-max = <5500>;
tFAW = <50000>;
tZQCS = <90000>;
tZQCL = <360000>;
tZQinit = <1000000>;
tRAS-max-ns = <70000>;
};
timings_elpida_ECB240ABACN_200mhz: lpddr2-timings1 {
compatible = "jedec,lpddr2-timings";
min-freq = <10000000>;
max-freq = <200000000>;
tRPab = <21000>;
tRCD = <18000>;
tWR = <15000>;
tRAS-min = <42000>;
tRRD = <10000>;
tWTR = <10000>;
tXP = <7500>;
tRTP = <7500>;
tCKESR = <15000>;
tDQSCK-max = <5500>;
tFAW = <50000>;
tZQCS = <90000>;
tZQCL = <360000>;
tZQinit = <1000000>;
tRAS-max-ns = <70000>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml
+157
View File
@@ -0,0 +1,157 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:
const: jedec,lpddr3-timings
reg:
maxItems: 1
description: |
Maximum DDR clock frequency for the speed-bin, in Hz.
Property is deprecated, use max-freq.
deprecated: true
max-freq:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Maximum DDR clock frequency for the speed-bin, in Hz.
min-freq:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Minimum DDR clock frequency for the speed-bin, in Hz.
tCKE:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
CKE minimum pulse width (HIGH and LOW pulse width) in pico seconds.
tCKESR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
CKE minimum pulse width during SELF REFRESH (low pulse width during
SELF REFRESH) in pico seconds.
tFAW:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Four-bank activate window in pico seconds.
tMRD:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Mode register set command delay in pico seconds.
tR2R-C2C:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Additional READ-to-READ delay in chip-to-chip cases in pico seconds.
tRAS:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Row active time in pico seconds.
tRC:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
ACTIVATE-to-ACTIVATE command period in pico seconds.
tRCD:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
RAS-to-CAS delay in pico seconds.
tRFC:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Refresh Cycle time in pico seconds.
tRPab:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Row precharge time (all banks) in pico seconds.
tRPpb:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Row precharge time (single banks) in pico seconds.
tRRD:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Active bank A to active bank B in pico seconds.
tRTP:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Internal READ to PRECHARGE command delay in pico seconds.
tW2W-C2C:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Additional WRITE-to-WRITE delay in chip-to-chip cases in pico seconds.
tWR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
WRITE recovery time in pico seconds.
tWTR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Internal WRITE-to-READ command delay in pico seconds.
tXP:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Exit power-down to next valid command delay in pico seconds.
tXSR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
SELF REFRESH exit to next valid command delay in pico seconds.
required:
- compatible
- min-freq
- max-freq
additionalProperties: false
examples:
- |
lpddr3 {
timings {
compatible = "jedec,lpddr3-timings";
max-freq = <800000000>;
min-freq = <100000000>;
tCKE = <3750>;
tCKESR = <3750>;
tFAW = <25000>;
tMRD = <7000>;
tR2R-C2C = <0>;
tRAS = <23000>;
tRC = <33750>;
tRCD = <10000>;
tRFC = <65000>;
tRPab = <12000>;
tRPpb = <12000>;
tRRD = <6000>;
tRTP = <3750>;
tW2W-C2C = <0>;
tWR = <7500>;
tWTR = <3750>;
tXP = <3750>;
tXSR = <70000>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml
+243
View File
@@ -0,0 +1,243 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
allOf:
- $ref: jedec,sdram-props.yaml#
properties:
compatible:
oneOf:
- items:
- enum:
- samsung,K3QF2F20DB
- const: jedec,lpddr3
- items:
- pattern: "^lpddr3-[0-9a-f]{2},[0-9a-f]{4}$"
- const: jedec,lpddr3
'#address-cells':
const: 1
deprecated: true
manufacturer-id:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Manufacturer ID value read from Mode Register 5. The property is
deprecated, manufacturer should be derived from the compatible.
deprecated: true
'#size-cells':
const: 0
deprecated: true
tCKE-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
of clock cycles.
tCKESR-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
CKE minimum pulse width during SELF REFRESH (low pulse width during
SELF REFRESH) in terms of number of clock cycles.
tDQSCK-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
DQS output data access time from CK_t/CK_c in terms of number of clock
cycles.
tFAW-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 63
description: |
Four-bank activate window in terms of number of clock cycles.
tMRD-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
Mode register set command delay in terms of number of clock cycles.
tR2R-C2C-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description: |
Additional READ-to-READ delay in chip-to-chip cases in terms of number
of clock cycles.
tRAS-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 63
description: |
Row active time in terms of number of clock cycles.
tRC-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 63
description: |
ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles.
tRCD-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
RAS-to-CAS delay in terms of number of clock cycles.
tRFC-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 255
description: |
Refresh Cycle time in terms of number of clock cycles.
tRL-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
READ data latency in terms of number of clock cycles.
tRPab-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
Row precharge time (all banks) in terms of number of clock cycles.
tRPpb-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
Row precharge time (single banks) in terms of number of clock cycles.
tRRD-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
Active bank A to active bank B in terms of number of clock cycles.
tRTP-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
Internal READ to PRECHARGE command delay in terms of number of clock
cycles.
tW2W-C2C-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description: |
Additional WRITE-to-WRITE delay in chip-to-chip cases in terms of number
of clock cycles.
tWL-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
WRITE data latency in terms of number of clock cycles.
tWR-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
WRITE recovery time in terms of number of clock cycles.
tWTR-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
Internal WRITE-to-READ command delay in terms of number of clock cycles.
tXP-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 255
description: |
Exit power-down to next valid command delay in terms of number of clock
cycles.
tXSR-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 1023
description: |
SELF REFRESH exit to next valid command delay in terms of number of clock
cycles.
patternProperties:
"^timings((-[0-9])+|(@[0-9a-f]+))?$":
$ref: jedec,lpddr3-timings.yaml
description: |
The lpddr3 node may have one or more child nodes with timings.
Each timing node provides AC timing parameters of the device for a given
speed-bin. The user may provide the timings for as many speed-bins as is
required.
required:
- compatible
- density
- io-width
unevaluatedProperties: false
examples:
- |
lpddr3 {
compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
density = <16384>;
io-width = <32>;
tCKE-min-tck = <2>;
tCKESR-min-tck = <2>;
tDQSCK-min-tck = <5>;
tFAW-min-tck = <5>;
tMRD-min-tck = <5>;
tR2R-C2C-min-tck = <0>;
tRAS-min-tck = <5>;
tRC-min-tck = <6>;
tRCD-min-tck = <3>;
tRFC-min-tck = <17>;
tRL-min-tck = <14>;
tRPab-min-tck = <2>;
tRPpb-min-tck = <2>;
tRRD-min-tck = <2>;
tRTP-min-tck = <2>;
tW2W-C2C-min-tck = <0>;
tWL-min-tck = <8>;
tWR-min-tck = <7>;
tWTR-min-tck = <2>;
tXP-min-tck = <2>;
tXSR-min-tck = <12>;
timings {
compatible = "jedec,lpddr3-timings";
max-freq = <800000000>;
min-freq = <100000000>;
tCKE = <3750>;
tCKESR = <3750>;
tFAW = <25000>;
tMRD = <7000>;
tR2R-C2C = <0>;
tRAS = <23000>;
tRC = <33750>;
tRCD = <10000>;
tRFC = <65000>;
tRPab = <12000>;
tRPpb = <12000>;
tRRD = <6000>;
tRTP = <3750>;
tW2W-C2C = <0>;
tWR = <7500>;
tWTR = <3750>;
tXP = <3750>;
tXSR = <70000>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr4.yaml
+35
View File
@@ -0,0 +1,35 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr4.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LPDDR4 SDRAM compliant to JEDEC JESD209-4
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
allOf:
- $ref: jedec,sdram-props.yaml#
properties:
compatible:
items:
- pattern: "^lpddr4-[0-9a-f]{2},[0-9a-f]{4}$"
- const: jedec,lpddr4
required:
- compatible
- density
- io-width
unevaluatedProperties: false
examples:
- |
lpddr {
compatible = "lpddr4-ff,0100", "jedec,lpddr4";
density = <8192>;
io-width = <16>;
revision-id = <1 0>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr5.yaml
+46
View File
@@ -0,0 +1,46 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr5.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LPDDR5 SDRAM compliant to JEDEC JESD209-5
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
allOf:
- $ref: jedec,sdram-props.yaml#
properties:
compatible:
items:
- pattern: "^lpddr5-[0-9a-f]{2},[0-9a-f]{4}$"
- const: jedec,lpddr5
serial-id:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
Serial IDs read from Mode Registers 47 through 54. One byte per uint32
cell (i.e. <MR47 MR48 MR49 MR50 MR51 MR52 MR53 MR54>).
maxItems: 8
items:
minimum: 0
maximum: 255
required:
- compatible
- density
- io-width
unevaluatedProperties: false
examples:
- |
lpddr {
compatible = "lpddr5-01,0200", "jedec,lpddr5";
density = <8192>;
io-width = <8>;
revision-id = <2 0>;
serial-id = <3 1 0 0 0 0 0 0>;
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-channel.yaml
+160
View File
@@ -0,0 +1,160 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,sdram-channel.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SDRAM channel with chip/rank topology description
description:
A memory channel of SDRAM memory like DDR SDRAM or LPDDR SDRAM is a completely
independent set of pins (DQ, CA, CS, CK, etc.) that connect one or more memory
chips to a host system. The main purpose of this node is to overall memory
topology of the system, including the amount of individual memory chips and
the ranks per chip.
maintainers:
- Julius Werner <jwerner@chromium.org>
properties:
$nodename:
pattern: "sdram-channel-[0-9]+$"
compatible:
enum:
- jedec,ddr4-channel
- jedec,lpddr2-channel
- jedec,lpddr3-channel
- jedec,lpddr4-channel
- jedec,lpddr5-channel
io-width:
description:
The number of DQ pins in the channel. If this number is different
from (a multiple of) the io-width of the SDRAM chip, that means that
multiple instances of that type of chip are wired in parallel on this
channel (with the channel's DQ pins split up between the different
chips, and the CA, CS, etc. pins of the different chips all shorted
together). This means that the total physical memory controlled by a
channel is equal to the sum of the densities of each rank on the
connected SDRAM chip, times the io-width of the channel divided by
the io-width of the SDRAM chip.
enum:
- 8
- 16
- 32
- 64
- 128
"#address-cells":
const: 1
"#size-cells":
const: 0
patternProperties:
"^rank@[0-9]+$":
type: object
description:
Each physical SDRAM chip may have one or more ranks. Ranks are
internal but fully independent sub-units of the chip. Each SDRAM bus
transaction on the channel targets exactly one rank, based on the
state of the CS pins. Different ranks may have different densities and
timing requirements.
required:
- reg
allOf:
- if:
properties:
compatible:
contains:
const: jedec,ddr4-channel
then:
patternProperties:
"^rank@[0-9]+$":
$ref: /schemas/memory-controllers/ddr/jedec,ddr4.yaml#
- if:
properties:
compatible:
contains:
const: jedec,lpddr2-channel
then:
patternProperties:
"^rank@[0-9]+$":
$ref: /schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
- if:
properties:
compatible:
contains:
const: jedec,lpddr3-channel
then:
patternProperties:
"^rank@[0-9]+$":
$ref: /schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
- if:
properties:
compatible:
contains:
const: jedec,lpddr4-channel
then:
patternProperties:
"^rank@[0-9]+$":
$ref: /schemas/memory-controllers/ddr/jedec,lpddr4.yaml#
- if:
properties:
compatible:
contains:
const: jedec,lpddr5-channel
then:
patternProperties:
"^rank@[0-9]+$":
$ref: /schemas/memory-controllers/ddr/jedec,lpddr5.yaml#
required:
- compatible
- io-width
- "#address-cells"
- "#size-cells"
additionalProperties: false
examples:
- |
sdram-channel-0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "jedec,lpddr3-channel";
io-width = <32>;
rank@0 {
compatible = "lpddr3-ff,0100", "jedec,lpddr3";
reg = <0>;
density = <8192>;
io-width = <16>;
revision-id = <1 0>;
};
};
sdram-channel-1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "jedec,lpddr4-channel";
io-width = <32>;
rank@0 {
compatible = "lpddr4-05,0301", "jedec,lpddr4";
reg = <0>;
density = <4096>;
io-width = <32>;
revision-id = <3 1>;
};
rank@1 {
compatible = "lpddr4-05,0301", "jedec,lpddr4";
reg = <1>;
density = <2048>;
io-width = <32>;
revision-id = <3 1>;
};
};
linux-7.2.3/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,sdram-props.yaml
+94
View File
@@ -0,0 +1,94 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,sdram-props.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Common properties for SDRAM types
description:
Different SDRAM types generally use the same properties and only differ in the
range of legal values for each. This file defines the common parts that can be
reused for each type. Nodes using this schema should generally be nested under
a SDRAM channel node.
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:
description: |
Compatible strings can be either explicit vendor names and part numbers
(e.g. elpida,ECB240ABACN), or generated strings of the form
lpddrX-YY,ZZZZ or ddrX-YYYY,AAAA...-ZZ where X, Y, and Z are lowercase
hexadecimal with leading zeroes, and A is lowercase ASCII.
For LPDDR and DDR SDRAM, X is the SDRAM version (2, 3, 4, etc.).
For LPDDR SDRAM:
- YY is the manufacturer ID (from MR5), 1 byte
- ZZZZ is the revision ID (from MR6 and MR7), 2 bytes
For DDR4 SDRAM with SPD, according to JEDEC SPD4.1.2.L-6:
- YYYY is the manufacturer ID, 2 bytes, from bytes 320 and 321
- AAAA... is the part number, 20 bytes (20 chars) from bytes 329 to 348
without trailing spaces
- ZZ is the revision ID, 1 byte, from byte 349
The former form is useful when the SDRAM vendor and part number are
known, for example, when memory is soldered on the board. The latter
form is useful when SDRAM nodes are created at runtime by boot firmware
that doesn't have access to static part number information.
reg:
description:
The rank number of this memory rank when used as a subnode to an memory
channel.
minimum: 0
maximum: 3
revision-id:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: |
SDRAM revision ID:
- LPDDR SDRAM, decoded from Mode Registers 6 and 7, always 2 bytes.
- DDR4 SDRAM, decoded from the SPD from byte 349 according to
JEDEC SPD4.1.2.L-6, always 1 byte.
One byte per uint32 cell (e.g., <MR6 MR7>).
maxItems: 2
items:
minimum: 0
maximum: 255
density:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Density of the SDRAM chip in megabits:
- LPDDR SDRAM, decoded from Mode Register 8.
- DDR4 SDRAM, decoded from the SPD from bits 3-0 of byte 4 according to
JEDEC SPD4.1.2.L-6.
enum:
- 64
- 128
- 256
- 512
- 1024
- 2048
- 3072
- 4096
- 6144
- 8192
- 12288
- 16384
- 24576
- 32768
io-width:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
I/O bus width in bits of the SDRAM chip:
- LPDDR SDRAM, decoded from Mode Register 8.
- DDR4 SDRAM, decoded from the SPD from bits 2-0 of byte 12 according to
JEDEC SPD4.1.2.L-6.
enum:
- 8
- 16
- 32
additionalProperties: true