lastdragon/linux-kernel
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Resguardo inicial

Browse Source
This commit is contained in:
lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
linux-7.2.3/arch/arm64/boot/dts/realtek/Makefile
+14
View File
@@ -0,0 +1,14 @@
# SPDX-License-Identifier: GPL-2.0-only
dtb-$(CONFIG_ARCH_REALTEK) += rtd1293-ds418j.dtb
dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-mele-v9.dtb
dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-probox2-ava.dtb
dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-xnano-x5.dtb
dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb
dtb-$(CONFIG_ARCH_REALTEK) += rtd1296-ds418.dtb
dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-bpi-m4.dtb
dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-lionskin.dtb
dtb-$(CONFIG_ARCH_REALTEK) += rtd1501s-phantom-8gb.dtb
dtb-$(CONFIG_ARCH_REALTEK) += rtd1619-mjolnir.dtb
dtb-$(CONFIG_ARCH_REALTEK) += rtd1861b-krypton-8gb.dtb
dtb-$(CONFIG_ARCH_REALTEK) += rtd1920s-smallville-4gb.dtb
linux-7.2.3/arch/arm64/boot/dts/realtek/kent.dtsi
+186
View File
@@ -0,0 +1,186 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Realtek Kent SoC family
*
* Copyright (c) 2024 Realtek Semiconductor Corp.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &uart0;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a78";
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&l2_0>;
dynamic-power-coefficient = <454>;
#cooling-cells = <2>;
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-line-size = <64>;
cache-sets = <256>;
cache-size = <0x40000>;
cache-unified;
next-level-cache = <&l3>;
};
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a78";
reg = <0x100>;
enable-method = "psci";
next-level-cache = <&l2_1>;
dynamic-power-coefficient = <454>;
#cooling-cells = <2>;
l2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-line-size = <64>;
cache-sets = <256>;
cache-size = <0x40000>;
cache-unified;
next-level-cache = <&l3>;
};
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a78";
reg = <0x200>;
enable-method = "psci";
next-level-cache = <&l2_2>;
dynamic-power-coefficient = <454>;
#cooling-cells = <2>;
l2_2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-line-size = <64>;
cache-sets = <256>;
cache-size = <0x40000>;
cache-unified;
next-level-cache = <&l3>;
};
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a78";
reg = <0x300>;
enable-method = "psci";
next-level-cache = <&l2_3>;
dynamic-power-coefficient = <454>;
#cooling-cells = <2>;
l2_3: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-line-size = <64>;
cache-sets = <256>;
cache-size = <0x40000>;
cache-unified;
next-level-cache = <&l3>;
};
};
l3: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-line-size = <64>;
cache-sets = <512>;
cache-size = <0x200000>;
cache-unified;
};
};
psci: psci {
compatible = "arm,psci-1.0";
method = "smc";
};
soc@0 {
compatible = "simple-bus";
ranges = <0x0 0x0 0x0 0x40000>, /* boot code */
<0x98000000 0x0 0x98000000 0xef0000>, /* rbus */
<0xa0000000 0x0 0xa0000000 0x10000000>, /* PCIE */
<0xff000000 0x0 0xff000000 0x200000>; /* GIC */
#address-cells = <1>;
#size-cells = <1>;
rbus: bus@98000000 {
compatible = "simple-bus";
ranges = <0x0 0x98000000 0xef0000>,
<0xa0000000 0xa0000000 0x10000000>; /* PCIE */
#address-cells = <1>;
#size-cells = <1>;
uart0: serial@7800 {
compatible = "snps,dw-apb-uart";
reg = <0x7800 0x100>;
clock-frequency = <432000000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
iso_pinctrl: pinctrl@4e000 {
compatible = "realtek,rtd1625-iso-pinctrl";
reg = <0x4e000 0x1a4>;
};
main2_pinctrl: pinctrl@4f200 {
compatible = "realtek,rtd1625-main2-pinctrl";
reg = <0x4f200 0x50>;
};
isom_pinctrl: pinctrl@146200 {
compatible = "realtek,rtd1625-isom-pinctrl";
reg = <0x146200 0x34>;
};
ve4_pinctrl: pinctrl@14e000 {
compatible = "realtek,rtd1625-ve4-pinctrl";
reg = <0x14e000 0x84>;
};
};
gic: interrupt-controller@ff100000 {
compatible = "arm,gic-v3";
reg = <0xff100000 0x10000>,
<0xff140000 0x80000>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#interrupt-cells = <3>;
#size-cells = <1>;
};
};
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd1293-ds418j.dts
+30
View File
@@ -0,0 +1,30 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
* Copyright (c) 2017-2019 Andreas Färber
*/
/dts-v1/;
#include "rtd1293.dtsi"
/ {
compatible = "synology,ds418j", "realtek,rtd1293";
model = "Synology DiskStation DS418j";
memory@1f000 {
device_type = "memory";
reg = <0x1f000 0x3ffe1000>; /* boot ROM to 1 GiB */
};
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd1293.dtsi
+57
View File
@@ -0,0 +1,57 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
* Realtek RTD1293 SoC
*
* Copyright (c) 2017-2019 Andreas Färber
*/
#include "rtd129x.dtsi"
/ {
compatible = "realtek,rtd1293";
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
next-level-cache = <&l2>;
};
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
};
&arm_pmu {
interrupt-affinity = <&cpu0>, <&cpu1>;
};
&gic {
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd1295-mele-v9.dts
+31
View File
@@ -0,0 +1,31 @@
/*
* Copyright (c) 2017-2019 Andreas Färber
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
#include "rtd1295.dtsi"
/ {
compatible = "mele,v9", "realtek,rtd1295";
model = "MeLE V9";
memory@1f000 {
device_type = "memory";
reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */
};
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd1295-probox2-ava.dts
+31
View File
@@ -0,0 +1,31 @@
/*
* Copyright (c) 2017-2019 Andreas Färber
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
#include "rtd1295.dtsi"
/ {
compatible = "probox2,ava", "realtek,rtd1295";
model = "PROBOX2 AVA";
memory@1f000 {
device_type = "memory";
reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */
};
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd1295-xnano-x5.dts
+30
View File
@@ -0,0 +1,30 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
* Copyright (c) 2017-2019 Andreas Färber
*/
/dts-v1/;
#include "rtd1295.dtsi"
/ {
compatible = "xnano,x5", "realtek,rtd1295";
model = "Xnano X5";
memory@1f000 {
device_type = "memory";
reg = <0x1f000 0x3ffe1000>; /* boot ROM to 1 GiB or 2 GiB */
};
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd1295-zidoo-x9s.dts
+35
View File
@@ -0,0 +1,35 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
* Copyright (c) 2016-2017 Andreas Färber
*/
/dts-v1/;
#include "rtd1295.dtsi"
/ {
compatible = "zidoo,x9s", "realtek,rtd1295";
model = "Zidoo X9S";
memory@1f000 {
device_type = "memory";
reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */
};
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd1295.dtsi
+67
View File
@@ -0,0 +1,67 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
* Realtek RTD1295 SoC
*
* Copyright (c) 2016-2019 Andreas Färber
*/
#include "rtd129x.dtsi"
/ {
compatible = "realtek,rtd1295";
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
next-level-cache = <&l2>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
next-level-cache = <&l2>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
next-level-cache = <&l2>;
};
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
};
&arm_pmu {
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd1296-ds418.dts
+30
View File
@@ -0,0 +1,30 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
* Copyright (c) 2017-2019 Andreas Färber
*/
/dts-v1/;
#include "rtd1296.dtsi"
/ {
compatible = "synology,ds418", "realtek,rtd1296";
model = "Synology DiskStation DS418";
memory@1f000 {
device_type = "memory";
reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */
};
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd1296.dtsi
+67
View File
@@ -0,0 +1,67 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
* Realtek RTD1296 SoC
*
* Copyright (c) 2017-2019 Andreas Färber
*/
#include "rtd129x.dtsi"
/ {
compatible = "realtek,rtd1296";
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
next-level-cache = <&l2>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
next-level-cache = <&l2>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
next-level-cache = <&l2>;
};
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
};
&arm_pmu {
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd129x.dtsi
+195
View File
@@ -0,0 +1,195 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
* Realtek RTD1293/RTD1295/RTD1296 SoC
*
* Copyright (c) 2016-2019 Andreas Färber
*/
/memreserve/ 0x0000000000000000 0x000000000001f000;
/memreserve/ 0x000000000001f000 0x00000000000e1000;
/memreserve/ 0x0000000001b00000 0x00000000004be000;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/realtek,rtd1295.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
rpc_comm: rpc@1f000 {
reg = <0x1f000 0x1000>;
};
rpc_ringbuf: rpc@1ffe000 {
reg = <0x1ffe000 0x4000>;
};
tee: tee@10100000 {
reg = <0x10100000 0xf00000>;
no-map;
};
};
arm_pmu: arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
};
osc27M: osc {
compatible = "fixed-clock";
clock-frequency = <27000000>;
#clock-cells = <0>;
clock-output-names = "osc27M";
};
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
/* Exclude up to 2 GiB of RAM */
<0x80000000 0x80000000 0x80000000>;
rbus: bus@98000000 {
compatible = "simple-bus";
reg = <0x98000000 0x200000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x98000000 0x200000>;
crt: syscon@0 {
compatible = "syscon", "simple-mfd";
reg = <0x0 0x1800>;
reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x1800>;
};
iso: syscon@7000 {
compatible = "syscon", "simple-mfd";
reg = <0x7000 0x1000>;
reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x7000 0x1000>;
};
sb2: syscon@1a000 {
compatible = "syscon", "simple-mfd";
reg = <0x1a000 0x1000>;
reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1a000 0x1000>;
};
misc: syscon@1b000 {
compatible = "syscon", "simple-mfd";
reg = <0x1b000 0x1000>;
reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1b000 0x1000>;
};
scpu_wrapper: syscon@1d000 {
compatible = "syscon", "simple-mfd";
reg = <0x1d000 0x2000>;
reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1d000 0x2000>;
};
};
gic: interrupt-controller@ff011000 {
compatible = "arm,gic-400";
reg = <0xff011000 0x1000>,
<0xff012000 0x2000>,
<0xff014000 0x2000>,
<0xff016000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-controller;
#interrupt-cells = <3>;
};
};
};
&crt {
reset1: reset-controller@0 {
compatible = "snps,dw-low-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
};
reset2: reset-controller@4 {
compatible = "snps,dw-low-reset";
reg = <0x4 0x4>;
#reset-cells = <1>;
};
reset3: reset-controller@8 {
compatible = "snps,dw-low-reset";
reg = <0x8 0x4>;
#reset-cells = <1>;
};
reset4: reset-controller@50 {
compatible = "snps,dw-low-reset";
reg = <0x50 0x4>;
#reset-cells = <1>;
};
};
&iso {
iso_reset: reset-controller@88 {
compatible = "snps,dw-low-reset";
reg = <0x88 0x4>;
#reset-cells = <1>;
};
wdt: watchdog@680 {
compatible = "realtek,rtd1295-watchdog";
reg = <0x680 0x100>;
clocks = <&osc27M>;
};
uart0: serial@800 {
compatible = "snps,dw-apb-uart";
reg = <0x800 0x400>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <27000000>;
resets = <&iso_reset RTD1295_ISO_RSTN_UR0>;
status = "disabled";
};
};
&misc {
uart1: serial@200 {
compatible = "snps,dw-apb-uart";
reg = <0x200 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <432000000>;
resets = <&reset2 RTD1295_RSTN_UR1>;
status = "disabled";
};
uart2: serial@400 {
compatible = "snps,dw-apb-uart";
reg = <0x400 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <432000000>;
resets = <&reset2 RTD1295_RSTN_UR2>;
status = "disabled";
};
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts
+30
View File
@@ -0,0 +1,30 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
* Copyright (c) 2019 Andreas Färber
*/
/dts-v1/;
#include "rtd1395.dtsi"
/ {
compatible = "bananapi,bpi-m4", "realtek,rtd1395";
model = "Banana Pi BPI-M4";
memory@2f000 {
device_type = "memory";
reg = <0x2f000 0x3ffd1000>; /* boot ROM to 1 GiB or 2 GiB */
};
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&uart0 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd1395-lionskin.dts
+36
View File
@@ -0,0 +1,36 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
* Copyright (c) 2019 Andreas Färber
*/
/dts-v1/;
#include "rtd1395.dtsi"
/ {
compatible = "realtek,lion-skin", "realtek,rtd1395";
model = "Realtek Lion Skin EVB";
memory@2f000 {
device_type = "memory";
reg = <0x2f000 0x3ffd1000>; /* boot ROM to 1 GiB or 2 GiB */
};
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
/* debug console (J1) */
&uart0 {
status = "okay";
};
/* M.2 slot (CON1) */
&uart1 {
status = "disabled";
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd1395.dtsi
+67
View File
@@ -0,0 +1,67 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
* Realtek RTD1395 SoC
*
* Copyright (c) 2019 Andreas Färber
*/
#include "rtd139x.dtsi"
/ {
compatible = "realtek,rtd1395";
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
next-level-cache = <&l2>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
next-level-cache = <&l2>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
next-level-cache = <&l2>;
};
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
};
&arm_pmu {
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd139x.dtsi
+193
View File
@@ -0,0 +1,193 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
* Realtek RTD1395 SoC family
*
* Copyright (c) 2019 Andreas Färber
*/
/memreserve/ 0x0000000000000000 0x000000000002f000;
/memreserve/ 0x000000000002f000 0x00000000000d1000;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/realtek,rtd1295.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
rpc_comm: rpc@2f000 {
reg = <0x2f000 0x1000>;
};
rpc_ringbuf: rpc@1ffe000 {
reg = <0x1ffe000 0x4000>;
};
tee: tee@10100000 {
reg = <0x10100000 0xf00000>;
no-map;
};
};
arm_pmu: arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
};
osc27M: osc {
compatible = "fixed-clock";
clock-frequency = <27000000>;
#clock-cells = <0>;
clock-output-names = "osc27M";
};
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
<0x98000000 0x98000000 0x68000000>;
rbus: bus@98000000 {
compatible = "simple-bus";
reg = <0x98000000 0x200000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x98000000 0x200000>;
crt: syscon@0 {
compatible = "syscon", "simple-mfd";
reg = <0x0 0x1000>;
reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x1000>;
};
iso: syscon@7000 {
compatible = "syscon", "simple-mfd";
reg = <0x7000 0x1000>;
reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x7000 0x1000>;
};
sb2: syscon@1a000 {
compatible = "syscon", "simple-mfd";
reg = <0x1a000 0x1000>;
reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1a000 0x1000>;
};
misc: syscon@1b000 {
compatible = "syscon", "simple-mfd";
reg = <0x1b000 0x1000>;
reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1b000 0x1000>;
};
scpu_wrapper: syscon@1d000 {
compatible = "syscon", "simple-mfd";
reg = <0x1d000 0x2000>;
reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1d000 0x2000>;
};
};
gic: interrupt-controller@ff011000 {
compatible = "arm,gic-400";
reg = <0xff011000 0x1000>,
<0xff012000 0x2000>,
<0xff014000 0x2000>,
<0xff016000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-controller;
#interrupt-cells = <3>;
};
};
};
&crt {
reset1: reset-controller@0 {
compatible = "snps,dw-low-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
};
reset2: reset-controller@4 {
compatible = "snps,dw-low-reset";
reg = <0x4 0x4>;
#reset-cells = <1>;
};
reset3: reset-controller@8 {
compatible = "snps,dw-low-reset";
reg = <0x8 0x4>;
#reset-cells = <1>;
};
reset4: reset-controller@50 {
compatible = "snps,dw-low-reset";
reg = <0x50 0x4>;
#reset-cells = <1>;
};
};
&iso {
iso_reset: reset-controller@88 {
compatible = "snps,dw-low-reset";
reg = <0x88 0x4>;
#reset-cells = <1>;
};
wdt: watchdog@680 {
compatible = "realtek,rtd1295-watchdog";
reg = <0x680 0x100>;
clocks = <&osc27M>;
};
uart0: serial@800 {
compatible = "snps,dw-apb-uart";
reg = <0x800 0x400>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <27000000>;
resets = <&iso_reset RTD1295_ISO_RSTN_UR0>;
status = "disabled";
};
};
&misc {
uart1: serial@200 {
compatible = "snps,dw-apb-uart";
reg = <0x200 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <432000000>;
resets = <&reset2 RTD1295_RSTN_UR1>;
status = "disabled";
};
uart2: serial@400 {
compatible = "snps,dw-apb-uart";
reg = <0x400 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <432000000>;
resets = <&reset2 RTD1295_RSTN_UR2>;
status = "disabled";
};
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd1501.dtsi
+12
View File
@@ -0,0 +1,12 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Realtek RTD1501 SoC
*
* Copyright (c) 2024 Realtek Semiconductor Corp.
*/
#include "kent.dtsi"
&uart0 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd1501s-phantom-8gb.dts
+25
View File
@@ -0,0 +1,25 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Realtek RTD1501S Phantom EVB
*
* Copyright (c) 2024 Realtek Semiconductor Corp.
*/
/dts-v1/;
#include "rtd1501s-phantom.dtsi"
/ {
compatible = "realtek,phantom", "realtek,rtd1501s";
model = "Realtek Phantom EVB Chromium (8GB)";
memory@40000 {
device_type = "memory";
reg = <0x0 0x50000 0x0 0x7ffb0000>,
<0x0 0x8a100000 0x0 0xdef0000>,
<0x0 0x98700000 0x0 0x7900000>,
<0x0 0xa0600000 0x0 0x5ea00000>,
<0x1 0x0 0x0 0xa0000000>,
<0x1 0xa0600000 0x0 0x5fa00000>;
};
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd1501s-phantom.dtsi
+118
View File
@@ -0,0 +1,118 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Realtek RTD1501S Phantom EVB
*
* Copyright (c) 2024 Realtek Semiconductor Corp.
*/
/dts-v1/;
#include <dt-bindings/thermal/thermal.h>
#include "rtd1501.dtsi"
/ {
chosen {
stdout-path = "serial0:460800n8";
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
alignment = <0x0 0x400000>;
alloc-ranges = <0x0 0x0 0x0 0x20000000>;
size = <0x0 0x2000000>;
reusable;
linux,cma-default;
};
};
cpu_opps: opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
opp800: opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <830000 830000 1100000>;
};
opp900: opp-900000000 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <850000 850000 1100000>;
};
opp1000: opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <870000 870000 1100000>;
};
opp1100: opp-1100000000 {
opp-hz = /bits/ 64 <1100000000>;
opp-microvolt = <890000 890000 1100000>;
};
opp1200: opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <910000 910000 1100000>;
};
opp1300: opp-1300000000 {
opp-hz = /bits/ 64 <1300000000>;
opp-microvolt = <930000 930000 1100000>;
};
opp1400: opp-1400000000 {
opp-hz = /bits/ 64 <1400000000>;
opp-microvolt = <950000 950000 1100000>;
};
opp1500: opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <970000 970000 1100000>;
};
opp1600: opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <990000 990000 1100000>;
opp-suspend;
};
opp1700: opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <1010000 1010000 1100000>;
};
opp1800: opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1030000 1030000 1100000>;
};
opp1900: opp-1900000000 {
opp-hz = /bits/ 64 <1900000000>;
opp-microvolt = <1050000 1050000 1100000>;
};
};
};
&cpu0 {
operating-points-v2 = <&cpu_opps>;
#cooling-cells = <2>;
};
&cpu1 {
operating-points-v2 = <&cpu_opps>;
#cooling-cells = <2>;
};
&cpu2 {
operating-points-v2 = <&cpu_opps>;
#cooling-cells = <2>;
};
&cpu3 {
operating-points-v2 = <&cpu_opps>;
#cooling-cells = <2>;
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd1619-mjolnir.dts
+44
View File
@@ -0,0 +1,44 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
* Copyright (c) 2019 Realtek Semiconductor Corp.
* Copyright (c) 2019 Andreas Färber
*/
/dts-v1/;
#include "rtd1619.dtsi"
/ {
compatible = "realtek,mjolnir", "realtek,rtd1619";
model = "Realtek Mjolnir EVB";
memory@2e000 {
device_type = "memory";
reg = <0x2e000 0x7ffd2000>; /* boot ROM to 2 GiB */
};
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
};
};
/* debug console (J1) */
&uart0 {
status = "okay";
};
/* M.2 slot (CON4) */
&uart1 {
status = "disabled";
};
/* GPIO connector (T1) */
&uart2 {
status = "disabled";
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd1619.dtsi
+12
View File
@@ -0,0 +1,12 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
* Realtek RTD1619 SoC
*
* Copyright (c) 2019 Realtek Semiconductor Corp.
*/
#include "rtd16xx.dtsi"
/ {
compatible = "realtek,rtd1619";
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd16xx.dtsi
+233
View File
@@ -0,0 +1,233 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
* Realtek RTD16xx SoC family
*
* Copyright (c) 2019 Realtek Semiconductor Corp.
* Copyright (c) 2019 Andreas Färber
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
rpc_comm: rpc@2f000 {
reg = <0x2f000 0x1000>;
};
rpc_ringbuf: rpc@1ffe000 {
reg = <0x1ffe000 0x4000>;
};
tee: tee@10100000 {
reg = <0x10100000 0xf00000>;
no-map;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x100>;
enable-method = "psci";
next-level-cache = <&l3>;
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x200>;
enable-method = "psci";
next-level-cache = <&l3>;
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x300>;
enable-method = "psci";
next-level-cache = <&l3>;
};
cpu4: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x400>;
enable-method = "psci";
next-level-cache = <&l3>;
};
cpu5: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x500>;
enable-method = "psci";
next-level-cache = <&l3>;
};
l2: l2-cache {
compatible = "cache";
next-level-cache = <&l3>;
cache-level = <2>;
cache-unified;
};
l3: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
arm_pmu: pmu {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>,
<&cpu3>, <&cpu4>, <&cpu5>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
osc27M: osc {
compatible = "fixed-clock";
clock-frequency = <27000000>;
clock-output-names = "osc27M";
#clock-cells = <0>;
};
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00000000 0x0002e000>, /* boot ROM */
<0x98000000 0x98000000 0x68000000>;
rbus: bus@98000000 {
compatible = "simple-bus";
reg = <0x98000000 0x200000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x98000000 0x200000>;
crt: syscon@0 {
compatible = "syscon", "simple-mfd";
reg = <0x0 0x1000>;
reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x1000>;
};
iso: syscon@7000 {
compatible = "syscon", "simple-mfd";
reg = <0x7000 0x1000>;
reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x7000 0x1000>;
};
sb2: syscon@1a000 {
compatible = "syscon", "simple-mfd";
reg = <0x1a000 0x1000>;
reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1a000 0x1000>;
};
misc: syscon@1b000 {
compatible = "syscon", "simple-mfd";
reg = <0x1b000 0x1000>;
reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1b000 0x1000>;
};
scpu_wrapper: syscon@1d000 {
compatible = "syscon", "simple-mfd";
reg = <0x1d000 0x1000>;
reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1d000 0x1000>;
};
};
gic: interrupt-controller@ff100000 {
compatible = "arm,gic-v3";
reg = <0xff100000 0x10000>,
<0xff140000 0xc0000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
};
};
};
&iso {
uart0: serial@800 {
compatible = "snps,dw-apb-uart";
reg = <0x800 0x400>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <27000000>;
status = "disabled";
};
};
&misc {
uart1: serial@200 {
compatible = "snps,dw-apb-uart";
reg = <0x200 0x400>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <432000000>;
status = "disabled";
};
uart2: serial@400 {
compatible = "snps,dw-apb-uart";
reg = <0x400 0x400>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <432000000>;
status = "disabled";
};
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd1861.dtsi
+12
View File
@@ -0,0 +1,12 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Realtek RTD1861 SoC
*
* Copyright (c) 2024 Realtek Semiconductor Corp.
*/
#include "kent.dtsi"
&uart0 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd1861b-krypton-8gb.dts
+25
View File
@@ -0,0 +1,25 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Realtek RTD1861B Krypton EVB
*
* Copyright (c) 2024 Realtek Semiconductor Corp.
*/
/dts-v1/;
#include "rtd1861b-krypton.dtsi"
/ {
compatible = "realtek,krypton", "realtek,rtd1861b";
model = "Realtek Krypton EVB (8GB)";
memory@40000 {
device_type = "memory";
reg = <0x0 0x50000 0x0 0x7ffb0000>,
<0x0 0x8a100000 0x0 0xdef0000>,
<0x0 0x98700000 0x0 0x7900000>,
<0x0 0xa0600000 0x0 0x5ea00000>,
<0x1 0x0 0x0 0xa0000000>,
<0x1 0xa0600000 0x0 0x5fa00000>;
};
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd1861b-krypton.dtsi
+72
View File
@@ -0,0 +1,72 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Realtek RTD1861B Krypton EVB
*
* Copyright (c) 2024 Realtek Semiconductor Corp.
*/
/dts-v1/;
#include "rtd1861.dtsi"
/ {
chosen {
stdout-path = "serial0:460800n8";
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
alignment = <0x0 0x400000>;
alloc-ranges = <0x0 0x0 0x0 0x20000000>;
size = <0x0 0x2000000>;
reusable;
linux,cma-default;
};
};
cpu_opps: opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
opp1200: opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <900000>;
};
opp1600: opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <1000000>;
opp-suspend;
};
opp1800: opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1050000>;
};
};
};
&cpu0 {
operating-points-v2 = <&cpu_opps>;
#cooling-cells = <2>;
};
&cpu1 {
operating-points-v2 = <&cpu_opps>;
#cooling-cells = <2>;
};
&cpu2 {
operating-points-v2 = <&cpu_opps>;
#cooling-cells = <2>;
};
&cpu3 {
operating-points-v2 = <&cpu_opps>;
#cooling-cells = <2>;
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd1920.dtsi
+12
View File
@@ -0,0 +1,12 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Realtek RTD1920 SoC
*
* Copyright (c) 2024 Realtek Semiconductor Corp.
*/
#include "kent.dtsi"
&uart0 {
status = "okay";
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd1920s-smallville-4gb.dts
+23
View File
@@ -0,0 +1,23 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Realtek RTD1920S Smallville EVB
*
* Copyright (c) 2024 Realtek Semiconductor Corp.
*/
/dts-v1/;
#include "rtd1920s-smallville.dtsi"
/ {
compatible = "realtek,smallville", "realtek,rtd1920s";
model = "Realtek Smallville EVB (4GB)";
memory@40000 {
device_type = "memory";
reg = <0x0 0x50000 0x0 0x7ffb0000>,
<0x0 0x8a100000 0x0 0xdef0000>,
<0x0 0x98700000 0x0 0x7900000>,
<0x0 0xa1000000 0x0 0x5e000000>;
};
};
linux-7.2.3/arch/arm64/boot/dts/realtek/rtd1920s-smallville.dtsi
+128
View File
@@ -0,0 +1,128 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Realtek RTD1920S Smallville EVB
*
* Copyright (c) 2024 Realtek Semiconductor Corp.
*/
/dts-v1/;
#include <dt-bindings/thermal/thermal.h>
#include "rtd1920.dtsi"
/ {
chosen {
stdout-path = "serial0:460800n8";
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
protected_mem: protected-mem@50000 {
reg = <0x0 0x50000 0x0 0xbf0000>;
no-map;
};
metadata: metadata@c40000 {
reg = <0x0 0xc40000 0x0 0x3c4000>;
no-map;
};
linux,cma {
compatible = "shared-dma-pool";
alignment = <0x0 0x400000>;
alloc-ranges = <0x0 0x0 0x0 0x20000000>;
size = <0x0 0x2000000>;
reusable;
linux,cma-default;
};
};
cpu_opps: opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
opp800: opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <830000 830000 1100000>;
};
opp900: opp-900000000 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <850000 850000 1100000>;
};
opp1000: opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <870000 870000 1100000>;
};
opp1100: opp-1100000000 {
opp-hz = /bits/ 64 <1100000000>;
opp-microvolt = <890000 890000 1100000>;
};
opp1200: opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <910000 910000 1100000>;
};
opp1300: opp-1300000000 {
opp-hz = /bits/ 64 <1300000000>;
opp-microvolt = <930000 930000 1100000>;
};
opp1400: opp-1400000000 {
opp-hz = /bits/ 64 <1400000000>;
opp-microvolt = <950000 950000 1100000>;
};
opp1500: opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <970000 970000 1100000>;
};
opp1600: opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <990000 990000 1100000>;
opp-suspend;
};
opp1700: opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <1010000 1010000 1100000>;
};
opp1800: opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1030000 1030000 1100000>;
};
opp1900: opp-1900000000 {
opp-hz = /bits/ 64 <1900000000>;
opp-microvolt = <1050000 1050000 1100000>;
};
};
};
&cpu0 {
operating-points-v2 = <&cpu_opps>;
#cooling-cells = <2>;
};
&cpu1 {
operating-points-v2 = <&cpu_opps>;
#cooling-cells = <2>;
};
&cpu2 {
operating-points-v2 = <&cpu_opps>;
#cooling-cells = <2>;
};
&cpu3 {
operating-points-v2 = <&cpu_opps>;
#cooling-cells = <2>;
};