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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/arch/riscv/boot/dts/microchip/Makefile
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# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MICROCHIP) += mpfs-beaglev-fire.dtb
dtb-$(CONFIG_ARCH_MICROCHIP) += mpfs-disco-kit.dtb
dtb-$(CONFIG_ARCH_MICROCHIP) += mpfs-icicle-kit.dtb
dtb-$(CONFIG_ARCH_MICROCHIP) += mpfs-icicle-kit-prod.dtb
dtb-$(CONFIG_ARCH_MICROCHIP) += mpfs-m100pfsevp.dtb
dtb-$(CONFIG_ARCH_MICROCHIP) += mpfs-polarberry.dtb
dtb-$(CONFIG_ARCH_MICROCHIP) += mpfs-sev-kit.dtb
dtb-$(CONFIG_ARCH_MICROCHIP) += mpfs-tysom-m.dtb
dtb-$(CONFIG_ARCH_MICROCHIP) += pic64gx-curiosity-kit.dtb
linux-7.2.3/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/ {
fabric_clk3: fabric-clk3 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
};
fabric_clk1: fabric-clk1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
fabric-bus@40000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>, /* FIC3-FAB */
<0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>, /* FIC0, LO */
<0x0 0xe0000000 0x0 0xe0000000 0x0 0x20000000>, /* FIC1, LO */
<0x20 0x0 0x20 0x0 0x10 0x0>, /* FIC0,HI */
<0x30 0x0 0x30 0x0 0x10 0x0>; /* FIC1,HI */
cape_gpios_p8: gpio@41100000 {
compatible = "microchip,coregpio-rtl-v3";
reg = <0x0 0x41100000 0x0 0x1000>;
clocks = <&fabric_clk3>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <16>;
gpio-line-names = "P8_PIN31", "P8_PIN32", "P8_PIN33", "P8_PIN34",
"P8_PIN35", "P8_PIN36", "P8_PIN37", "P8_PIN38",
"P8_PIN39", "P8_PIN40", "P8_PIN41", "P8_PIN42",
"P8_PIN43", "P8_PIN44", "P8_PIN45", "P8_PIN46";
};
cape_gpios_p9: gpio@41200000 {
compatible = "microchip,coregpio-rtl-v3";
reg = <0x0 0x41200000 0x0 0x1000>;
clocks = <&fabric_clk3>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <20>;
gpio-line-names = "P9_PIN11", "P9_PIN12", "P9_PIN13", "P9_PIN14",
"P9_PIN15", "P9_PIN16", "P9_PIN17", "P9_PIN18",
"P9_PIN21", "P9_PIN22", "P9_PIN23", "P9_PIN24",
"P9_PIN25", "P9_PIN26", "P9_PIN27", "P9_PIN28",
"P9_PIN29", "P9_PIN31", "P9_PIN41", "P9_PIN42";
};
hsi_gpios: gpio@44000000 {
compatible = "microchip,coregpio-rtl-v3";
reg = <0x0 0x44000000 0x0 0x1000>;
clocks = <&fabric_clk3>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <20>;
gpio-line-names = "B0_HSIO70N", "B0_HSIO71N", "B0_HSIO83N",
"B0_HSIO73N_C2P_CLKN", "B0_HSIO70P", "B0_HSIO71P",
"B0_HSIO83P", "B0_HSIO73N_C2P_CLKP", "XCVR1_RX_VALID",
"XCVR1_LOCK", "XCVR1_ERROR", "XCVR2_RX_VALID",
"XCVR2_LOCK", "XCVR2_ERROR", "XCVR3_RX_VALID",
"XCVR3_LOCK", "XCVR3_ERROR", "XCVR_0B_REF_CLK_PLL_LOCK",
"XCVR_0C_REF_CLK_PLL_LOCK", "B0_HSIO81N";
};
};
refclk_ccc: cccrefclk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
};
&ccc_nw {
clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
<&refclk_ccc>, <&refclk_ccc>;
clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
"dll0_ref", "dll1_ref";
status = "okay";
};
linux-7.2.3/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020-2021 Microchip Technology Inc */
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "mpfs.dtsi"
#include "mpfs-beaglev-fire-fabric.dtsi"
/* Clock frequency (in Hz) of MTIMER */
#define MTIMER_FREQ 1000000
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "BeagleBoard BeagleV-Fire";
compatible = "beagle,beaglev-fire", "microchip,mpfs";
aliases {
serial0 = &mmuart0;
serial1 = &mmuart1;
serial2 = &mmuart2;
serial3 = &mmuart3;
serial4 = &mmuart4;
};
chosen {
stdout-path = "serial0:115200n8";
};
cpus {
timebase-frequency = <MTIMER_FREQ>;
};
ddrc_cache_lo: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
status = "okay";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hss: hss-buffer@103fc00000 {
compatible = "shared-dma-pool";
reg = <0x10 0x3fc00000 0x0 0x400000>;
no-map;
};
};
imx219_clk: camera-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
imx219_vana: fixedregulator-0 {
compatible = "regulator-fixed";
regulator-name = "imx219_vana";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
imx219_vdig: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "imx219_vdig";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
imx219_vddl: regulator-1v2 {
compatible = "regulator-fixed";
regulator-name = "imx219_vddl";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
regulator-1v8-syzygy {
compatible = "regulator-fixed";
gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
regulator-name = "syzygy_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
enable-active-high;
};
};
&gpio0 {
interrupts = <13>, <14>, <15>, <16>,
<17>, <18>, <19>, <20>,
<21>, <22>, <23>, <24>,
<25>, <26>;
ngpios = <14>;
gpio-line-names = "", "", "", "", "", "", "",
"", "", "", "", "", "SD_CARD_CS", "USER_BUTTON";
status = "okay";
};
&gpio1 {
interrupts = <27>, <28>, <29>, <30>,
<31>, <32>, <33>, <34>,
<35>, <36>, <37>, <38>,
<39>, <40>, <41>, <42>,
<43>, <44>, <45>, <46>,
<47>, <48>, <49>, <50>;
ngpios = <24>;
gpio-line-names = "", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
"ADC_IRQn", "", "", "USB_OCn";
status = "okay";
};
&gpio2 {
interrupts = <53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>;
ngpios = <32>;
gpio-line-names = "P8_PIN3_USER_LED_0", "P8_PIN4_USER_LED_1", "P8_PIN5_USER_LED_2",
"P8_PIN6_USER_LED_3", "P8_PIN7_USER_LED_4", "P8_PIN8_USER_LED_5",
"P8_PIN9_USER_LED_6", "P8_PIN10_USER_LED_7", "P8_PIN11_USER_LED_8",
"P8_PIN12_USER_LED_9", "P8_PIN13_USER_LED_10", "P8_PIN14_USER_LED_11",
"P8_PIN15", "P8_PIN16", "P8_PIN17", "P8_PIN18", "P8_PIN19", "P8_PIN20",
"P8_PIN21", "P8_PIN22", "P8_PIN23", "P8_PIN24", "P8_PIN25", "P8_PIN26",
"P8_PIN27", "P8_PIN28", "P8_PIN29", "P8_PIN30", "M2_W_DISABLE1",
"M2_W_DISABLE2", "VIO_ENABLE", "SD_DET";
status = "okay";
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
eeprom: eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
};
imx219: sensor@10 {
compatible = "sony,imx219";
reg = <0x10>;
clocks = <&imx219_clk>;
VANA-supply = <&imx219_vana>; /* 2.8v */
VDIG-supply = <&imx219_vdig>; /* 1.8v */
VDDL-supply = <&imx219_vddl>; /* 1.2v */
port {
imx219_0: endpoint {
data-lanes = <1 2>;
clock-noncontinuous;
link-frequencies = /bits/ 64 <456000000>;
};
};
};
};
&irqmux {
interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>,
<3 &plic 16>, <4 &plic 17>, <5 &plic 18>,
<6 &plic 19>, <7 &plic 20>, <8 &plic 21>,
<9 &plic 22>, <10 &plic 23>, <11 &plic 24>,
<12 &plic 25>, <13 &plic 26>,
<32 &plic 27>, <33 &plic 28>, <34 &plic 29>,
<35 &plic 30>, <36 &plic 31>, <37 &plic 32>,
<38 &plic 33>, <39 &plic 34>, <40 &plic 35>,
<41 &plic 36>, <42 &plic 37>, <43 &plic 38>,
<44 &plic 39>, <45 &plic 40>, <46 &plic 41>,
<47 &plic 42>, <48 &plic 43>, <49 &plic 44>,
<50 &plic 45>, <51 &plic 46>, <52 &plic 47>,
<53 &plic 48>, <54 &plic 49>, <55 &plic 50>,
<64 &plic 53>, <65 &plic 53>, <66 &plic 53>,
<67 &plic 53>, <68 &plic 53>, <69 &plic 53>,
<70 &plic 53>, <71 &plic 53>, <72 &plic 53>,
<73 &plic 53>, <74 &plic 53>, <75 &plic 53>,
<76 &plic 53>, <77 &plic 53>, <78 &plic 53>,
<79 &plic 53>, <80 &plic 53>, <81 &plic 53>,
<82 &plic 53>, <83 &plic 53>, <84 &plic 53>,
<85 &plic 53>, <86 &plic 53>, <87 &plic 53>,
<88 &plic 53>, <89 &plic 53>, <90 &plic 53>,
<91 &plic 53>, <92 &plic 53>, <93 &plic 53>,
<94 &plic 53>, <95 &plic 53>;
};
&mac0 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&phy0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};
&mbox {
status = "okay";
};
&mmc {
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&mmuart0 {
status = "okay";
};
&mmuart1 {
status = "okay";
};
&refclk {
clock-frequency = <125000000>;
};
&refclk_ccc {
clock-frequency = <50000000>;
};
&rtc {
status = "okay";
};
&spi0 {
status = "okay";
};
&spi1 {
status = "okay";
};
&qspi {
status = "okay";
cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>, <&gpio0 12 GPIO_ACTIVE_LOW>;
num-cs = <2>;
adc@0 {
compatible = "microchip,mcp3464r";
reg = <0>; /* CE0 */
spi-cpol;
spi-cpha;
spi-max-frequency = <5000000>;
microchip,hw-device-address = <1>;
interrupts-extended = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
channel@0 {
/* CH0 to AGND */
reg = <0>;
label = "CH0";
};
channel@1 {
/* CH1 to AGND */
reg = <1>;
label = "CH1";
};
channel@2 {
/* CH2 to AGND */
reg = <2>;
label = "CH2";
};
channel@3 {
/* CH3 to AGND */
reg = <3>;
label = "CH3";
};
channel@4 {
/* CH4 to AGND */
reg = <4>;
label = "CH4";
};
channel@5 {
/* CH5 to AGND */
reg = <5>;
label = "CH5";
};
channel@6 {
/* CH6 to AGND */
reg = <6>;
label = "CH6";
};
channel@7 {
/* CH7 is connected to AGND */
reg = <7>;
label = "CH7";
};
};
mmc@1 {
compatible = "mmc-spi-slot";
reg = <1>;
cd-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>;
voltage-ranges = <3300 3300>;
spi-max-frequency = <5000000>;
disable-wp;
};
};
&syscontroller {
microchip,bitstream-flash = <&sys_ctrl_flash>;
};
&syscontroller_qspi {
status = "okay";
sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
spi-rx-bus-width = <1>;
reg = <0>;
};
};
&usb {
status = "okay";
dr_mode = "otg";
};
linux-7.2.3/arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020-2025 Microchip Technology Inc */
/ {
core_pwm0: pwm@40000000 {
compatible = "microchip,corepwm-rtl-v4";
reg = <0x0 0x40000000 0x0 0xF0>;
microchip,sync-update-mask = /bits/ 32 <0>;
#pwm-cells = <3>;
clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>;
status = "disabled";
};
i2c2: i2c@40000200 {
compatible = "microchip,corei2c-rtl-v7";
reg = <0x0 0x40000200 0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>;
interrupt-parent = <&plic>;
interrupts = <122>;
clock-frequency = <100000>;
status = "disabled";
};
ihc: mailbox {
compatible = "microchip,sbi-ipc";
interrupt-parent = <&plic>;
interrupts = <180>, <179>, <178>, <177>;
interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
#mbox-cells = <1>;
status = "disabled";
};
mailbox@50000000 {
compatible = "microchip,miv-ihc-rtl-v2";
reg = <0x0 0x50000000 0x0 0x1c000>;
interrupt-parent = <&plic>;
interrupts = <180>, <179>, <178>, <177>;
interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
#mbox-cells = <1>;
microchip,ihc-chan-disabled-mask = /bits/ 16 <0>;
status = "disabled";
};
refclk_ccc: clock-cccref {
compatible = "fixed-clock";
#clock-cells = <0>;
};
};
&ccc_sw {
clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
<&refclk_ccc>, <&refclk_ccc>;
clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
"dll0_ref", "dll1_ref";
status = "okay";
};
linux-7.2.3/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020-2025 Microchip Technology Inc */
/dts-v1/;
#include "mpfs.dtsi"
#include "mpfs-disco-kit-fabric.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/ {
model = "Microchip PolarFire-SoC Discovery Kit";
compatible = "microchip,mpfs-disco-kit-reference-rtl-v2507",
"microchip,mpfs-disco-kit",
"microchip,mpfs";
aliases {
ethernet0 = &mac0;
serial4 = &mmuart4;
};
chosen {
stdout-path = "serial4:115200n8";
};
leds {
compatible = "gpio-leds";
led-1 {
gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
label = "led1";
};
led-2 {
gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
label = "led2";
};
led-3 {
gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
label = "led3";
};
led-4 {
gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
label = "led4";
};
led-5 {
gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
label = "led5";
};
led-6 {
gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
label = "led6";
};
led-7 {
gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
label = "led7";
};
led-8 {
gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
label = "led8";
};
};
ddrc_cache_lo: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hss_payload: region@bfc00000 {
reg = <0x0 0xbfc00000 0x0 0x400000>;
no-map;
};
};
};
&core_pwm0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&i2c0 {
status = "okay";
};
&i2c2 {
status = "okay";
};
&ihc {
status = "okay";
};
&irqmux {
interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>,
<3 &plic 16>, <4 &plic 17>, <5 &plic 18>,
<6 &plic 19>, <7 &plic 20>, <8 &plic 21>,
<9 &plic 22>, <10 &plic 23>, <11 &plic 24>,
<12 &plic 25>, <13 &plic 26>,
<32 &plic 27>, <33 &plic 28>, <34 &plic 29>,
<35 &plic 30>, <36 &plic 31>, <37 &plic 32>,
<38 &plic 33>, <39 &plic 34>, <40 &plic 35>,
<41 &plic 36>, <42 &plic 37>, <43 &plic 38>,
<44 &plic 39>, <45 &plic 40>, <46 &plic 41>,
<47 &plic 42>, <48 &plic 43>, <49 &plic 44>,
<50 &plic 45>, <51 &plic 46>, <52 &plic 47>,
<53 &plic 48>, <54 &plic 49>, <55 &plic 50>,
<64 &plic 53>, <65 &plic 53>, <66 &plic 53>,
<67 &plic 53>, <68 &plic 53>, <69 &plic 53>,
<70 &plic 53>, <71 &plic 53>, <72 &plic 53>,
<73 &plic 53>, <74 &plic 53>, <75 &plic 53>,
<76 &plic 53>, <77 &plic 53>, <78 &plic 53>,
<79 &plic 53>, <80 &plic 53>, <81 &plic 53>,
<82 &plic 53>, <83 &plic 53>, <84 &plic 53>,
<85 &plic 53>, <86 &plic 53>, <87 &plic 53>,
<88 &plic 53>, <89 &plic 53>, <90 &plic 53>,
<91 &plic 53>, <92 &plic 53>, <93 &plic 53>,
<94 &plic 53>, <95 &plic 53>;
};
&mac0 {
phy-mode = "sgmii";
phy-handle = <&phy0>;
status = "okay";
phy0: ethernet-phy@b {
reg = <0xb>;
};
};
&mbox {
status = "okay";
};
&mmc {
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-mmc-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
no-1-8-v;
status = "okay";
};
&mmuart1 {
status = "okay";
};
&mmuart4 {
status = "okay";
};
&refclk {
clock-frequency = <125000000>;
};
&refclk_ccc {
clock-frequency = <50000000>;
};
&rtc {
status = "okay";
};
&spi0 {
status = "okay";
};
&spi1 {
status = "okay";
};
linux-7.2.3/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2025 Microchip Technology Inc */
/dts-v1/;
#include "mpfs-icicle-kit-fabric.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/ {
aliases {
ethernet0 = &mac1;
serial0 = &mmuart0;
serial1 = &mmuart1;
serial2 = &mmuart2;
serial3 = &mmuart3;
serial4 = &mmuart4;
};
chosen {
stdout-path = "serial1:115200n8";
};
leds {
compatible = "gpio-leds";
led-1 {
gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
label = "led1";
};
led-2 {
gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
label = "led2";
};
led-3 {
gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
label = "led3";
};
led-4 {
gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
label = "led4";
};
};
ddrc_cache_lo: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
};
ddrc_cache_hi: memory@1040000000 {
device_type = "memory";
reg = <0x10 0x40000000 0x0 0x40000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hss_payload: region@bfc00000 {
reg = <0x0 0xbfc00000 0x0 0x400000>;
no-map;
};
};
};
&core_pwm0 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
power-monitor@10 {
compatible = "microchip,pac1934";
reg = <0x10>;
#address-cells = <1>;
#size-cells = <0>;
channel@1 {
reg = <0x1>;
shunt-resistor-micro-ohms = <10000>;
label = "VDDREG";
};
channel@2 {
reg = <0x2>;
shunt-resistor-micro-ohms = <10000>;
label = "VDDA25";
};
channel@3 {
reg = <0x3>;
shunt-resistor-micro-ohms = <10000>;
label = "VDD25";
};
channel@4 {
reg = <0x4>;
shunt-resistor-micro-ohms = <10000>;
label = "VDDA_REG";
};
};
};
&i2c2 {
status = "okay";
};
&ihc {
status = "okay";
};
&irqmux {
interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>,
<3 &plic 16>, <4 &plic 17>, <5 &plic 18>,
<6 &plic 19>, <7 &plic 20>, <8 &plic 21>,
<9 &plic 22>, <10 &plic 23>, <11 &plic 24>,
<12 &plic 25>, <13 &plic 26>,
<32 &plic 27>, <33 &plic 28>, <34 &plic 29>,
<35 &plic 30>, <36 &plic 31>, <37 &plic 32>,
<38 &plic 33>, <39 &plic 34>, <40 &plic 35>,
<41 &plic 36>, <42 &plic 37>, <43 &plic 38>,
<44 &plic 39>, <45 &plic 40>, <46 &plic 41>,
<47 &plic 42>, <48 &plic 43>, <49 &plic 44>,
<50 &plic 45>, <51 &plic 46>, <52 &plic 47>,
<53 &plic 48>, <54 &plic 49>, <55 &plic 50>,
<64 &plic 53>, <65 &plic 53>, <66 &plic 53>,
<67 &plic 53>, <68 &plic 53>, <69 &plic 53>,
<70 &plic 53>, <71 &plic 53>, <72 &plic 53>,
<73 &plic 53>, <74 &plic 53>, <75 &plic 53>,
<76 &plic 53>, <77 &plic 53>, <78 &plic 53>,
<79 &plic 53>, <80 &plic 53>, <81 &plic 53>,
<82 &plic 53>, <83 &plic 53>, <84 &plic 53>,
<85 &plic 53>, <86 &plic 53>, <87 &plic 53>,
<88 &plic 53>, <89 &plic 53>, <90 &plic 53>,
<91 &plic 53>, <92 &plic 53>, <93 &plic 53>,
<94 &plic 53>, <95 &plic 53>;
};
&mac0 {
phy-mode = "sgmii";
phy-handle = <&phy0>;
status = "okay";
};
&mac1 {
phy-mode = "sgmii";
phy-handle = <&phy1>;
status = "okay";
phy1: ethernet-phy@9 {
reg = <9>;
};
phy0: ethernet-phy@8 {
reg = <8>;
};
};
&mbox {
status = "okay";
};
&mmc {
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&mmuart1 {
status = "okay";
};
&mmuart2 {
status = "okay";
};
&mmuart3 {
status = "okay";
};
&mmuart4 {
status = "okay";
};
&pcie {
status = "okay";
};
&qspi {
status = "okay";
};
&refclk {
clock-frequency = <125000000>;
};
&refclk_ccc {
clock-frequency = <50000000>;
};
&rtc {
status = "okay";
};
&spi0 {
status = "okay";
};
&spi1 {
status = "okay";
};
&syscontroller_qspi {
/*
* The flash *is* there, but Icicle kits that have engineering sample
* silicon (write?) access to this flash to non-functional. The system
* controller itself can actually access it, but the MSS cannot write
* an image there. Instantiating a coreQSPI in the fabric & connecting
* it to the flash instead should work though. Pre-production or later
* silicon does not have this issue.
*/
status = "disabled";
sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <20000000>;
spi-rx-bus-width = <1>;
reg = <0>;
};
};
&usb {
status = "okay";
dr_mode = "host";
};
linux-7.2.3/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020-2021 Microchip Technology Inc */
#include "mpfs.dtsi"
#include "mpfs-pinctrl.dtsi"
/ {
core_pwm0: pwm@40000000 {
compatible = "microchip,corepwm-rtl-v4";
reg = <0x0 0x40000000 0x0 0xF0>;
microchip,sync-update-mask = /bits/ 32 <0>;
#pwm-cells = <3>;
clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>;
status = "disabled";
};
i2c2: i2c@40000200 {
compatible = "microchip,corei2c-rtl-v7";
reg = <0x0 0x40000200 0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>;
interrupt-parent = <&plic>;
interrupts = <122>;
clock-frequency = <100000>;
status = "disabled";
};
ihc: mailbox {
compatible = "microchip,sbi-ipc";
interrupt-parent = <&plic>;
interrupts = <180>, <179>, <178>, <177>;
interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
#mbox-cells = <1>;
status = "disabled";
};
mailbox@50000000 {
compatible = "microchip,miv-ihc-rtl-v2";
reg = <0x0 0x50000000 0x0 0x1c000>;
interrupt-parent = <&plic>;
interrupts = <180>, <179>, <178>, <177>;
interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
#mbox-cells = <1>;
microchip,ihc-chan-disabled-mask = /bits/ 16 <0>;
status = "disabled";
};
pcie: pcie@3000000000 {
compatible = "microchip,pcie-host-1.0";
#address-cells = <0x3>;
#interrupt-cells = <0x1>;
#size-cells = <0x2>;
device_type = "pci";
reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>,
<0x0 0x4300a000 0x0 0x2000>;
reg-names = "cfg", "bridge", "ctrl";
bus-range = <0x0 0x7f>;
interrupt-parent = <&plic>;
interrupts = <119>;
interrupt-map = <0 0 0 1 &pcie_intc 0>,
<0 0 0 2 &pcie_intc 1>,
<0 0 0 3 &pcie_intc 2>,
<0 0 0 4 &pcie_intc 3>;
interrupt-map-mask = <0 0 0 7>;
clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>;
clock-names = "fic1", "fic3";
ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>;
dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;
msi-parent = <&pcie>;
msi-controller;
status = "disabled";
pcie_intc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
refclk_ccc: clock-cccref {
compatible = "fixed-clock";
#clock-cells = <0>;
};
};
&can0 {
pinctrl-names = "default";
pinctrl-0 = <&can0_fabric>;
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&ikrd_can1_cfg>;
};
&ccc_nw {
clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
<&refclk_ccc>, <&refclk_ccc>;
clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
"dll0_ref", "dll1_ref";
status = "okay";
};
&mmuart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_fabric>;
};
&mmuart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_fabric>;
};
&mmuart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_fabric>;
};
&mmuart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_fabric>;
};
&mssio {
pinctrl-names = "default";
pinctrl-0 = <&spi1_mssio>, <&can1_mssio>, <&mdio0_mssio>, <&mdio1_mssio>;
};
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&qspi_fabric>;
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_fabric>;
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&ikrd_spi1_cfg>;
};
linux-7.2.3/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2025 Microchip Technology Inc */
/dts-v1/;
#include "mpfs-icicle-kit-common.dtsi"
/ {
model = "Microchip PolarFire-SoC Icicle Kit (Production Silicon)";
compatible = "microchip,mpfs-icicle-prod-reference-rtl-v2507",
"microchip,mpfs-icicle-kit-prod",
"microchip,mpfs-icicle-kit",
"microchip,mpfs-prod",
"microchip,mpfs";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_fabric>;
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_mssio>;
};
&syscontroller {
microchip,bitstream-flash = <&sys_ctrl_flash>;
};
&syscontroller_qspi {
status = "okay";
};
linux-7.2.3/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020-2021 Microchip Technology Inc */
/dts-v1/;
#include "mpfs-icicle-kit-common.dtsi"
/ {
model = "Microchip PolarFire-SoC Icicle Kit";
compatible = "microchip,mpfs-icicle-es-reference-rtl-v2507",
"microchip,mpfs-icicle-kit",
"microchip,mpfs";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_fabric>;
};
/*
* Due to silicon errata, routing via MSS IOs doesn't work on ES devices.
* Instead, i2c1, appearing on B1/C1, which are normally MSS IOs, is routed
* via the fabric and back to B1/C1 via "fabric-test" functionality.
* This is done silently by Libero, so the iomux0 setting for i2c1 has to
* be fabric IO, despite tooling etc saying that MSS IOs are used.
*
* See Section 3.3 of https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/Errata/polarfiresoc/microsemi_polarfire_soc_fpga_egineering_samples_errata_er0219_v1.pdf
*/
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_fabric>;
};
linux-7.2.3/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2022 Microchip Technology Inc */
/ {
fabric_clk3: fabric-clk3 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <62500000>;
};
fabric_clk1: fabric-clk1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
pcie: pcie@2000000000 {
compatible = "microchip,pcie-host-1.0";
#address-cells = <0x3>;
#interrupt-cells = <0x1>;
#size-cells = <0x2>;
device_type = "pci";
reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>,
<0x0 0x4300a000 0x0 0x2000>;
reg-names = "cfg", "bridge", "ctrl";
bus-range = <0x0 0x7f>;
interrupt-parent = <&plic>;
interrupts = <119>;
interrupt-map = <0 0 0 1 &pcie_intc 0>,
<0 0 0 2 &pcie_intc 1>,
<0 0 0 3 &pcie_intc 2>,
<0 0 0 4 &pcie_intc 3>;
interrupt-map-mask = <0 0 0 7>;
clocks = <&fabric_clk1>, <&fabric_clk3>;
clock-names = "fic0", "fic3";
ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
msi-parent = <&pcie>;
msi-controller;
status = "disabled";
pcie_intc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
};
linux-7.2.3/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Original all-in-one devicetree:
* Copyright (C) 2021-2022 - Wolfgang Grandegger <wg@aries-embedded.de>
* Rewritten to use includes:
* Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com>
*/
/dts-v1/;
#include "mpfs.dtsi"
#include "mpfs-m100pfs-fabric.dtsi"
/ {
model = "Aries Embedded M100PFEVPS";
compatible = "aries,m100pfsevp", "microchip,mpfs";
aliases {
ethernet0 = &mac0;
ethernet1 = &mac1;
serial0 = &mmuart0;
serial1 = &mmuart1;
serial2 = &mmuart2;
serial3 = &mmuart3;
serial4 = &mmuart4;
gpio0 = &gpio0;
gpio1 = &gpio2;
};
chosen {
stdout-path = "serial1:115200n8";
};
ddrc_cache_lo: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
};
ddrc_cache_hi: memory@1040000000 {
device_type = "memory";
reg = <0x10 0x40000000 0x0 0x40000000>;
};
};
&can0 {
status = "okay";
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
&irqmux {
interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>,
<3 &plic 16>, <4 &plic 17>, <5 &plic 18>,
<6 &plic 19>, <7 &plic 20>, <8 &plic 21>,
<9 &plic 22>, <10 &plic 23>, <11 &plic 24>,
<12 &plic 25>, <13 &plic 26>,
<32 &plic 27>, <33 &plic 28>, <34 &plic 29>,
<35 &plic 30>, <36 &plic 31>, <37 &plic 32>,
<38 &plic 33>, <39 &plic 34>, <40 &plic 35>,
<41 &plic 36>, <42 &plic 37>, <43 &plic 38>,
<44 &plic 39>, <45 &plic 40>, <46 &plic 41>,
<47 &plic 42>, <48 &plic 43>, <49 &plic 44>,
<50 &plic 45>, <51 &plic 46>, <52 &plic 47>,
<53 &plic 48>, <54 &plic 49>, <55 &plic 50>,
<64 &plic 53>, <65 &plic 53>, <66 &plic 53>,
<67 &plic 53>, <68 &plic 53>, <69 &plic 53>,
<70 &plic 53>, <71 &plic 53>, <72 &plic 53>,
<73 &plic 53>, <74 &plic 53>, <75 &plic 53>,
<76 &plic 53>, <77 &plic 53>, <78 &plic 53>,
<79 &plic 53>, <80 &plic 53>, <81 &plic 53>,
<82 &plic 53>, <83 &plic 53>, <84 &plic 53>,
<85 &plic 53>, <86 &plic 53>, <87 &plic 53>,
<88 &plic 53>, <89 &plic 53>, <90 &plic 53>,
<91 &plic 53>, <92 &plic 53>, <93 &plic 53>,
<94 &plic 53>, <95 &plic 53>;
};
&gpio0 {
ngpios = <14>;
status = "okay";
pmic-irq-hog {
gpio-hog;
gpios = <13 0>;
input;
};
/* Set to low for eMMC, high for SD-card */
mmc-sel-hog {
gpio-hog;
gpios = <12 0>;
output-high;
};
};
&gpio2 {
status = "okay";
};
&mac0 {
status = "okay";
phy-mode = "gmii";
phy-handle = <&phy0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};
&mac1 {
status = "okay";
phy-mode = "gmii";
phy-handle = <&phy1>;
phy1: ethernet-phy@0 {
reg = <0>;
};
};
&mbox {
status = "okay";
};
&mmc {
max-frequency = <50000000>;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
no-1-8-v;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
disable-wp;
status = "okay";
};
&mmuart1 {
status = "okay";
};
&mmuart2 {
status = "okay";
};
&mmuart3 {
status = "okay";
};
&mmuart4 {
status = "okay";
};
&pcie {
status = "okay";
};
&qspi {
status = "okay";
};
&refclk {
clock-frequency = <125000000>;
};
&rtc {
status = "okay";
};
&spi0 {
status = "okay";
};
&spi1 {
status = "okay";
};
&usb {
status = "okay";
dr_mode = "host";
};
linux-7.2.3/arch/riscv/boot/dts/microchip/mpfs-pinctrl.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
&iomux0 {
spi0_fabric: mux-spi0-fabric {
function = "spi0";
groups = "spi0_fabric";
};
spi0_mssio: mux-spi0-mssio {
function = "spi0";
groups = "spi0_mssio";
};
spi1_fabric: mux-spi1-fabric {
function = "spi1";
groups = "spi1_fabric";
};
spi1_mssio: mux-spi1-mssio {
function = "spi1";
groups = "spi1_mssio";
};
i2c0_fabric: mux-i2c0-fabric {
function = "i2c0";
groups = "i2c0_fabric";
};
i2c0_mssio: mux-i2c0-mssio {
function = "i2c0";
groups = "i2c0_mssio";
};
i2c1_fabric: mux-i2c1-fabric {
function = "i2c1";
groups = "i2c1_fabric";
};
i2c1_mssio: mux-i2c1-mssio {
function = "i2c1";
groups = "i2c1_mssio";
};
can0_fabric: mux-can0-fabric {
function = "can0";
groups = "can0_fabric";
};
can0_mssio: mux-can0-mssio {
function = "can0";
groups = "can0_mssio";
};
can1_fabric: mux-can1-fabric {
function = "can1";
groups = "can1_fabric";
};
can1_mssio: mux-can1-mssio {
function = "can1";
groups = "can1_mssio";
};
qspi_fabric: mux-qspi-fabric {
function = "qspi";
groups = "qspi_fabric";
};
qspi_mssio: mux-qspi-mssio {
function = "qspi";
groups = "qspi_mssio";
};
uart0_fabric: mux-uart0-fabric {
function = "uart0";
groups = "uart0_fabric";
};
uart0_mssio: mux-uart0-mssio {
function = "uart0";
groups = "uart0_mssio";
};
uart1_fabric: mux-uart1-fabric {
function = "uart1";
groups = "uart1_fabric";
};
uart1_mssio: mux-uart1-mssio {
function = "uart1";
groups = "uart1_mssio";
};
uart2_fabric: mux-uart2-fabric {
function = "uart2";
groups = "uart2_fabric";
};
uart2_mssio: mux-uart2-mssio {
function = "uart2";
groups = "uart2_mssio";
};
uart3_fabric: mux-uart3-fabric {
function = "uart3";
groups = "uart3_fabric";
};
uart3_mssio: mux-uart3-mssio {
function = "uart3";
groups = "uart3_mssio";
};
uart4_fabric: mux-uart4-fabric {
function = "uart4";
groups = "uart4_fabric";
};
uart4_mssio: mux-uart4-mssio {
function = "uart4";
groups = "uart4_mssio";
};
mdio0_fabric: mux-mdio0-fabric {
function = "mdio0";
groups = "mdio0_fabric";
};
mdio0_mssio: mux-mdio0-mssio {
function = "mdio0";
groups = "mdio0_mssio";
};
mdio1_fabric: mux-mdio1-fabric {
function = "mdio1";
groups = "mdio1_fabric";
};
mdio1_mssio: mux-mdio1-mssio {
function = "mdio1";
groups = "mdio1_mssio";
};
};
&mssio {
ikrd_can1_cfg: ikrd-can1-cfg {
can1-pins {
pins = <34>, <35>, <36>;
function = "can";
bias-pull-up;
drive-strength = <8>;
power-source = <3300000>;
microchip,ibufmd = <0x1>;
};
};
ikrd_spi1_cfg: ikrd-spi1-cfg {
spi1-pins {
pins = <30>, <31>, <32>, <33>;
function = "spi";
bias-pull-up;
drive-strength = <8>;
power-source = <3300000>;
microchip,ibufmd = <0x1>;
};
};
};
linux-7.2.3/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020-2022 Microchip Technology Inc */
/ {
fabric_clk3: fabric-clk3 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <62500000>;
};
fabric_clk1: fabric-clk1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
pcie: pcie@2000000000 {
compatible = "microchip,pcie-host-1.0";
#address-cells = <0x3>;
#interrupt-cells = <0x1>;
#size-cells = <0x2>;
device_type = "pci";
reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>,
<0x0 0x4300a000 0x0 0x2000>;
reg-names = "cfg", "bridge", "ctrl";
bus-range = <0x0 0x7f>;
interrupt-parent = <&plic>;
interrupts = <119>;
interrupt-map = <0 0 0 1 &pcie_intc 0>,
<0 0 0 2 &pcie_intc 1>,
<0 0 0 3 &pcie_intc 2>,
<0 0 0 4 &pcie_intc 3>;
interrupt-map-mask = <0 0 0 7>;
clocks = <&fabric_clk1>, <&fabric_clk3>;
clock-names = "fic0", "fic3";
ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
msi-parent = <&pcie>;
msi-controller;
status = "disabled";
pcie_intc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
};
linux-7.2.3/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020-2022 Microchip Technology Inc */
/dts-v1/;
#include "mpfs.dtsi"
#include "mpfs-polarberry-fabric.dtsi"
/ {
model = "Sundance PolarBerry";
compatible = "sundance,polarberry", "microchip,mpfs";
aliases {
ethernet0 = &mac1;
serial0 = &mmuart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
ddrc_cache_lo: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x2e000000>;
};
ddrc_cache_hi: memory@1000000000 {
device_type = "memory";
reg = <0x10 0x00000000 0x0 0xC0000000>;
};
};
&irqmux {
interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>,
<3 &plic 16>, <4 &plic 17>, <5 &plic 18>,
<6 &plic 19>, <7 &plic 20>, <8 &plic 21>,
<9 &plic 22>, <10 &plic 23>, <11 &plic 24>,
<12 &plic 25>, <13 &plic 26>,
<32 &plic 27>, <33 &plic 28>, <34 &plic 29>,
<35 &plic 30>, <36 &plic 31>, <37 &plic 32>,
<38 &plic 33>, <39 &plic 34>, <40 &plic 35>,
<41 &plic 36>, <42 &plic 37>, <43 &plic 38>,
<44 &plic 39>, <45 &plic 40>, <46 &plic 41>,
<47 &plic 42>, <48 &plic 43>, <49 &plic 44>,
<50 &plic 45>, <51 &plic 46>, <52 &plic 47>,
<53 &plic 48>, <54 &plic 49>, <55 &plic 50>,
<64 &plic 53>, <65 &plic 53>, <66 &plic 53>,
<67 &plic 53>, <68 &plic 53>, <69 &plic 53>,
<70 &plic 53>, <71 &plic 53>, <72 &plic 53>,
<73 &plic 53>, <74 &plic 53>, <75 &plic 53>,
<76 &plic 53>, <77 &plic 53>, <78 &plic 53>,
<79 &plic 53>, <80 &plic 53>, <81 &plic 53>,
<82 &plic 53>, <83 &plic 53>, <84 &plic 53>,
<85 &plic 53>, <86 &plic 53>, <87 &plic 53>,
<88 &plic 53>, <89 &plic 53>, <90 &plic 53>,
<91 &plic 53>, <92 &plic 53>, <93 &plic 53>,
<94 &plic 53>, <95 &plic 53>;
};
/*
* phy0 is connected to mac0, but the port itself is on the (optional) carrier
* board.
*/
&mac0 {
phy-mode = "sgmii";
phy-handle = <&phy0>;
status = "disabled";
};
&mac1 {
phy-mode = "sgmii";
phy-handle = <&phy1>;
status = "okay";
phy1: ethernet-phy@5 {
reg = <5>;
};
phy0: ethernet-phy@4 {
reg = <4>;
};
};
&mbox {
status = "okay";
};
&mmc {
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&mmuart0 {
status = "okay";
};
&refclk {
clock-frequency = <125000000>;
};
&rtc {
status = "okay";
};
linux-7.2.3/arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2022 Microchip Technology Inc */
/ {
fabric_clk3: fabric-clk3 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
fabric_clk1: fabric-clk1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
};
linux-7.2.3/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2022 Microchip Technology Inc */
/dts-v1/;
#include "mpfs.dtsi"
#include "mpfs-sev-kit-fabric.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "Microchip PolarFire-SoC SEV Kit";
compatible = "microchip,mpfs-sev-kit", "microchip,mpfs";
aliases {
ethernet0 = &mac1;
serial0 = &mmuart0;
serial1 = &mmuart1;
serial2 = &mmuart2;
serial3 = &mmuart3;
serial4 = &mmuart4;
};
chosen {
stdout-path = "serial1:115200n8";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
fabricbuf0ddrc: buffer@80000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x80000000 0x0 0x2000000>;
};
fabricbuf1ddrnc: buffer@c4000000 {
compatible = "shared-dma-pool";
reg = <0x0 0xc4000000 0x0 0x4000000>;
};
fabricbuf2ddrncwcb: buffer@d4000000 {
compatible = "shared-dma-pool";
reg = <0x0 0xd4000000 0x0 0x4000000>;
};
};
ddrc_cache: memory@1000000000 {
device_type = "memory";
reg = <0x10 0x0 0x0 0x76000000>;
};
};
&i2c0 {
status = "okay";
};
&irqmux {
interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>,
<3 &plic 16>, <4 &plic 17>, <5 &plic 18>,
<6 &plic 19>, <7 &plic 20>, <8 &plic 21>,
<9 &plic 22>, <10 &plic 23>, <11 &plic 24>,
<12 &plic 25>, <13 &plic 26>,
<32 &plic 27>, <33 &plic 28>, <34 &plic 29>,
<35 &plic 30>, <36 &plic 31>, <37 &plic 32>,
<38 &plic 33>, <39 &plic 34>, <40 &plic 35>,
<41 &plic 36>, <42 &plic 37>, <43 &plic 38>,
<44 &plic 39>, <45 &plic 40>, <46 &plic 41>,
<47 &plic 42>, <48 &plic 43>, <49 &plic 44>,
<50 &plic 45>, <51 &plic 46>, <52 &plic 47>,
<53 &plic 48>, <54 &plic 49>, <55 &plic 50>,
<64 &plic 53>, <65 &plic 53>, <66 &plic 53>,
<67 &plic 53>, <68 &plic 53>, <69 &plic 53>,
<70 &plic 53>, <71 &plic 53>, <72 &plic 53>,
<73 &plic 53>, <74 &plic 53>, <75 &plic 53>,
<76 &plic 53>, <77 &plic 53>, <78 &plic 53>,
<79 &plic 53>, <80 &plic 53>, <81 &plic 53>,
<82 &plic 53>, <83 &plic 53>, <84 &plic 53>,
<85 &plic 53>, <86 &plic 53>, <87 &plic 53>,
<88 &plic 53>, <89 &plic 53>, <90 &plic 53>,
<91 &plic 53>, <92 &plic 53>, <93 &plic 53>,
<94 &plic 53>, <95 &plic 53>;
};
&gpio2 {
status = "okay";
};
&mac0 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&phy0>;
phy1: ethernet-phy@9 {
reg = <9>;
};
phy0: ethernet-phy@8 {
reg = <8>;
};
};
&mac1 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&phy1>;
};
&mbox {
status = "okay";
};
&mmc {
status = "okay";
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
};
&mmuart1 {
status = "okay";
};
&mmuart2 {
status = "okay";
};
&mmuart3 {
status = "okay";
};
&mmuart4 {
status = "okay";
};
&refclk {
clock-frequency = <125000000>;
};
&rtc {
status = "okay";
};
&usb {
status = "okay";
dr_mode = "otg";
};
linux-7.2.3/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi
+18
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2022 Microchip Technology Inc */
// #include "dt-bindings/mailbox/miv-ihc.h"
/ {
fabric_clk3: fabric-clk3 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <62500000>;
};
fabric_clk1: fabric-clk1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
};
linux-7.2.3/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
+177
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// SPDX-License-Identifier: GPL-2.0
/*
* Original all-in-one devicetree:
* Copyright (C) 2020-2022 - Aldec
* Rewritten to use includes:
* Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com>
*/
/dts-v1/;
#include "mpfs.dtsi"
#include "mpfs-tysom-m-fabric.dtsi"
/ {
model = "Aldec TySOM-M-MPFS250T-REV2";
compatible = "aldec,tysom-m-mpfs250t-rev2", "microchip,mpfs";
aliases {
ethernet0 = &mac0;
ethernet1 = &mac1;
serial0 = &mmuart0;
serial1 = &mmuart1;
serial2 = &mmuart2;
serial3 = &mmuart3;
serial4 = &mmuart4;
gpio0 = &gpio0;
gpio1 = &gpio2;
};
chosen {
stdout-path = "serial1:115200n8";
};
ddrc_cache_lo: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x30000000>;
status = "okay";
};
ddrc_cache_hi: memory@1000000000 {
device_type = "memory";
reg = <0x10 0x00000000 0x0 0x40000000>;
status = "okay";
};
leds {
compatible = "gpio-leds";
status = "okay";
led0 {
gpios = <&gpio1 23 1>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
};
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
hwmon: hwmon@45 {
status = "okay";
compatible = "ti,ina219";
reg = <0x45>;
shunt-resistor = <2000>;
};
};
&irqmux {
interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>,
<3 &plic 16>, <4 &plic 17>, <5 &plic 18>,
<6 &plic 19>, <7 &plic 20>, <8 &plic 21>,
<9 &plic 22>, <10 &plic 23>, <11 &plic 24>,
<12 &plic 25>, <13 &plic 26>,
<32 &plic 27>, <33 &plic 28>, <34 &plic 29>,
<35 &plic 30>, <36 &plic 31>, <37 &plic 32>,
<38 &plic 33>, <39 &plic 34>, <40 &plic 35>,
<41 &plic 36>, <42 &plic 37>, <43 &plic 38>,
<44 &plic 39>, <45 &plic 40>, <46 &plic 41>,
<47 &plic 42>, <48 &plic 43>, <49 &plic 44>,
<50 &plic 45>, <51 &plic 46>, <52 &plic 47>,
<53 &plic 48>, <54 &plic 49>, <55 &plic 50>,
<64 &plic 53>, <65 &plic 53>, <66 &plic 53>,
<67 &plic 53>, <68 &plic 53>, <69 &plic 53>,
<70 &plic 53>, <71 &plic 53>, <72 &plic 53>,
<73 &plic 53>, <74 &plic 53>, <75 &plic 53>,
<76 &plic 53>, <77 &plic 53>, <78 &plic 53>,
<79 &plic 53>, <80 &plic 53>, <81 &plic 53>,
<82 &plic 53>, <83 &plic 53>, <84 &plic 53>,
<85 &plic 53>, <86 &plic 53>, <87 &plic 53>,
<88 &plic 53>, <89 &plic 53>, <90 &plic 53>,
<91 &plic 53>, <92 &plic 53>, <93 &plic 53>,
<94 &plic 53>, <95 &plic 53>;
};
&gpio1 {
status = "okay";
};
&mac0 {
status = "okay";
phy-mode = "gmii";
phy-handle = <&phy0>;
};
&mac1 {
status = "okay";
phy-mode = "gmii";
phy-handle = <&phy1>;
phy1: ethernet-phy@1 {
reg = <1>;
};
phy0: ethernet-phy@0 {
reg = <0>;
};
};
&mbox {
status = "okay";
};
&mmc {
max-frequency = <200000000>;
cap-mmc-highspeed;
cap-sd-highspeed;
no-1-8-v;
disable-wp;
status = "okay";
};
&mmuart1 {
status = "okay";
};
&mmuart2 {
status = "okay";
};
&mmuart3 {
status = "okay";
};
&mmuart4 {
status = "okay";
};
&refclk {
clock-frequency = <125000000>;
};
&rtc {
status = "okay";
};
&spi0 {
status = "okay";
};
&spi1 {
status = "okay";
flash@0 {
compatible = "micron,n25q128a11", "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <10000000>;
};
};
&usb {
status = "okay";
dr_mode = "host";
};
linux-7.2.3/arch/riscv/boot/dts/microchip/mpfs.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020-2021 Microchip Technology Inc */
/dts-v1/;
#include "dt-bindings/clock/microchip,mpfs-clock.h"
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "Microchip PolarFire SoC";
compatible = "microchip,mpfs";
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <1000000>;
cpu0: cpu@0 {
compatible = "sifive,e51", "sifive,rocket0", "riscv";
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
"zihpm";
clocks = <&clkcfg CLK_CPU>;
status = "disabled";
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu1: cpu@1 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <1>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
next-level-cache = <&cctrllr>;
status = "okay";
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu2: cpu@2 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <2>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
next-level-cache = <&cctrllr>;
status = "okay";
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu3: cpu@3 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <3>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
next-level-cache = <&cctrllr>;
status = "okay";
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu4: cpu@4 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <4>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
next-level-cache = <&cctrllr>;
status = "okay";
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
core4 {
cpu = <&cpu4>;
};
};
};
};
refclk: mssrefclk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
syscontroller: syscontroller {
compatible = "microchip,mpfs-sys-controller";
mboxes = <&mbox 0>;
};
scbclk: mssclkclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <80000000>;
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
cctrllr: cache-controller@2010000 {
compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";
reg = <0x0 0x2010000 0x0 0x1000>;
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <1024>;
cache-size = <2097152>;
cache-unified;
interrupt-parent = <&plic>;
interrupts = <1>, <3>, <4>, <2>;
};
clint: clint@2000000 {
compatible = "sifive,fu540-c000-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0xC000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
<&cpu1_intc 3>, <&cpu1_intc 7>,
<&cpu2_intc 3>, <&cpu2_intc 7>,
<&cpu3_intc 3>, <&cpu3_intc 7>,
<&cpu4_intc 3>, <&cpu4_intc 7>;
};
plic: interrupt-controller@c000000 {
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
interrupts-extended = <&cpu0_intc 11>,
<&cpu1_intc 11>, <&cpu1_intc 9>,
<&cpu2_intc 11>, <&cpu2_intc 9>,
<&cpu3_intc 11>, <&cpu3_intc 9>,
<&cpu4_intc 11>, <&cpu4_intc 9>;
riscv,ndev = <186>;
};
pdma: dma-controller@3000000 {
compatible = "microchip,mpfs-pdma", "sifive,pdma0";
reg = <0x0 0x3000000 0x0 0x8000>;
interrupt-parent = <&plic>;
interrupts = <5 6>, <7 8>, <9 10>, <11 12>;
dma-channels = <4>;
#dma-cells = <1>;
};
mss_top_sysreg: syscon@20002000 {
compatible = "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd";
reg = <0x0 0x20002000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
#reset-cells = <1>;
irqmux: interrupt-controller@54 {
compatible = "microchip,mpfs-irqmux";
reg = <0x54 0x4>;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0x7f>;
};
iomux0: pinctrl@200 {
compatible = "microchip,mpfs-pinctrl-iomux0";
reg = <0x200 0x4>;
pinctrl-use-default;
};
mssio: pinctrl@204 {
compatible = "microchip,mpfs-pinctrl-mssio";
reg = <0x204 0x7c>;
/* on icicle ref design at least */
pinctrl-use-default;
};
};
sysreg_scb: syscon@20003000 {
compatible = "microchip,mpfs-sysreg-scb", "syscon";
reg = <0x0 0x20003000 0x0 0x1000>;
};
ccc_se: clock-controller@38010000 {
compatible = "microchip,mpfs-ccc";
reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>,
<0x0 0x39010000 0x0 0x1000>, <0x0 0x39020000 0x0 0x1000>;
#clock-cells = <1>;
status = "disabled";
};
ccc_ne: clock-controller@38040000 {
compatible = "microchip,mpfs-ccc";
reg = <0x0 0x38040000 0x0 0x1000>, <0x0 0x38080000 0x0 0x1000>,
<0x0 0x39040000 0x0 0x1000>, <0x0 0x39080000 0x0 0x1000>;
#clock-cells = <1>;
status = "disabled";
};
ccc_nw: clock-controller@38100000 {
compatible = "microchip,mpfs-ccc";
reg = <0x0 0x38100000 0x0 0x1000>, <0x0 0x38200000 0x0 0x1000>,
<0x0 0x39100000 0x0 0x1000>, <0x0 0x39200000 0x0 0x1000>;
#clock-cells = <1>;
status = "disabled";
};
ccc_sw: clock-controller@38400000 {
compatible = "microchip,mpfs-ccc";
reg = <0x0 0x38400000 0x0 0x1000>, <0x0 0x38800000 0x0 0x1000>,
<0x0 0x39400000 0x0 0x1000>, <0x0 0x39800000 0x0 0x1000>;
#clock-cells = <1>;
status = "disabled";
};
mmuart0: serial@20000000 {
compatible = "ns16550a";
reg = <0x0 0x20000000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <90>;
current-speed = <115200>;
clocks = <&clkcfg CLK_MMUART0>;
status = "disabled"; /* Reserved for the HSS */
};
mmuart1: serial@20100000 {
compatible = "ns16550a";
reg = <0x0 0x20100000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <91>;
current-speed = <115200>;
clocks = <&clkcfg CLK_MMUART1>;
status = "disabled";
};
mmuart2: serial@20102000 {
compatible = "ns16550a";
reg = <0x0 0x20102000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <92>;
current-speed = <115200>;
clocks = <&clkcfg CLK_MMUART2>;
status = "disabled";
};
mmuart3: serial@20104000 {
compatible = "ns16550a";
reg = <0x0 0x20104000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <93>;
current-speed = <115200>;
clocks = <&clkcfg CLK_MMUART3>;
status = "disabled";
};
mmuart4: serial@20106000 {
compatible = "ns16550a";
reg = <0x0 0x20106000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <94>;
clocks = <&clkcfg CLK_MMUART4>;
current-speed = <115200>;
status = "disabled";
};
/* Common node entry for emmc/sd */
mmc: mmc@20008000 {
compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
reg = <0x0 0x20008000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <88>;
clocks = <&clkcfg CLK_MMC>;
max-frequency = <200000000>;
status = "disabled";
};
spi0: spi@20108000 {
compatible = "microchip,mpfs-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20108000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <54>;
clocks = <&clkcfg CLK_SPI0>;
status = "disabled";
};
spi1: spi@20109000 {
compatible = "microchip,mpfs-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20109000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <55>;
clocks = <&clkcfg CLK_SPI1>;
status = "disabled";
};
qspi: spi@21000000 {
compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x21000000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <85>;
clocks = <&clkcfg CLK_QSPI>;
status = "disabled";
};
i2c0: i2c@2010a000 {
compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
reg = <0x0 0x2010a000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&plic>;
interrupts = <58>;
clocks = <&clkcfg CLK_I2C0>;
clock-frequency = <100000>;
status = "disabled";
};
i2c1: i2c@2010b000 {
compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
reg = <0x0 0x2010b000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&plic>;
interrupts = <61>;
clocks = <&clkcfg CLK_I2C1>;
clock-frequency = <100000>;
status = "disabled";
};
can0: can@2010c000 {
compatible = "microchip,mpfs-can";
reg = <0x0 0x2010c000 0x0 0x1000>;
clocks = <&clkcfg CLK_CAN0>, <&clkcfg CLK_MSSPLL3>;
interrupt-parent = <&plic>;
interrupts = <56>;
resets = <&mss_top_sysreg CLK_CAN0>;
status = "disabled";
};
can1: can@2010d000 {
compatible = "microchip,mpfs-can";
reg = <0x0 0x2010d000 0x0 0x1000>;
clocks = <&clkcfg CLK_CAN1>, <&clkcfg CLK_MSSPLL3>;
interrupt-parent = <&plic>;
interrupts = <57>;
resets = <&mss_top_sysreg CLK_CAN1>;
status = "disabled";
};
mac0: ethernet@20110000 {
compatible = "microchip,mpfs-macb", "cdns,macb";
reg = <0x0 0x20110000 0x0 0x2000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&plic>;
interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>, <&refclk>;
clock-names = "pclk", "hclk", "tsu_clk";
resets = <&mss_top_sysreg CLK_MAC0>;
status = "disabled";
};
mac1: ethernet@20112000 {
compatible = "microchip,mpfs-macb", "cdns,macb";
reg = <0x0 0x20112000 0x0 0x2000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&plic>;
interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>, <&refclk>;
clock-names = "pclk", "hclk", "tsu_clk";
resets = <&mss_top_sysreg CLK_MAC1>;
status = "disabled";
};
gpio0: gpio@20120000 {
compatible = "microchip,mpfs-gpio";
reg = <0x0 0x20120000 0x0 0x1000>;
interrupt-parent = <&irqmux>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0>, <1>, <2>, <3>,
<4>, <5>, <6>, <7>,
<8>, <9>, <10>, <11>,
<12>, <13>;
clocks = <&clkcfg CLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <14>;
status = "disabled";
};
gpio1: gpio@20121000 {
compatible = "microchip,mpfs-gpio";
reg = <0x0 0x20121000 0x0 0x1000>;
interrupt-parent = <&irqmux>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <32>, <33>, <34>, <35>,
<36>, <37>, <38>, <39>,
<40>, <41>, <42>, <43>,
<44>, <45>, <46>, <47>,
<48>, <49>, <50>, <51>,
<52>, <53>, <54>, <55>;
clocks = <&clkcfg CLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
status = "disabled";
};
gpio2: gpio@20122000 {
compatible = "microchip,mpfs-gpio";
reg = <0x0 0x20122000 0x0 0x1000>;
interrupt-parent = <&irqmux>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <64>, <65>, <66>, <67>,
<68>, <69>, <70>, <71>,
<72>, <73>, <74>, <75>,
<76>, <77>, <78>, <79>,
<80>, <81>, <82>, <83>,
<84>, <85>, <86>, <87>,
<88>, <89>, <90>, <91>,
<92>, <93>, <94>, <95>;
clocks = <&clkcfg CLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
status = "disabled";
};
rtc: rtc@20124000 {
compatible = "microchip,mpfs-rtc";
reg = <0x0 0x20124000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <80>, <81>;
clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;
clock-names = "rtc", "rtcref";
status = "disabled";
};
usb: usb@20201000 {
compatible = "microchip,mpfs-musb";
reg = <0x0 0x20201000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <86>, <87>;
clocks = <&clkcfg CLK_USB>;
interrupt-names = "dma","mc";
status = "disabled";
};
control_scb: syscon@37020000 {
compatible = "microchip,mpfs-control-scb", "syscon";
reg = <0x0 0x37020000 0x0 0x100>;
};
mbox: mailbox@37020800 {
compatible = "microchip,mpfs-mailbox";
reg = <0x0 0x37020800 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <96>;
#mbox-cells = <1>;
status = "disabled";
};
syscontroller_qspi: spi@37020100 {
compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x37020100 0x0 0x100>;
interrupt-parent = <&plic>;
interrupts = <110>;
clocks = <&scbclk>;
status = "disabled";
};
clkcfg: clkcfg@3e001000 {
compatible = "microchip,mpfs-clkcfg";
reg = <0x0 0x3e001000 0x0 0x1000>;
clocks = <&refclk>;
#clock-cells = <1>;
};
};
};
linux-7.2.3/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Source for the PIC64GX Curiosity Kit
*
* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
*
* Author: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
*
* The Curiosity-GX10000 (PIC64GX SoC Curiosity Kit) is a compact SoC
* prototyping board featuring a Microchip PIC64GX SoC
* PIC64GX-1000. Features include:
* - 1 GB DDR4 SDRAM
* - Gigabit Ethernet
* - microSD-card slot
*
* https://www.microchip.com/en-us/development-tool/curiosity-pic64gx1000-kit-es
*/
/dts-v1/;
#include "pic64gx.dtsi"
#include "pic64gx-pinctrl.dtsi"
/* Clock frequency (in Hz) of the rtcclk */
#define RTCCLK_FREQ 1000000
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "Microchip PIC64GX Curiosity Kit";
compatible = "microchip,pic64gx-curiosity-kit", "microchip,pic64gx";
aliases {
ethernet0 = &mac0;
serial1 = &mmuart1;
serial2 = &mmuart2;
};
chosen {
stdout-path = "serial1:115200n8";
};
cpus {
timebase-frequency = <RTCCLK_FREQ>;
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hss: hss-buffer@bfc00000 {
compatible = "shared-dma-pool";
reg = <0x0 0xbfc00000 0x0 0x400000>;
no-map;
};
};
};
&gpio0 {
status ="okay";
gpio-line-names =
"", "", "", "", "", "", "", "",
"", "", "", "", "MIPI_CAM_RESET", "MIPI_CAM_STANDBY";
};
&gpio1 {
status ="okay";
gpio-line-names =
"", "", "LED1", "LED2", "LED3", "LED4", "LED5", "LED6",
"LED7", "LED8", "", "", "", "", "", "",
"", "", "", "", "HDMI_HPD", "", "", "GPIO_1_23";
};
&gpio2 {
pinctrl-names = "default";
pinctrl-0 = <&mdio1_gpio>, <&spi0_gpio>, <&can0_gpio>, <&pcie_gpio>,
<&qspi_gpio>, <&uart3_gpio>, <&uart4_gpio>, <&can1_gpio>;
status ="okay";
gpio-line-names =
"", "", "", "", "", "", "SWITCH2", "USR_IO12",
"DIP1", "DIP2", "", "DIP3", "USR_IO1", "USR_IO2", "USR_IO7", "USR_IO8",
"USR_IO3", "USR_IO4", "USR_IO5", "USR_IO6", "", "", "USR_IO9", "USR_IO10",
"DIP4", "USR_IO11", "", "", "SWITCH1", "", "", "";
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
&irqmux {
interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>,
<3 &plic 16>, <4 &plic 17>, <5 &plic 18>,
<6 &plic 19>, <7 &plic 20>, <8 &plic 21>,
<9 &plic 22>, <10 &plic 23>, <11 &plic 24>,
<12 &plic 25>, <13 &plic 26>,
<32 &plic 27>, <33 &plic 28>, <34 &plic 29>,
<35 &plic 30>, <36 &plic 31>, <37 &plic 32>,
<38 &plic 33>, <39 &plic 34>, <40 &plic 35>,
<41 &plic 36>, <42 &plic 37>, <43 &plic 38>,
<44 &plic 39>, <45 &plic 40>, <46 &plic 41>,
<47 &plic 42>, <48 &plic 43>, <49 &plic 44>,
<50 &plic 45>, <51 &plic 46>, <52 &plic 47>,
<53 &plic 48>, <54 &plic 49>, <55 &plic 50>,
<64 &plic 53>, <65 &plic 53>, <66 &plic 53>,
<67 &plic 53>, <68 &plic 53>, <69 &plic 53>,
<70 &plic 53>, <71 &plic 53>, <72 &plic 53>,
<73 &plic 53>, <74 &plic 53>, <75 &plic 53>,
<76 &plic 53>, <77 &plic 53>, <78 &plic 53>,
<79 &plic 53>, <80 &plic 53>, <81 &plic 53>,
<82 &plic 53>, <83 &plic 53>, <84 &plic 53>,
<85 &plic 53>, <86 &plic 53>, <87 &plic 53>,
<88 &plic 53>, <89 &plic 53>, <90 &plic 53>,
<91 &plic 53>, <92 &plic 53>, <93 &plic 53>,
<94 &plic 53>, <95 &plic 53>;
};
&mac0 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&phy0>;
pinctrl-names = "default";
pinctrl-0 = <&mdio0_default>;
phy0: ethernet-phy@b {
reg = <0xb>;
};
};
&mbox {
status = "okay";
};
&mmc {
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-mmc-highspeed;
sdhci-caps-mask = <0x00000007 0x00000000>;
status = "okay";
};
&mmuart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_fio>;
status = "okay";
};
&mmuart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_default>;
status = "okay";
};
&refclk {
clock-frequency = <125000000>;
};
&rtc {
status = "okay";
};
linux-7.2.3/arch/riscv/boot/dts/microchip/pic64gx-pinctrl.dtsi
+177
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
&iomux0 {
spi0_fio: mux-spi0-fabric {
function = "spi0";
groups = "spi0_fabric";
};
spi1_mssio: mux-spi1-mssio {
function = "spi1";
groups = "spi1_mssio";
};
i2c0_mssio: mux-i2c0-mssio {
function = "i2c0";
groups = "i2c0_mssio";
};
i2c1_mssio: mux-i2c1-mssio {
function = "i2c1";
groups = "i2c1_mssio";
};
can0_fio: mux-can0-fabric {
function = "can0";
groups = "can0_fabric";
};
can1_fio: mux-can1-fabric {
function = "can1";
groups = "can1_fabric";
};
qspi_fio: mux-qspi-fabric {
function = "qspi";
groups = "qspi_fabric";
};
uart0_mssio: mux-uart0-mssio {
function = "uart0";
groups = "uart0_mssio";
};
uart1_fio: mux-uart1-fabric {
function = "uart1";
groups = "uart1_fabric";
};
uart2_fio: mux-uart2-fabric {
function = "uart2";
groups = "uart2_fabric";
};
uart3_fio: mux-uart3-fabric {
function = "uart3";
groups = "uart3_fabric";
};
uart4_fio: mux-uart4-fabric {
function = "uart4";
groups = "uart4_fabric";
};
mdio0_fio: mux-mdio0-fabric {
function = "mdio0";
groups = "mdio0_fabric";
};
mdio1_fio: mux-mdio1-fabric {
function = "mdio1";
groups = "mdio1_fabric";
};
};
&gpio2_pinctrl {
//TODO rethink the labels, since a bunch of these are not defaults or
//just outright remove the non-default groups
mdio0_default: mux-mac0 {
function = "mdio0";
groups = "mdio0";
};
mdio0_gpio: mux-mac0-gpio2 {
function = "gpio";
groups = "gpio_mdio0";
};
mdio1_default: mux-mac1 {
function = "mdio1";
groups = "mdio1";
};
mdio1_gpio: mux-mac1-gpio2 {
function = "gpio";
groups = "gpio_mdio1";
};
spi0_default: mux-spi0 {
function = "spi0";
groups = "spi0";
};
spi0_gpio: mux-spi0-gpio2 {
function = "gpio";
groups = "gpio_spi0";
};
can0_default: mux-can0 {
function = "can0";
groups = "can0";
};
can0_gpio: mux-can0-gpio2 {
function = "gpio";
groups = "gpio_can0";
};
pcie_default: mux-pcie {
function = "pcie";
groups = "pcie";
};
pcie_gpio: mux-pcie-gpio2 {
function = "gpio";
groups = "gpio_pcie";
};
qspi_default: mux-qspi {
function = "qspi";
groups = "qspi";
};
qspi_gpio: mux-qspi-gpio2 {
function = "gpio";
groups = "gpio_qspi";
};
uart3_default: mux-uart3 {
function = "uart3";
groups = "uart3";
};
uart3_gpio: mux-uart3-gpio2 {
function = "gpio";
groups = "gpio_uart3";
};
uart4_default: mux-uart4 {
function = "uart4";
groups = "uart4";
};
uart4_gpio: mux-uart4-gpio2 {
function = "gpio";
groups = "gpio_uart4";
};
can1_default: mux-can1 {
function = "can1";
groups = "can1";
};
can1_gpio: mux-can1-gpio2 {
function = "gpio";
groups = "gpio_can1";
};
uart2_default: mux-uart2 {
function = "uart2";
groups = "uart2";
};
uart2_gpio: mux-uart2-gpio2 {
function = "gpio";
groups = "gpio_uart2";
};
};
linux-7.2.3/arch/riscv/boot/dts/microchip/pic64gx.dtsi
+656
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Source for the PIC64GX SoCs
*
* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
*
* Author: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
*
* PIC64GX is a series RISC-V multicore SoCs:
* https://www.microchip.com/en-us/products/microprocessors/64-bit-mpus/pic64gx
*/
/dts-v1/;
#include "dt-bindings/clock/microchip,mpfs-clock.h"
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "Microchip PIC64GX SoC";
compatible = "microchip,pic64gx";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "sifive,e51", "sifive,rocket0", "riscv";
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
clocks = <&clkcfg CLK_CPU>;
status = "disabled";
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu1: cpu@1 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <1>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr",
"zicsr", "zifencei", "zihpm";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
next-level-cache = <&cctrllr>;
status = "okay";
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu2: cpu@2 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <2>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr",
"zicsr", "zifencei", "zihpm";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
next-level-cache = <&cctrllr>;
status = "okay";
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu3: cpu@3 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <3>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr",
"zicsr", "zifencei", "zihpm";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
next-level-cache = <&cctrllr>;
status = "okay";
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu4: cpu@4 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <4>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr",
"zicsr", "zifencei", "zihpm";
clocks = <&clkcfg CLK_CPU>;
tlb-split;
next-level-cache = <&cctrllr>;
status = "okay";
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
core4 {
cpu = <&cpu4>;
};
};
};
};
scbclk: clock-80000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <80000000>;
};
refclk: mssrefclk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
axiclk: axi-aclk0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
videoclk: video-aclk0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
syscontroller: syscontroller {
compatible = "microchip,pic64gx-sys-controller";
mboxes = <&mbox 0>;
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
clint: clint@2000000 {
compatible = "microchip,pic64gx-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0xC000>;
interrupts-extended = <&cpu0_intc 0xffffffff>, <&cpu0_intc 0xffffffff>,
<&cpu1_intc 3>, <&cpu1_intc 7>,
<&cpu2_intc 3>, <&cpu2_intc 7>,
<&cpu3_intc 3>, <&cpu3_intc 7>,
<&cpu4_intc 3>, <&cpu4_intc 7>;
};
cctrllr: cache-controller@2010000 {
compatible = "microchip,pic64gx-ccache", "microchip,mpfs-ccache",
"sifive,fu540-c000-ccache", "cache";
reg = <0x0 0x2010000 0x0 0x1000>;
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <1024>;
cache-size = <2097152>;
cache-unified;
interrupt-parent = <&plic>;
interrupts = <1>, <3>, <4>, <2>;
};
pdma: dma-controller@3000000 {
compatible = "microchip,pic64gx-pdma", "microchip,mpfs-pdma",
"sifive,pdma0";
reg = <0x0 0x3000000 0x0 0x8000>;
interrupt-parent = <&plic>;
interrupts = <5 6>, <7 8>, <9 10>, <11 12>;
#dma-cells = <1>;
};
plic: interrupt-controller@c000000 {
compatible = "microchip,pic64gx-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
interrupts-extended = <&cpu0_intc 0xffffffff>,
<&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
<&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
<&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
<&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
riscv,ndev = <186>;
};
mmuart0: serial@20000000 {
compatible = "ns16550a";
reg = <0x0 0x20000000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <90>;
current-speed = <115200>;
clocks = <&clkcfg CLK_MMUART0>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_mssio>;
status = "disabled"; /* Reserved for the HSS */
};
mss_top_sysreg: syscon@20002000 {
compatible = "microchip,pic64gx-mss-top-sysreg",
"microchip,mpfs-mss-top-sysreg",
"syscon", "simple-mfd";
reg = <0x0 0x20002000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
#reset-cells = <1>;
irqmux: interrupt-controller@54 {
compatible = "microchip,pic64gx-irqmux", "microchip,mpfs-irqmux";
reg = <0x54 0x4>;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0x7f>;
};
iomux0: pinctrl@200 {
compatible = "microchip,pic64gx-pinctrl-iomux0",
"microchip,mpfs-pinctrl-iomux0";
reg = <0x200 0x4>;
pinctrl-use-default;
};
mssio: pinctrl@204 {
compatible = "microchip,pic64gx-pinctrl-mssio",
"microchip,mpfs-pinctrl-mssio";
reg = <0x204 0x7c>;
/* on icicle ref design at least */
pinctrl-use-default;
};
};
sysreg_scb: syscon@20003000 {
compatible = "microchip,pic64gx-sysreg-scb",
"microchip,mpfs-sysreg-scb",
"syscon";
reg = <0x0 0x20003000 0x0 0x1000>;
};
/* Common node entry for emmc/sd */
mmc: mmc@20008000 {
compatible = "microchip,pic64gx-sd4hc", "cdns,sd4hc";
reg = <0x0 0x20008000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <88>;
clocks = <&clkcfg CLK_MMC>;
max-frequency = <200000000>;
status = "disabled";
};
mmuart1: serial@20100000 {
compatible = "ns16550a";
reg = <0x0 0x20100000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <91>;
current-speed = <115200>;
clocks = <&clkcfg CLK_MMUART1>;
status = "disabled";
};
mmuart2: serial@20102000 {
compatible = "ns16550a";
reg = <0x0 0x20102000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <92>;
current-speed = <115200>;
clocks = <&clkcfg CLK_MMUART2>;
status = "disabled";
};
mmuart3: serial@20104000 {
compatible = "ns16550a";
reg = <0x0 0x20104000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <93>;
current-speed = <115200>;
clocks = <&clkcfg CLK_MMUART3>;
status = "disabled";
};
mmuart4: serial@20106000 {
compatible = "ns16550a";
reg = <0x0 0x20106000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <94>;
clocks = <&clkcfg CLK_MMUART4>;
current-speed = <115200>;
status = "disabled";
};
spi0: spi@20108000 {
compatible = "microchip,pic64gx-spi", "microchip,mpfs-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20108000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <54>;
clocks = <&clkcfg CLK_SPI0>;
status = "disabled";
};
spi1: spi@20109000 {
compatible = "microchip,pic64gx-spi", "microchip,mpfs-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20109000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <55>;
clocks = <&clkcfg CLK_SPI1>;
pinctrl-names = "default";
pinctrl-0 = <&spi1_mssio>;
status = "disabled";
};
i2c0: i2c@2010a000 {
compatible = "microchip,pic64gx-i2c", "microchip,corei2c-rtl-v7";
reg = <0x0 0x2010a000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&plic>;
interrupts = <58>;
clocks = <&clkcfg CLK_I2C0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_mssio>;
status = "disabled";
};
i2c1: i2c@2010b000 {
compatible = "microchip,pic64gx-i2c", "microchip,corei2c-rtl-v7";
reg = <0x0 0x2010b000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&plic>;
interrupts = <61>;
clocks = <&clkcfg CLK_I2C1>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_mssio>;
status = "disabled";
};
can0: can@2010c000 {
compatible = "microchip,pic64gx-can", "microchip,mpfs-can";
reg = <0x0 0x2010c000 0x0 0x1000>;
clocks = <&clkcfg CLK_CAN0>, <&clkcfg CLK_MSSPLL3>;
interrupt-parent = <&plic>;
interrupts = <56>;
resets = <&mss_top_sysreg CLK_CAN0>;
status = "disabled";
};
can1: can@2010d000 {
compatible = "microchip,pic64gx-can", "microchip,mpfs-can";
reg = <0x0 0x2010d000 0x0 0x1000>;
clocks = <&clkcfg CLK_CAN1>, <&clkcfg CLK_MSSPLL3>;
interrupt-parent = <&plic>;
interrupts = <57>;
resets = <&mss_top_sysreg CLK_CAN1>;
status = "disabled";
};
mac0: ethernet@20110000 {
compatible = "microchip,pic64gx-macb", "microchip,mpfs-macb",
"cdns,macb";
reg = <0x0 0x20110000 0x0 0x2000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&plic>;
interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
/* Filled in by a bootloader */
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>, <&refclk>;
clock-names = "pclk", "hclk", "tsu_clk";
resets = <&mss_top_sysreg CLK_MAC0>;
status = "disabled";
};
mac1: ethernet@20112000 {
compatible = "microchip,pic64gx-macb", "microchip,mpfs-macb",
"cdns,macb";
reg = <0x0 0x20112000 0x0 0x2000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&plic>;
interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
/* Filled in by a bootloader */
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>, <&refclk>;
clock-names = "pclk", "hclk", "tsu_clk";
resets = <&mss_top_sysreg CLK_MAC1>;
status = "disabled";
};
gpio0: gpio@20120000 {
compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio";
reg = <0x0 0x20120000 0x0 0x1000>;
interrupt-parent = <&irqmux>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0>, <1>, <2>, <3>,
<4>, <5>, <6>, <7>,
<8>, <9>, <10>, <11>,
<12>, <13>;
clocks = <&clkcfg CLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <14>;
status = "disabled";
};
gpio1: gpio@20121000 {
compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio";
reg = <0x0 0x20121000 0x0 0x1000>;
interrupt-parent = <&irqmux>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <32>, <33>, <34>, <35>,
<36>, <37>, <38>, <39>,
<40>, <41>, <42>, <43>,
<44>, <45>, <46>, <47>,
<48>, <49>, <50>, <51>,
<52>, <53>, <54>, <55>;
clocks = <&clkcfg CLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
status = "disabled";
};
gpio2: gpio@20122000 {
compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio";
reg = <0x0 0x20122000 0x0 0x1000>;
interrupt-parent = <&irqmux>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <64>, <65>, <66>, <67>,
<68>, <69>, <70>, <71>,
<72>, <73>, <74>, <75>,
<76>, <77>, <78>, <79>,
<80>, <81>, <82>, <83>,
<84>, <85>, <86>, <87>,
<88>, <89>, <90>, <91>,
<92>, <93>, <94>, <95>;
clocks = <&clkcfg CLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
status = "disabled";
};
rtc: rtc@20124000 {
compatible = "microchip,pic64gx-rtc", "microchip,mpfs-rtc";
reg = <0x0 0x20124000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <80>, <81>;
clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;
clock-names = "rtc", "rtcref";
status = "disabled";
};
usb: usb@20201000 {
compatible = "microchip,pic64gx-musb", "microchip,mpfs-musb";
reg = <0x0 0x20201000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <86>, <87>;
clocks = <&clkcfg CLK_USB>;
interrupt-names = "dma", "mc";
status = "disabled";
};
qspi: spi@21000000 {
compatible = "microchip,pic64gx-qspi", "microchip,coreqspi-rtl-v2";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x21000000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <85>;
clocks = <&clkcfg CLK_QSPI>;
status = "disabled";
};
control_scb: syscon@37020000 {
compatible = "microchip,pic64gx-control-scb",
"microchip,mpfs-control-scb",
"syscon";
reg = <0x0 0x37020000 0x0 0x100>;
};
syscontroller_qspi: spi@37020100 {
compatible = "microchip,pic64gx-qspi", "microchip,coreqspi-rtl-v2";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x37020100 0x0 0x100>;
interrupt-parent = <&plic>;
interrupts = <110>;
clocks = <&scbclk>;
status = "disabled";
};
mbox: mailbox@37020800 {
compatible = "microchip,pic64gx-mailbox", "microchip,mpfs-mailbox";
reg = <0x0 0x37020800 0x0 0x100>;
interrupt-parent = <&plic>;
interrupts = <96>;
#mbox-cells = <1>;
status = "disabled";
};
ccc_se: clock-controller@38010000 {
compatible = "microchip,pic64gx-ccc", "microchip,mpfs-ccc";
reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>,
<0x0 0x39010000 0x0 0x1000>, <0x0 0x39020000 0x0 0x1000>;
#clock-cells = <1>;
status = "disabled";
};
ccc_ne: clock-controller@38040000 {
compatible = "microchip,pic64gx-ccc", "microchip,mpfs-ccc";
reg = <0x0 0x38040000 0x0 0x1000>, <0x0 0x38080000 0x0 0x1000>,
<0x0 0x39040000 0x0 0x1000>, <0x0 0x39080000 0x0 0x1000>;
#clock-cells = <1>;
status = "disabled";
};
ccc_nw: clock-controller@38100000 {
compatible = "microchip,pic64gx-ccc", "microchip,mpfs-ccc";
reg = <0x0 0x38100000 0x0 0x1000>, <0x0 0x38200000 0x0 0x1000>,
<0x0 0x39100000 0x0 0x1000>, <0x0 0x39200000 0x0 0x1000>;
#clock-cells = <1>;
status = "disabled";
};
ccc_sw: clock-controller@38400000 {
compatible = "microchip,pic64gx-ccc", "microchip,mpfs-ccc";
reg = <0x0 0x38400000 0x0 0x1000>, <0x0 0x38800000 0x0 0x1000>,
<0x0 0x39400000 0x0 0x1000>, <0x0 0x39800000 0x0 0x1000>;
#clock-cells = <1>;
status = "disabled";
};
clkcfg: clkcfg@3e001000 {
compatible = "microchip,pic64gx-clkcfg", "microchip,mpfs-clkcfg";
reg = <0x0 0x3e001000 0x0 0x1000>;
clocks = <&refclk>;
#clock-cells = <1>;
};
gpio2_pinctrl: pinctrl@41000000 {
compatible = "microchip,pic64gx-pinctrl-gpio2";
reg = <0x0 0x41000000 0x0 0x4>;
pinctrl-use-default;
pinctrl-names = "default";
pinctrl-0 = <&mdio0_fio>, <&mdio1_fio>, <&spi0_fio>, <&qspi_fio>,
<&uart3_fio>, <&uart4_fio>, <&can1_fio>, <&can0_fio>,
<&uart2_fio>;
};
};
};