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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/arch/riscv/boot/dts/sophgo/Makefile
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# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v1.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v2.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2044-sophgo-srd3-10.dtb
linux-7.2.3/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
*/
/dts-v1/;
#include "cv1800b.dtsi"
/ {
model = "Milk-V Duo";
compatible = "milkv,duo", "sophgo,cv1800b";
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
};
chosen {
stdout-path = "serial0:115200n8";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
coprocessor_rtos: region@83f40000 {
reg = <0x83f40000 0xc0000>;
no-map;
};
};
};
&osc {
clock-frequency = <25000000>;
};
&pinctrl {
uart0_cfg: uart0-cfg {
uart0-pins {
pinmux = <PINMUX(PIN_UART0_TX, 0)>,
<PINMUX(PIN_UART0_RX, 0)>;
bias-pull-up;
drive-strength-microamp = <10800>;
power-source = <3300>;
};
};
sdhci0_cfg: sdhci0-cfg {
sdhci0-clk-pins {
pinmux = <PINMUX(PIN_SD0_CLK, 0)>;
bias-pull-up;
drive-strength-microamp = <16100>;
power-source = <3300>;
};
sdhci0-cmd-pins {
pinmux = <PINMUX(PIN_SD0_CMD, 0)>;
bias-pull-up;
drive-strength-microamp = <10800>;
power-source = <3300>;
};
sdhci0-data-pins {
pinmux = <PINMUX(PIN_SD0_D0, 0)>,
<PINMUX(PIN_SD0_D1, 0)>,
<PINMUX(PIN_SD0_D2, 0)>,
<PINMUX(PIN_SD0_D3, 0)>;
bias-pull-up;
drive-strength-microamp = <10800>;
power-source = <3300>;
};
sdhci0-cd-pins {
pinmux = <PINMUX(PIN_SD0_CD, 0)>;
bias-pull-up;
drive-strength-microamp = <10800>;
power-source = <3300>;
};
};
};
&sdhci0 {
pinctrl-0 = <&sdhci0_cfg>;
pinctrl-names = "default";
status = "okay";
bus-width = <4>;
no-1-8-v;
no-mmc;
no-sdio;
disable-wp;
};
&uart0 {
pinctrl-0 = <&uart0_cfg>;
pinctrl-names = "default";
status = "okay";
};
&usb {
dr_mode = "host";
status = "okay";
};
linux-7.2.3/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
*/
#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
#include <dt-bindings/pinctrl/pinctrl-cv1800b.h>
#include "cv180x-cpus.dtsi"
#include "cv180x.dtsi"
/ {
compatible = "sophgo,cv1800b";
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x4000000>;
};
soc {
interrupt-parent = <&plic>;
dma-noncoherent;
pinctrl: pinctrl@3001000 {
compatible = "sophgo,cv1800b-pinctrl";
reg = <0x03001000 0x1000>,
<0x05027000 0x1000>;
reg-names = "sys", "rtc";
};
clk: clock-controller@3002000 {
compatible = "sophgo,cv1800b-clk";
reg = <0x03002000 0x1000>;
clocks = <&osc>;
#clock-cells = <1>;
};
plic: interrupt-controller@70000000 {
compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
reg = <0x70000000 0x4000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
riscv,ndev = <101>;
};
clint: timer@74000000 {
compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
reg = <0x74000000 0x10000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
};
};
};
linux-7.2.3/arch/riscv/boot/dts/sophgo/cv180x-cpus.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
*/
/ {
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <25000000>;
cpu0: cpu@0 {
compatible = "thead,c906", "riscv";
device_type = "cpu";
reg = <0>;
d-cache-block-size = <64>;
d-cache-sets = <512>;
d-cache-size = <65536>;
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <32768>;
mmu-type = "riscv,sv39";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
};
};
linux-7.2.3/arch/riscv/boot/dts/sophgo/cv180x.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
*/
#include <dt-bindings/clock/sophgo,cv1800.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "cv18xx-reset.h"
/ {
#address-cells = <1>;
#size-cells = <1>;
osc: oscillator {
compatible = "fixed-clock";
clock-output-names = "osc_25m";
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
syscon: syscon@3000000 {
compatible = "sophgo,cv1800b-top-syscon",
"syscon", "simple-mfd";
reg = <0x03000000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
usbphy: phy@48 {
compatible = "sophgo,cv1800b-usb2-phy";
reg = <0x48 0x4>;
#phy-cells = <0>;
clocks = <&clk CLK_USB_125M>,
<&clk CLK_USB_33K>,
<&clk CLK_USB_12M>;
clock-names = "app", "stb", "lpm";
resets = <&rst RST_COMBO_PHY0>;
};
dmamux: dma-router@154 {
compatible = "sophgo,cv1800b-dmamux";
reg = <0x154 0x8>, <0x298 0x4>;
#dma-cells = <2>;
dma-masters = <&dmac>;
};
};
rst: reset-controller@3003000 {
compatible = "sophgo,cv1800b-reset";
reg = <0x3003000 0x1000>;
#reset-cells = <1>;
};
mdio: mdio-mux@3009800 {
compatible = "mdio-mux-mmioreg", "mdio-mux";
reg = <0x3009800 0x4>;
#address-cells = <1>;
#size-cells = <0>;
mdio-parent-bus = <&gmac0_mdio>;
mux-mask = <0x80>;
status = "disabled";
internal_mdio: mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
internal_ephy: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
external_mdio: mdio@80 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x80>;
};
};
gpio0: gpio@3020000 {
compatible = "snps,dw-apb-gpio";
reg = <0x3020000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&rst RST_GPIO0>;
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>;
};
};
gpio1: gpio@3021000 {
compatible = "snps,dw-apb-gpio";
reg = <0x3021000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&rst RST_GPIO1>;
portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
};
};
gpio2: gpio@3022000 {
compatible = "snps,dw-apb-gpio";
reg = <0x3022000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&rst RST_GPIO2>;
portc: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>;
};
};
gpio3: gpio@3023000 {
compatible = "snps,dw-apb-gpio";
reg = <0x3023000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&rst RST_GPIO3>;
portd: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_LEVEL_HIGH>;
};
};
saradc: adc@30f0000 {
compatible = "sophgo,cv1800b-saradc";
reg = <0x030f0000 0x1000>;
clocks = <&clk CLK_SARADC>;
interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
channel@0 {
reg = <0>;
};
channel@1 {
reg = <1>;
};
channel@2 {
reg = <2>;
};
};
i2c0: i2c@4000000 {
compatible = "snps,designware-i2c";
reg = <0x04000000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
clock-names = "ref", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_I2C0>;
status = "disabled";
};
i2c1: i2c@4010000 {
compatible = "snps,designware-i2c";
reg = <0x04010000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
clock-names = "ref", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_I2C1>;
status = "disabled";
};
i2c2: i2c@4020000 {
compatible = "snps,designware-i2c";
reg = <0x04020000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
clock-names = "ref", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_I2C2>;
status = "disabled";
};
i2c3: i2c@4030000 {
compatible = "snps,designware-i2c";
reg = <0x04030000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
clock-names = "ref", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_I2C3>;
status = "disabled";
};
i2c4: i2c@4040000 {
compatible = "snps,designware-i2c";
reg = <0x04040000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
clock-names = "ref", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_I2C4>;
status = "disabled";
};
gmac0: ethernet@4070000 {
compatible = "sophgo,cv1800b-dwmac", "snps,dwmac-3.70a";
reg = <0x04070000 0x10000>;
clocks = <&clk CLK_AXI4_ETH0>, <&clk CLK_ETH0_500M>;
clock-names = "stmmaceth", "ptp_ref";
interrupts = <SOC_PERIPHERAL_IRQ(15) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
phy-handle = <&internal_ephy>;
phy-mode = "internal";
resets = <&rst RST_ETH0>;
reset-names = "stmmaceth";
rx-fifo-depth = <8192>;
tx-fifo-depth = <8192>;
snps,multicast-filter-bins = <0>;
snps,perfect-filter-entries = <1>;
snps,aal;
snps,txpbl = <8>;
snps,rxpbl = <8>;
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
snps,axi-config = <&gmac0_stmmac_axi_setup>;
status = "disabled";
gmac0_mdio: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
gmac0_mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <1>;
queue0 {};
};
gmac0_mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <1>;
queue0 {};
};
gmac0_stmmac_axi_setup: stmmac-axi-config {
snps,blen = <16 8 4 0 0 0 0>;
snps,rd_osr_lmt = <2>;
snps,wr_osr_lmt = <1>;
};
};
uart0: serial@4140000 {
compatible = "snps,dw-apb-uart";
reg = <0x04140000 0x100>;
interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst RST_UART0>;
status = "disabled";
};
uart1: serial@4150000 {
compatible = "snps,dw-apb-uart";
reg = <0x04150000 0x100>;
interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst RST_UART1>;
status = "disabled";
};
uart2: serial@4160000 {
compatible = "snps,dw-apb-uart";
reg = <0x04160000 0x100>;
interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst RST_UART2>;
status = "disabled";
};
uart3: serial@4170000 {
compatible = "snps,dw-apb-uart";
reg = <0x04170000 0x100>;
interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst RST_UART3>;
status = "disabled";
};
spi0: spi@4180000 {
compatible = "snps,dw-apb-ssi";
reg = <0x04180000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
clock-names = "ssi_clk", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_SPI0>;
status = "disabled";
};
spi1: spi@4190000 {
compatible = "snps,dw-apb-ssi";
reg = <0x04190000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
clock-names = "ssi_clk", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_SPI1>;
status = "disabled";
};
spi2: spi@41a0000 {
compatible = "snps,dw-apb-ssi";
reg = <0x041a0000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
clock-names = "ssi_clk", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_SPI2>;
status = "disabled";
};
spi3: spi@41b0000 {
compatible = "snps,dw-apb-ssi";
reg = <0x041b0000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
clock-names = "ssi_clk", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_SPI3>;
status = "disabled";
};
uart4: serial@41c0000 {
compatible = "snps,dw-apb-uart";
reg = <0x041c0000 0x100>;
interrupts = <SOC_PERIPHERAL_IRQ(32) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst RST_UART4>;
status = "disabled";
};
sdhci0: mmc@4310000 {
compatible = "sophgo,cv1800b-dwcmshc";
reg = <0x4310000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(20) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_AXI4_SD0>,
<&clk CLK_SD0>;
clock-names = "core", "bus";
status = "disabled";
};
sdhci1: mmc@4320000 {
compatible = "sophgo,cv1800b-dwcmshc";
reg = <0x4320000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_AXI4_SD1>,
<&clk CLK_SD1>;
clock-names = "core", "bus";
status = "disabled";
};
dmac: dma-controller@4330000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x04330000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(13) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>;
clock-names = "core-clk", "cfgr-clk";
#dma-cells = <1>;
dma-channels = <8>;
snps,block-size = <1024 1024 1024 1024
1024 1024 1024 1024>;
snps,priority = <0 1 2 3 4 5 6 7>;
snps,dma-masters = <2>;
snps,data-width = <2>;
status = "disabled";
};
usb: usb@4340000 {
compatible = "sophgo,cv1800b-usb";
reg = <0x04340000 0x10000>;
clocks = <&clk CLK_AXI4_USB>, <&clk CLK_APB_USB>;
clock-names = "otg", "utmi";
g-np-tx-fifo-size = <32>;
g-rx-fifo-size = <1536>;
g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
interrupts = <SOC_PERIPHERAL_IRQ(14) IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbphy>;
phy-names = "usb2-phy";
resets = <&rst RST_USB>;
reset-names = "dwc2";
status = "disabled";
};
rtc@5025000 {
compatible = "sophgo,cv1800b-rtc", "syscon";
reg = <0x5025000 0x2000>;
interrupts = <SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "alarm", "longpress", "vbat";
clocks = <&clk CLK_RTC_25M>,
<&clk CLK_SRC_RTC_SYS_0>;
clock-names = "rtc", "mcu";
};
};
};
linux-7.2.3/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
*/
/dts-v1/;
#include "cv1812h.dtsi"
/ {
model = "Huashan Pi";
compatible = "sophgo,huashan-pi", "sophgo,cv1812h";
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
};
chosen {
stdout-path = "serial0:115200n8";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
coprocessor_rtos: region@8fe00000 {
reg = <0x8fe00000 0x200000>;
no-map;
};
};
};
&osc {
clock-frequency = <25000000>;
};
&emmc {
status = "okay";
bus-width = <4>;
max-frequency = <200000000>;
mmc-ddr-1_8v;
mmc-ddr-3_3v;
mmc-hs200-1_8v;
no-sd;
no-sdio;
non-removable;
};
&gmac0 {
status = "okay";
};
&mdio {
status = "okay";
};
&sdhci0 {
status = "okay";
bus-width = <4>;
no-1-8-v;
no-mmc;
no-sdio;
disable-wp;
};
&sdhci1 {
status = "okay";
bus-width = <4>;
cap-sdio-irq;
max-frequency = <50000000>;
no-mmc;
no-sd;
disable-wp;
non-removable;
};
&uart0 {
status = "okay";
};
&usb {
dr_mode = "host";
status = "okay";
};
linux-7.2.3/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
*/
#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/pinctrl-cv1812h.h>
#include "cv180x-cpus.dtsi"
#include "cv180x.dtsi"
#include "cv181x.dtsi"
/ {
compatible = "sophgo,cv1812h";
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
soc {
interrupt-parent = <&plic>;
dma-noncoherent;
pinctrl: pinctrl@3001000 {
compatible = "sophgo,cv1812h-pinctrl";
reg = <0x03001000 0x1000>,
<0x05027000 0x1000>;
reg-names = "sys", "rtc";
};
clk: clock-controller@3002000 {
compatible = "sophgo,cv1812h-clk";
reg = <0x03002000 0x1000>;
clocks = <&osc>;
#clock-cells = <1>;
};
plic: interrupt-controller@70000000 {
compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
reg = <0x70000000 0x4000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
riscv,ndev = <101>;
};
clint: timer@74000000 {
compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
reg = <0x74000000 0x10000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
};
};
};
linux-7.2.3/arch/riscv/boot/dts/sophgo/cv181x.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
*/
#include <dt-bindings/clock/sophgo,cv1800.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
soc {
emmc: mmc@4300000 {
compatible = "sophgo,cv1800b-dwcmshc";
reg = <0x4300000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(18) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_AXI4_EMMC>,
<&clk CLK_EMMC>;
clock-names = "core", "bus";
status = "disabled";
};
};
};
linux-7.2.3/arch/riscv/boot/dts/sophgo/cv18xx-reset.h
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Copyright (C) 2025 Inochi Amaoto <inochiama@outlook.com>
*/
#ifndef _SOPHGO_CV18XX_RESET
#define _SOPHGO_CV18XX_RESET
#define RST_DDR 2
#define RST_H264C 3
#define RST_JPEG 4
#define RST_H265C 5
#define RST_VIPSYS 6
#define RST_TDMA 7
#define RST_TPU 8
#define RST_TPUSYS 9
#define RST_USB 11
#define RST_ETH0 12
#define RST_ETH1 13
#define RST_NAND 14
#define RST_EMMC 15
#define RST_SD0 16
#define RST_SDMA 18
#define RST_I2S0 19
#define RST_I2S1 20
#define RST_I2S2 21
#define RST_I2S3 22
#define RST_UART0 23
#define RST_UART1 24
#define RST_UART2 25
#define RST_UART3 26
#define RST_I2C0 27
#define RST_I2C1 28
#define RST_I2C2 29
#define RST_I2C3 30
#define RST_I2C4 31
#define RST_PWM0 32
#define RST_PWM1 33
#define RST_PWM2 34
#define RST_PWM3 35
#define RST_SPI0 40
#define RST_SPI1 41
#define RST_SPI2 42
#define RST_SPI3 43
#define RST_GPIO0 44
#define RST_GPIO1 45
#define RST_GPIO2 46
#define RST_EFUSE 47
#define RST_WDT 48
#define RST_AHB_ROM 49
#define RST_SPIC 50
#define RST_TEMPSEN 51
#define RST_SARADC 52
#define RST_COMBO_PHY0 58
#define RST_SPI_NAND 61
#define RST_SE 62
#define RST_UART4 74
#define RST_GPIO3 75
#define RST_SYSTEM 76
#define RST_TIMER 77
#define RST_TIMER0 78
#define RST_TIMER1 79
#define RST_TIMER2 80
#define RST_TIMER3 81
#define RST_TIMER4 82
#define RST_TIMER5 83
#define RST_TIMER6 84
#define RST_TIMER7 85
#define RST_WGN0 86
#define RST_WGN1 87
#define RST_WGN2 88
#define RST_KEYSCAN 89
#define RST_AUDDAC 91
#define RST_AUDDAC_APB 92
#define RST_AUDADC 93
#define RST_VCSYS 95
#define RST_ETHPHY 96
#define RST_ETHPHY_APB 97
#define RST_AUDSRC 98
#define RST_VIP_CAM0 99
#define RST_WDT1 100
#define RST_WDT2 101
#define RST_AUTOCLEAR_CPUCORE0 256
#define RST_AUTOCLEAR_CPUCORE1 257
#define RST_AUTOCLEAR_CPUCORE2 258
#define RST_AUTOCLEAR_CPUCORE3 259
#define RST_AUTOCLEAR_CPUSYS0 260
#define RST_AUTOCLEAR_CPUSYS1 261
#define RST_AUTOCLEAR_CPUSYS2 262
#define RST_CPUCORE0 288
#define RST_CPUCORE1 289
#define RST_CPUCORE2 290
#define RST_CPUCORE3 291
#define RST_CPUSYS0 292
#define RST_CPUSYS1 293
#define RST_CPUSYS2 294
#endif /* _SOPHGO_CV18XX_RESET */
linux-7.2.3/arch/riscv/boot/dts/sophgo/sg2002-licheerv-nano-b.dts
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@bootlin.com>
*/
/dts-v1/;
#include "sg2002.dtsi"
/ {
model = "LicheeRV Nano B";
compatible = "sipeed,licheerv-nano-b", "sipeed,licheerv-nano", "sophgo,sg2002";
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&osc {
clock-frequency = <25000000>;
};
&pinctrl {
uart0_cfg: uart0-cfg {
uart0-pins {
pinmux = <PINMUX(PIN_UART0_TX, 0)>,
<PINMUX(PIN_UART0_RX, 0)>;
bias-pull-up;
drive-strength-microamp = <10800>;
power-source = <3300>;
};
};
sdhci0_cfg: sdhci0-cfg {
sdhci0-clk-pins {
pinmux = <PINMUX(PIN_SD0_CLK, 0)>;
bias-pull-up;
drive-strength-microamp = <16100>;
power-source = <3300>;
};
sdhci0-cmd-pins {
pinmux = <PINMUX(PIN_SD0_CMD, 0)>;
bias-pull-up;
drive-strength-microamp = <10800>;
power-source = <3300>;
};
sdhci0-data-pins {
pinmux = <PINMUX(PIN_SD0_D0, 0)>,
<PINMUX(PIN_SD0_D1, 0)>,
<PINMUX(PIN_SD0_D2, 0)>,
<PINMUX(PIN_SD0_D3, 0)>;
bias-pull-up;
drive-strength-microamp = <10800>;
power-source = <3300>;
};
sdhci0-cd-pins {
pinmux = <PINMUX(PIN_SD0_CD, 0)>;
bias-pull-up;
drive-strength-microamp = <10800>;
power-source = <3300>;
};
};
};
&sdhci0 {
pinctrl-0 = <&sdhci0_cfg>;
pinctrl-names = "default";
status = "okay";
bus-width = <4>;
no-1-8-v;
no-mmc;
no-sdio;
disable-wp;
};
&uart0 {
pinctrl-0 = <&uart0_cfg>;
pinctrl-names = "default";
status = "okay";
};
&usb {
dr_mode = "host";
status = "okay";
};
linux-7.2.3/arch/riscv/boot/dts/sophgo/sg2002.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@bootlin.com>
*/
#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/pinctrl-sg2002.h>
#include "cv180x-cpus.dtsi"
#include "cv180x.dtsi"
#include "cv181x.dtsi"
/ {
compatible = "sophgo,sg2002";
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
soc {
interrupt-parent = <&plic>;
dma-noncoherent;
pinctrl: pinctrl@3001000 {
compatible = "sophgo,sg2002-pinctrl";
reg = <0x03001000 0x1000>,
<0x05027000 0x1000>;
reg-names = "sys", "rtc";
};
clk: clock-controller@3002000 {
compatible = "sophgo,sg2002-clk", "sophgo,sg2000-clk";
reg = <0x03002000 0x1000>;
clocks = <&osc>;
#clock-cells = <1>;
};
plic: interrupt-controller@70000000 {
compatible = "sophgo,sg2002-plic", "thead,c900-plic";
reg = <0x70000000 0x4000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
riscv,ndev = <101>;
};
clint: timer@74000000 {
compatible = "sophgo,sg2002-clint", "thead,c900-clint";
reg = <0x74000000 0x10000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
};
};
};
&sdhci0 {
compatible = "sophgo,sg2002-dwcmshc";
};
linux-7.2.3/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
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linux-7.2.3/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2025 Sophgo Technology Inc. All rights reserved.
*/
#include "sg2042.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Sophgo SG2042 EVB V1.X";
compatible = "sophgo,sg2042-evb-v1", "sophgo,sg2042";
chosen {
stdout-path = "serial0";
};
gpio-power {
compatible = "gpio-keys";
key-power {
label = "Power Key";
linux,code = <KEY_POWER>;
gpios = <&port0a 22 GPIO_ACTIVE_HIGH>;
linux,input-type = <EV_KEY>;
debounce-interval = <100>;
};
};
pwmfan: pwm-fan {
compatible = "pwm-fan";
cooling-levels = <103 128 179 230 255>;
pwms = <&pwm 0 40000 0>;
#cooling-cells = <2>;
};
thermal-zones {
soc-thermal {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&mcu 0>;
trips {
soc_active1: soc-active1 {
temperature = <30000>;
hysteresis = <8000>;
type = "active";
};
soc_active2: soc-active2 {
temperature = <58000>;
hysteresis = <12000>;
type = "active";
};
soc_active3: soc-active3 {
temperature = <70000>;
hysteresis = <10000>;
type = "active";
};
soc_hot: soc-hot {
temperature = <80000>;
hysteresis = <5000>;
type = "hot";
};
};
cooling-maps {
map0 {
trip = <&soc_active1>;
cooling-device = <&pwmfan 0 1>;
};
map1 {
trip = <&soc_active2>;
cooling-device = <&pwmfan 1 2>;
};
map2 {
trip = <&soc_active3>;
cooling-device = <&pwmfan 2 3>;
};
map3 {
trip = <&soc_hot>;
cooling-device = <&pwmfan 3 4>;
};
};
};
board-thermal {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&mcu 1>;
trips {
board_active: board-active {
temperature = <75000>;
hysteresis = <8000>;
type = "active";
};
};
cooling-maps {
map4 {
trip = <&board_active>;
cooling-device = <&pwmfan 3 4>;
};
};
};
};
};
&cgi_main {
clock-frequency = <25000000>;
};
&cgi_dpll0 {
clock-frequency = <25000000>;
};
&cgi_dpll1 {
clock-frequency = <25000000>;
};
&emmc {
pinctrl-0 = <&emmc_cfg>;
pinctrl-names = "default";
bus-width = <4>;
no-sdio;
no-sd;
non-removable;
wp-inverted;
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_cfg>;
pinctrl-names = "default";
status = "okay";
mcu: syscon@17 {
compatible = "sophgo,sg2042-hwmon-mcu";
reg = <0x17>;
#thermal-sensor-cells = <1>;
};
};
&gmac0 {
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
mdio {
phy0: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&port0a 27 GPIO_ACTIVE_LOW>;
reset-assert-us = <100000>;
reset-deassert-us = <100000>;
};
};
};
&pcie_rc0 {
status = "okay";
};
&pcie_rc1 {
status = "okay";
};
&pcie_rc2 {
status = "okay";
};
&pinctrl {
emmc_cfg: sdhci-emmc-cfg {
sdhci-emmc-wp-pins {
pinmux = <PINMUX(PIN_EMMC_WP, 0)>;
bias-disable;
drive-strength-microamp = <26800>;
input-schmitt-disable;
};
sdhci-emmc-cd-pins {
pinmux = <PINMUX(PIN_EMMC_CD, 0)>;
bias-pull-up;
drive-strength-microamp = <26800>;
input-schmitt-enable;
};
sdhci-emmc-rst-pwr-pins {
pinmux = <PINMUX(PIN_EMMC_RST, 0)>,
<PINMUX(PIN_EMMC_PWR_EN, 0)>;
bias-disable;
drive-strength-microamp = <26800>;
input-schmitt-disable;
};
};
i2c1_cfg: i2c1-cfg {
i2c1-pins {
pinmux = <PINMUX(PIN_IIC1_SDA, 0)>,
<PINMUX(PIN_IIC1_SCL, 0)>;
bias-pull-up;
drive-strength-microamp = <26800>;
input-schmitt-enable;
};
};
sd_cfg: sdhci-sd-cfg {
sdhci-sd-cd-wp-pins {
pinmux = <PINMUX(PIN_SDIO_CD, 0)>,
<PINMUX(PIN_SDIO_WP, 0)>;
bias-pull-up;
drive-strength-microamp = <26800>;
input-schmitt-enable;
};
sdhci-sd-rst-pwr-pins {
pinmux = <PINMUX(PIN_SDIO_RST, 0)>,
<PINMUX(PIN_SDIO_PWR_EN, 0)>;
bias-disable;
drive-strength-microamp = <26800>;
input-schmitt-disable;
};
};
uart0_cfg: uart0-cfg {
uart0-rx-pins {
pinmux = <PINMUX(PIN_UART0_TX, 0)>,
<PINMUX(PIN_UART0_RX, 0)>;
bias-pull-up;
drive-strength-microamp = <26800>;
input-schmitt-enable;
};
};
};
&sd {
pinctrl-0 = <&sd_cfg>;
pinctrl-names = "default";
bus-width = <4>;
no-sdio;
no-mmc;
wp-inverted;
status = "okay";
};
&spifmc0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};
&spifmc1 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};
&uart0 {
pinctrl-0 = <&uart0_cfg>;
pinctrl-names = "default";
status = "okay";
};
linux-7.2.3/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2025 Sophgo Technology Inc. All rights reserved.
*/
#include "sg2042.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Sophgo SG2042 EVB V2.0";
compatible = "sophgo,sg2042-evb-v2", "sophgo,sg2042";
chosen {
stdout-path = "serial0";
};
pwmfan: pwm-fan {
compatible = "pwm-fan";
cooling-levels = <103 128 179 230 255>;
pwms = <&pwm 0 40000 0>;
#cooling-cells = <2>;
};
thermal-zones {
soc-thermal {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&mcu 0>;
trips {
soc_active1: soc-active1 {
temperature = <30000>;
hysteresis = <8000>;
type = "active";
};
soc_active2: soc-active2 {
temperature = <58000>;
hysteresis = <12000>;
type = "active";
};
soc_active3: soc-active3 {
temperature = <70000>;
hysteresis = <10000>;
type = "active";
};
soc_hot: soc-hot {
temperature = <80000>;
hysteresis = <5000>;
type = "hot";
};
};
cooling-maps {
map0 {
trip = <&soc_active1>;
cooling-device = <&pwmfan 0 1>;
};
map1 {
trip = <&soc_active2>;
cooling-device = <&pwmfan 1 2>;
};
map2 {
trip = <&soc_active3>;
cooling-device = <&pwmfan 2 3>;
};
map3 {
trip = <&soc_hot>;
cooling-device = <&pwmfan 3 4>;
};
};
};
board-thermal {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&mcu 1>;
trips {
board_active: board-active {
temperature = <75000>;
hysteresis = <8000>;
type = "active";
};
};
cooling-maps {
map4 {
trip = <&board_active>;
cooling-device = <&pwmfan 3 4>;
};
};
};
};
};
&cgi_main {
clock-frequency = <25000000>;
};
&cgi_dpll0 {
clock-frequency = <25000000>;
};
&cgi_dpll1 {
clock-frequency = <25000000>;
};
&emmc {
pinctrl-0 = <&emmc_cfg>;
pinctrl-names = "default";
bus-width = <4>;
no-sdio;
no-sd;
non-removable;
wp-inverted;
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_cfg>;
pinctrl-names = "default";
status = "okay";
mcu: syscon@17 {
compatible = "sophgo,sg2042-hwmon-mcu";
reg = <0x17>;
#thermal-sensor-cells = <1>;
};
};
&gmac0 {
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
mdio {
phy0: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&port0a 27 GPIO_ACTIVE_LOW>;
reset-assert-us = <100000>;
reset-deassert-us = <100000>;
};
};
};
&pcie_rc0 {
status = "okay";
};
&pcie_rc1 {
status = "okay";
};
&pcie_rc2 {
status = "okay";
};
&pinctrl {
emmc_cfg: sdhci-emmc-cfg {
sdhci-emmc-wp-pins {
pinmux = <PINMUX(PIN_EMMC_WP, 0)>;
bias-disable;
drive-strength-microamp = <26800>;
input-schmitt-disable;
};
sdhci-emmc-cd-pins {
pinmux = <PINMUX(PIN_EMMC_CD, 0)>;
bias-pull-up;
drive-strength-microamp = <26800>;
input-schmitt-enable;
};
sdhci-emmc-rst-pwr-pins {
pinmux = <PINMUX(PIN_EMMC_RST, 0)>,
<PINMUX(PIN_EMMC_PWR_EN, 0)>;
bias-disable;
drive-strength-microamp = <26800>;
input-schmitt-disable;
};
};
i2c1_cfg: i2c1-cfg {
i2c1-pins {
pinmux = <PINMUX(PIN_IIC1_SDA, 0)>,
<PINMUX(PIN_IIC1_SCL, 0)>;
bias-pull-up;
drive-strength-microamp = <26800>;
input-schmitt-enable;
};
};
sd_cfg: sdhci-sd-cfg {
sdhci-sd-cd-wp-pins {
pinmux = <PINMUX(PIN_SDIO_CD, 0)>,
<PINMUX(PIN_SDIO_WP, 0)>;
bias-pull-up;
drive-strength-microamp = <26800>;
input-schmitt-enable;
};
sdhci-sd-rst-pwr-pins {
pinmux = <PINMUX(PIN_SDIO_RST, 0)>,
<PINMUX(PIN_SDIO_PWR_EN, 0)>;
bias-disable;
drive-strength-microamp = <26800>;
input-schmitt-disable;
};
};
uart0_cfg: uart0-cfg {
uart0-rx-pins {
pinmux = <PINMUX(PIN_UART0_TX, 0)>,
<PINMUX(PIN_UART0_RX, 0)>;
bias-pull-up;
drive-strength-microamp = <26800>;
input-schmitt-enable;
};
};
};
&sd {
pinctrl-0 = <&sd_cfg>;
pinctrl-names = "default";
bus-width = <4>;
no-sdio;
no-mmc;
wp-inverted;
status = "okay";
};
&spifmc1 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};
&uart0 {
pinctrl-0 = <&uart0_cfg>;
pinctrl-names = "default";
status = "okay";
};
linux-7.2.3/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
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// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
*/
#include "sg2042.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Milk-V Pioneer";
compatible = "milkv,pioneer", "sophgo,sg2042";
chosen {
stdout-path = "serial0";
};
gpio-power {
compatible = "gpio-keys";
key-power {
label = "Power Key";
linux,code = <KEY_POWER>;
gpios = <&port0a 22 GPIO_ACTIVE_HIGH>;
linux,input-type = <EV_KEY>;
debounce-interval = <100>;
};
};
};
&cgi_main {
clock-frequency = <25000000>;
};
&cgi_dpll0 {
clock-frequency = <25000000>;
};
&cgi_dpll1 {
clock-frequency = <25000000>;
};
&emmc {
pinctrl-0 = <&emmc_cfg>;
pinctrl-names = "default";
bus-width = <4>;
no-sdio;
no-sd;
non-removable;
wp-inverted;
status = "okay";
};
&i2c0 {
pinctrl-0 = <&i2c0_cfg>;
pinctrl-names = "default";
status = "okay";
rtc: rtc@68 {
compatible = "dallas,ds1307";
reg = <0x68>;
};
};
&i2c1 {
pinctrl-0 = <&i2c1_cfg>;
pinctrl-names = "default";
status = "okay";
mcu: syscon@17 {
compatible = "sophgo,sg2042-hwmon-mcu";
reg = <0x17>;
#thermal-sensor-cells = <1>;
};
};
&pinctrl {
emmc_cfg: sdhci-emmc-cfg {
sdhci-emmc-wp-pins {
pinmux = <PINMUX(PIN_EMMC_WP, 0)>;
bias-disable;
drive-strength-microamp = <26800>;
input-schmitt-disable;
};
sdhci-emmc-cd-pins {
pinmux = <PINMUX(PIN_EMMC_CD, 0)>;
bias-pull-up;
drive-strength-microamp = <26800>;
input-schmitt-enable;
};
sdhci-emmc-rst-pwr-pins {
pinmux = <PINMUX(PIN_EMMC_RST, 0)>,
<PINMUX(PIN_EMMC_PWR_EN, 0)>;
bias-disable;
drive-strength-microamp = <26800>;
input-schmitt-disable;
};
};
i2c0_cfg: i2c0-cfg {
i2c0-pins {
pinmux = <PINMUX(PIN_IIC0_SDA, 0)>,
<PINMUX(PIN_IIC0_SCL, 0)>;
bias-pull-up;
drive-strength-microamp = <26800>;
input-schmitt-enable;
};
};
i2c1_cfg: i2c1-cfg {
i2c1-pins {
pinmux = <PINMUX(PIN_IIC1_SDA, 0)>,
<PINMUX(PIN_IIC1_SCL, 0)>;
bias-pull-up;
drive-strength-microamp = <26800>;
input-schmitt-enable;
};
};
sd_cfg: sdhci-sd-cfg {
sdhci-sd-cd-wp-pins {
pinmux = <PINMUX(PIN_SDIO_CD, 0)>,
<PINMUX(PIN_SDIO_WP, 0)>;
bias-pull-up;
drive-strength-microamp = <26800>;
input-schmitt-enable;
};
sdhci-sd-rst-pwr-pins {
pinmux = <PINMUX(PIN_SDIO_RST, 0)>,
<PINMUX(PIN_SDIO_PWR_EN, 0)>;
bias-disable;
drive-strength-microamp = <26800>;
input-schmitt-disable;
};
};
uart0_cfg: uart0-cfg {
uart0-rx-pins {
pinmux = <PINMUX(PIN_UART0_TX, 0)>,
<PINMUX(PIN_UART0_RX, 0)>;
bias-pull-up;
drive-strength-microamp = <26800>;
input-schmitt-enable;
};
};
};
&pcie_rc0 {
status = "okay";
};
&pcie_rc2 {
status = "okay";
};
&pcie_rc3 {
status = "okay";
};
&sd {
pinctrl-0 = <&sd_cfg>;
pinctrl-names = "default";
bus-width = <4>;
no-sdio;
no-mmc;
wp-inverted;
status = "okay";
};
&spifmc0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};
&spifmc1 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};
&uart0 {
pinctrl-0 = <&uart0_cfg>;
pinctrl-names = "default";
status = "okay";
};
/ {
pwmfan: pwm-fan {
compatible = "pwm-fan";
cooling-levels = <103 128 179 230 255>;
pwms = <&pwm 0 40000 0>;
#cooling-cells = <2>;
};
thermal-zones {
soc-thermal {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&mcu 0>;
trips {
soc_active1: soc-active1 {
temperature = <30000>;
hysteresis = <8000>;
type = "active";
};
soc_active2: soc-active2 {
temperature = <58000>;
hysteresis = <12000>;
type = "active";
};
soc_active3: soc-active3 {
temperature = <70000>;
hysteresis = <10000>;
type = "active";
};
soc_hot: soc-hot {
temperature = <80000>;
hysteresis = <5000>;
type = "hot";
};
};
cooling-maps {
map0 {
trip = <&soc_active1>;
cooling-device = <&pwmfan 0 1>;
};
map1 {
trip = <&soc_active2>;
cooling-device = <&pwmfan 1 2>;
};
map2 {
trip = <&soc_active3>;
cooling-device = <&pwmfan 2 3>;
};
map3 {
trip = <&soc_hot>;
cooling-device = <&pwmfan 3 4>;
};
};
};
board-thermal {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&mcu 1>;
trips {
board_active: board-active {
temperature = <75000>;
hysteresis = <8000>;
type = "active";
};
};
cooling-maps {
map4 {
trip = <&board_active>;
cooling-device = <&pwmfan 3 4>;
};
};
};
};
};
linux-7.2.3/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+494
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
*/
/dts-v1/;
#include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
#include <dt-bindings/clock/sophgo,sg2042-pll.h>
#include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/pinctrl-sg2042.h>
#include <dt-bindings/reset/sophgo,sg2042-reset.h>
#include "sg2042-cpus.dtsi"
/ {
compatible = "sophgo,sg2042";
#address-cells = <2>;
#size-cells = <2>;
dma-noncoherent;
distance-map {
compatible = "numa-distance-map-v1";
distance-matrix = <0 0 10>,
<0 1 15>,
<0 2 25>,
<0 3 30>,
<1 0 15>,
<1 1 10>,
<1 2 30>,
<1 3 25>,
<2 0 25>,
<2 1 30>,
<2 2 10>,
<2 3 15>,
<3 0 30>,
<3 1 25>,
<3 2 15>,
<3 3 10>;
};
aliases {
serial0 = &uart0;
};
cgi_main: oscillator0 {
compatible = "fixed-clock";
clock-output-names = "cgi_main";
#clock-cells = <0>;
};
cgi_dpll0: oscillator1 {
compatible = "fixed-clock";
clock-output-names = "cgi_dpll0";
#clock-cells = <0>;
};
cgi_dpll1: oscillator2 {
compatible = "fixed-clock";
clock-output-names = "cgi_dpll1";
#clock-cells = <0>;
};
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&intc>;
ranges;
spifmc0: spi@7000180000 {
compatible = "sophgo,sg2042-spifmc-nor";
reg = <0x70 0x00180000 0x0 0x1000000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkgen GATE_CLK_AHB_SF>;
interrupt-parent = <&intc>;
interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rstgen RST_SF0>;
status = "disabled";
};
spifmc1: spi@7002180000 {
compatible = "sophgo,sg2042-spifmc-nor";
reg = <0x70 0x02180000 0x0 0x1000000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkgen GATE_CLK_AHB_SF>;
interrupt-parent = <&intc>;
interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rstgen RST_SF1>;
status = "disabled";
};
i2c0: i2c@7030005000 {
compatible = "snps,designware-i2c";
reg = <0x70 0x30005000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkgen GATE_CLK_APB_I2C>;
clock-names = "ref";
clock-frequency = <100000>;
interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rstgen RST_I2C0>;
status = "disabled";
};
i2c1: i2c@7030006000 {
compatible = "snps,designware-i2c";
reg = <0x70 0x30006000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkgen GATE_CLK_APB_I2C>;
clock-names = "ref";
clock-frequency = <100000>;
interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rstgen RST_I2C1>;
status = "disabled";
};
i2c2: i2c@7030007000 {
compatible = "snps,designware-i2c";
reg = <0x70 0x30007000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkgen GATE_CLK_APB_I2C>;
clock-names = "ref";
clock-frequency = <100000>;
interrupts = <103 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rstgen RST_I2C2>;
status = "disabled";
};
i2c3: i2c@7030008000 {
compatible = "snps,designware-i2c";
reg = <0x70 0x30008000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkgen GATE_CLK_APB_I2C>;
clock-names = "ref";
clock-frequency = <100000>;
interrupts = <104 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rstgen RST_I2C3>;
status = "disabled";
};
gpio0: gpio@7030009000 {
compatible = "snps,dw-apb-gpio";
reg = <0x70 0x30009000 0x0 0x400>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkgen GATE_CLK_APB_GPIO>,
<&clkgen GATE_CLK_GPIO_DB>;
clock-names = "bus", "db";
port0a: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <96 IRQ_TYPE_LEVEL_HIGH>;
};
};
gpio1: gpio@703000a000 {
compatible = "snps,dw-apb-gpio";
reg = <0x70 0x3000a000 0x0 0x400>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkgen GATE_CLK_APB_GPIO>,
<&clkgen GATE_CLK_GPIO_DB>;
clock-names = "bus", "db";
port1a: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <97 IRQ_TYPE_LEVEL_HIGH>;
};
};
gpio2: gpio@703000b000 {
compatible = "snps,dw-apb-gpio";
reg = <0x70 0x3000b000 0x0 0x400>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkgen GATE_CLK_APB_GPIO>,
<&clkgen GATE_CLK_GPIO_DB>;
clock-names = "bus", "db";
port2a: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <98 IRQ_TYPE_LEVEL_HIGH>;
};
};
pwm: pwm@703000c000 {
compatible = "sophgo,sg2042-pwm";
reg = <0x70 0x3000c000 0x0 0x20>;
#pwm-cells = <3>;
clocks = <&clkgen GATE_CLK_APB_PWM>;
clock-names = "apb";
resets = <&rstgen RST_PWM>;
};
pllclk: clock-controller@70300100c0 {
compatible = "sophgo,sg2042-pll";
reg = <0x70 0x300100c0 0x0 0x40>;
clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>;
clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1";
#clock-cells = <1>;
};
msi: msi-controller@7030010304 {
compatible = "sophgo,sg2042-msi";
reg = <0x70 0x30010304 0x0 0x4>,
<0x70 0x30010300 0x0 0x4>;
reg-names = "clr", "doorbell";
msi-controller;
#msi-cells = <0>;
msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 16>;
};
rpgate: clock-controller@7030010368 {
compatible = "sophgo,sg2042-rpgate";
reg = <0x70 0x30010368 0x0 0x98>;
clocks = <&clkgen GATE_CLK_RP_CPU_NORMAL>;
clock-names = "rpgate";
#clock-cells = <1>;
};
pinctrl: pinctrl@7030011000 {
compatible = "sophgo,sg2042-pinctrl";
reg = <0x70 0x30011000 0x0 0x1000>;
};
clkgen: clock-controller@7030012000 {
compatible = "sophgo,sg2042-clkgen";
reg = <0x70 0x30012000 0x0 0x1000>;
clocks = <&pllclk MPLL_CLK>,
<&pllclk FPLL_CLK>,
<&pllclk DPLL0_CLK>,
<&pllclk DPLL1_CLK>;
clock-names = "mpll",
"fpll",
"dpll0",
"dpll1";
#clock-cells = <1>;
};
rstgen: reset-controller@7030013000 {
compatible = "sophgo,sg2042-reset";
reg = <0x00000070 0x30013000 0x00000000 0x0000000c>;
#reset-cells = <1>;
};
uart0: serial@7040000000 {
compatible = "snps,dw-apb-uart";
reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
clocks = <&clkgen GATE_CLK_UART_500M>,
<&clkgen GATE_CLK_APB_UART>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rstgen RST_UART0>;
status = "disabled";
};
spi0: spi@7040004000 {
compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi";
reg = <0x70 0x40004000 0x00 0x1000>;
clocks = <&clkgen GATE_CLK_APB_SPI>;
interrupt-parent = <&intc>;
interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
num-cs = <2>;
resets = <&rstgen RST_SPI0>;
status = "disabled";
};
spi1: spi@7040005000 {
compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi";
reg = <0x70 0x40005000 0x00 0x1000>;
clocks = <&clkgen GATE_CLK_APB_SPI>;
interrupt-parent = <&intc>;
interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
num-cs = <2>;
resets = <&rstgen RST_SPI1>;
status = "disabled";
};
gmac0: ethernet@7040026000 {
compatible = "sophgo,sg2042-dwmac", "snps,dwmac-5.00a";
reg = <0x70 0x40026000 0x0 0x4000>;
clocks = <&clkgen GATE_CLK_AXI_ETH0>,
<&clkgen GATE_CLK_PTP_REF_I_ETH0>,
<&clkgen GATE_CLK_TX_ETH0>;
clock-names = "stmmaceth", "ptp_ref", "tx";
dma-noncoherent;
interrupt-parent = <&intc>;
interrupts = <132 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
resets = <&rstgen RST_ETH0>;
reset-names = "stmmaceth";
snps,multicast-filter-bins = <0>;
snps,perfect-filter-entries = <1>;
snps,aal;
snps,tso;
snps,txpbl = <32>;
snps,rxpbl = <32>;
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
snps,axi-config = <&gmac0_stmmac_axi_setup>;
status = "disabled";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
gmac0_mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <8>;
queue0 {};
queue1 {};
queue2 {};
queue3 {};
queue4 {};
queue5 {};
queue6 {};
queue7 {};
};
gmac0_mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <8>;
queue0 {};
queue1 {};
queue2 {};
queue3 {};
queue4 {};
queue5 {};
queue6 {};
queue7 {};
};
gmac0_stmmac_axi_setup: stmmac-axi-config {
snps,blen = <16 8 4 0 0 0 0>;
snps,wr_osr_lmt = <1>;
snps,rd_osr_lmt = <2>;
};
};
emmc: mmc@704002a000 {
compatible = "sophgo,sg2042-dwcmshc";
reg = <0x70 0x4002a000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <134 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkgen GATE_CLK_EMMC_100M>,
<&clkgen GATE_CLK_AXI_EMMC>,
<&clkgen GATE_CLK_100K_EMMC>;
clock-names = "core",
"bus",
"timer";
status = "disabled";
};
sd: mmc@704002b000 {
compatible = "sophgo,sg2042-dwcmshc";
reg = <0x70 0x4002b000 0x0 0x1000>;
interrupt-parent = <&intc>;
interrupts = <136 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkgen GATE_CLK_SD_100M>,
<&clkgen GATE_CLK_AXI_SD>,
<&clkgen GATE_CLK_100K_SD>;
clock-names = "core",
"bus",
"timer";
status = "disabled";
};
pcie_rc0: pcie@7060000000 {
compatible = "sophgo,sg2042-pcie-host";
device_type = "pci";
reg = <0x70 0x60000000 0x0 0x00800000>,
<0x40 0x00000000 0x0 0x00001000>;
reg-names = "reg", "cfg";
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>,
<0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>,
<0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>,
<0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
<0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
bus-range = <0x0 0xff>;
vendor-id = <0x1f1c>;
device-id = <0x2042>;
cdns,no-bar-match-nbits = <48>;
dma-coherent;
msi-parent = <&msi>;
status = "disabled";
};
pcie_rc1: pcie@7060800000 {
compatible = "sophgo,sg2042-pcie-host";
device_type = "pci";
reg = <0x70 0x60800000 0x0 0x00800000>,
<0x44 0x00000000 0x0 0x00001000>;
reg-names = "reg", "cfg";
linux,pci-domain = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>,
<0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>,
<0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>,
<0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>,
<0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>;
bus-range = <0x0 0xff>;
vendor-id = <0x1f1c>;
device-id = <0x2042>;
cdns,no-bar-match-nbits = <48>;
dma-coherent;
msi-parent = <&msi>;
status = "disabled";
};
pcie_rc2: pcie@7062000000 {
compatible = "sophgo,sg2042-pcie-host";
device_type = "pci";
reg = <0x70 0x62000000 0x0 0x00800000>,
<0x48 0x00000000 0x0 0x00001000>;
reg-names = "reg", "cfg";
linux,pci-domain = <2>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>,
<0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>,
<0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>,
<0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>,
<0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>;
bus-range = <0x0 0xff>;
vendor-id = <0x1f1c>;
device-id = <0x2042>;
cdns,no-bar-match-nbits = <48>;
dma-coherent;
msi-parent = <&msi>;
status = "disabled";
};
pcie_rc3: pcie@7062800000 {
compatible = "sophgo,sg2042-pcie-host";
device_type = "pci";
reg = <0x70 0x62800000 0x0 0x00800000>,
<0x4c 0x00000000 0x0 0x00001000>;
reg-names = "reg", "cfg";
linux,pci-domain = <3>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>,
<0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>,
<0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>,
<0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>,
<0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>;
bus-range = <0x0 0xff>;
vendor-id = <0x1f1c>;
device-id = <0x2042>;
cdns,no-bar-match-nbits = <48>;
dma-coherent;
msi-parent = <&msi>;
status = "disabled";
};
};
};
linux-7.2.3/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
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linux-7.2.3/arch/riscv/boot/dts/sophgo/sg2044-reset.h
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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
* Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com>
*/
#ifndef _SG2044_RESET_H
#define _SG2044_RESET_H
#define RST_AP_SYS 0
#define RST_AP_SYS_CORE0 1
#define RST_AP_SYS_CORE1 2
#define RST_AP_SYS_CORE2 3
#define RST_AP_SYS_CORE3 4
#define RST_AP_PIC 5
#define RST_AP_TDT 6
#define RST_RP_PIC_TDT 7
#define RST_HSDMA 8
#define RST_SYSDMA 9
#define RST_EFUSE0 10
#define RST_EFUSE1 11
#define RST_RTC 12
#define RST_TIMER 13
#define RST_WDT 14
#define RST_AHB_ROM0 15
#define RST_AHB_ROM1 16
#define RST_I2C0 17
#define RST_I2C1 18
#define RST_I2C2 19
#define RST_I2C3 20
#define RST_GPIO0 21
#define RST_GPIO1 22
#define RST_GPIO2 23
#define RST_PWM 24
#define RST_AXI_SRAM0 25
#define RST_AXI_SRAM1 26
#define RST_SPIFMC0 27
#define RST_SPIFMC1 28
#define RST_MAILBOX 29
#define RST_ETH0 30
#define RST_EMMC 31
#define RST_SD 32
#define RST_UART0 33
#define RST_UART1 34
#define RST_UART2 35
#define RST_UART3 36
#define RST_SPI0 37
#define RST_SPI1 38
#define RST_MTLI 39
#define RST_DBG_I2C 40
#define RST_C2C0 41
#define RST_C2C1 42
#define RST_C2C2 43
#define RST_C2C3 44
#define RST_CXP 45
#define RST_DDR0 46
#define RST_DDR1 47
#define RST_DDR2 48
#define RST_DDR3 49
#define RST_DDR4 50
#define RST_DDR5 51
#define RST_DDR6 52
#define RST_DDR7 53
#define RST_DDR8 54
#define RST_DDR9 55
#define RST_DDR10 56
#define RST_DDR11 57
#define RST_DDR12 58
#define RST_DDR13 59
#define RST_DDR14 60
#define RST_DDR15 61
#define RST_BAR 62
#define RST_K2K 63
#define RST_CC_SYS_X1Y1 64
#define RST_CC_SYS_X1Y2 65
#define RST_CC_SYS_X1Y3 66
#define RST_CC_SYS_X1Y4 67
#define RST_CC_SYS_X0Y1 68
#define RST_CC_SYS_X0Y2 69
#define RST_CC_SYS_X0Y3 70
#define RST_CC_SYS_X0Y4 71
#define RST_SC_X1Y1 80
#define RST_SC_X1Y2 81
#define RST_SC_X1Y3 82
#define RST_SC_X1Y4 83
#define RST_SC_X0Y1 84
#define RST_SC_X0Y2 85
#define RST_SC_X0Y3 86
#define RST_SC_X0Y4 87
#define RST_RP_CLUSTER_X1Y1_S0 160
#define RST_RP_CLUSTER_X1Y1_S1 161
#define RST_RP_CLUSTER_X1Y2_S0 162
#define RST_RP_CLUSTER_X1Y2_S1 163
#define RST_RP_CLUSTER_X1Y3_S0 164
#define RST_RP_CLUSTER_X1Y3_S1 165
#define RST_RP_CLUSTER_X1Y4_S0 166
#define RST_RP_CLUSTER_X1Y4_S1 167
#define RST_RP_CLUSTER_X0Y1_W0 168
#define RST_RP_CLUSTER_X0Y1_W1 169
#define RST_RP_CLUSTER_X0Y2_W0 170
#define RST_RP_CLUSTER_X0Y2_W1 171
#define RST_RP_CLUSTER_X0Y3_W0 172
#define RST_RP_CLUSTER_X0Y3_W1 173
#define RST_RP_CLUSTER_X0Y4_W0 174
#define RST_RP_CLUSTER_X0Y4_W1 175
#define RST_TPSYS_X1Y1 180
#define RST_TPSYS_X1Y2 181
#define RST_TPSYS_X1Y3 182
#define RST_TPSYS_X1Y4 183
#define RST_TPSYS_X0Y1 184
#define RST_TPSYS_X0Y2 185
#define RST_TPSYS_X0Y3 186
#define RST_TPSYS_X0Y4 187
#define RST_SPACC 188
#define RST_PKA 189
#define RST_SE_TRNG 190
#define RST_SE_DBG 191
#define RST_SE_FAB_FW 192
#define RST_SE_CTRL 193
#define RST_MAILBOX0 194
#define RST_MAILBOX1 195
#define RST_MAILBOX2 196
#define RST_MAILBOX3 197
#define RST_INTC0 198
#define RST_INTC1 199
#define RST_INTC2 200
#define RST_INTC3 201
#endif /* _DT_BINDINGS_SG2044_RESET_H */
linux-7.2.3/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
+119
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@@ -0,0 +1,119 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com>
*/
/dts-v1/;
#include "sg2044.dtsi"
/ {
model = "Sophgo SG2044 SRD3-10";
compatible = "sophgo,srd3-10", "sophgo,sg2044";
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
};
chosen {
stdout-path = "serial1:115200n8";
};
};
&osc {
clock-frequency = <25000000>;
};
&emmc {
bus-width = <4>;
no-sdio;
no-sd;
non-removable;
wp-inverted;
status = "okay";
};
&gmac0 {
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
mdio {
phy0: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&porta 28 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <10000>;
rx-internal-delay-ps = <2050>;
};
};
};
&i2c1 {
status = "okay";
mcu: syscon@17 {
compatible = "sophgo,sg2044-hwmon-mcu", "sophgo,sg2042-hwmon-mcu";
reg = <0x17>;
#thermal-sensor-cells = <1>;
};
};
&msi {
status = "okay";
};
&pcie0 {
bus-range = <0x00 0xff>;
linux,pci-domain = <1>;
status = "okay";
};
&pcie1 {
bus-range = <0x00 0xff>;
linux,pci-domain = <0>;
status = "okay";
};
&pcie2 {
bus-range = <0x00 0xff>;
linux,pci-domain = <3>;
status = "okay";
};
&pcie3 {
bus-range = <0x00 0xff>;
linux,pci-domain = <2>;
status = "okay";
};
&pcie4 {
bus-range = <0x00 0xff>;
linux,pci-domain = <4>;
status = "okay";
};
&pwm {
status = "okay";
};
&sd {
bus-width = <4>;
no-sdio;
no-mmc;
wp-inverted;
status = "okay";
};
&uart0 {
/* for firmware */
status = "reserved";
};
&uart1 {
status = "okay";
};
linux-7.2.3/arch/riscv/boot/dts/sophgo/sg2044.dtsi
+585
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@@ -0,0 +1,585 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com>
*/
#include <dt-bindings/clock/sophgo,sg2044-pll.h>
#include <dt-bindings/clock/sophgo,sg2044-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-sg2044.h>
#include "sg2044-cpus.dtsi"
#include "sg2044-reset.h"
/ {
compatible = "sophgo,sg2044";
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0x00000010 0x00000000>;
};
osc: oscillator {
compatible = "fixed-clock";
clock-output-names = "osc";
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
pcie0: pcie@6c00000000 {
compatible = "sophgo,sg2044-pcie";
reg = <0x6c 0x00000000 0x0 0x00001000>,
<0x6c 0x00300000 0x0 0x00004000>,
<0x48 0x00000000 0x0 0x00001000>,
<0x6c 0x000c0000 0x0 0x00001000>;
reg-names = "dbi", "atu", "config", "app";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
clocks = <&clk CLK_GATE_PCIE_1G>;
clock-names = "core";
device_type = "pci";
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
<0 0 0 2 &pcie_intc0 1>,
<0 0 0 3 &pcie_intc0 2>,
<0 0 0 4 &pcie_intc0 3>;
msi-parent = <&msi>;
ranges = <0x01000000 0x0 0x00000000 0x48 0x10000000 0x0 0x00200000>,
<0x42000000 0x0 0x10000000 0x0 0x10000000 0x0 0x04000000>,
<0x02000000 0x0 0x14000000 0x0 0x14000000 0x0 0x04000000>,
<0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>,
<0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>;
status = "disabled";
pcie_intc0: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
};
};
pcie1: pcie@6c00400000 {
compatible = "sophgo,sg2044-pcie";
reg = <0x6c 0x00400000 0x0 0x00001000>,
<0x6c 0x00700000 0x0 0x00004000>,
<0x40 0x00000000 0x0 0x00001000>,
<0x6c 0x00780000 0x0 0x00001000>;
reg-names = "dbi", "atu", "config", "app";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
clocks = <&clk CLK_GATE_PCIE_1G>;
clock-names = "core";
device_type = "pci";
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
<0 0 0 2 &pcie_intc1 1>,
<0 0 0 3 &pcie_intc1 2>,
<0 0 0 4 &pcie_intc1 3>;
msi-parent = <&msi>;
ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00200000>,
<0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x04000000>,
<0x02000000 0x0 0x04000000 0x0 0x04000000 0x0 0x04000000>,
<0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
<0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
status = "disabled";
pcie_intc1: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
};
};
pcie2: pcie@6c04000000 {
compatible = "sophgo,sg2044-pcie";
reg = <0x6c 0x04000000 0x0 0x00001000>,
<0x6c 0x04300000 0x0 0x00004000>,
<0x58 0x00000000 0x0 0x00001000>,
<0x6c 0x040c0000 0x0 0x00001000>;
reg-names = "dbi", "atu", "config", "app";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
clocks = <&clk CLK_GATE_PCIE_1G>;
clock-names = "core";
device_type = "pci";
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc2 0>,
<0 0 0 2 &pcie_intc2 1>,
<0 0 0 3 &pcie_intc2 2>,
<0 0 0 4 &pcie_intc2 3>;
msi-parent = <&msi>;
ranges = <0x01000000 0x0 0x00000000 0x58 0x10000000 0x0 0x00200000>,
<0x42000000 0x0 0x30000000 0x0 0x30000000 0x0 0x04000000>,
<0x02000000 0x0 0x34000000 0x0 0x34000000 0x0 0x04000000>,
<0x43000000 0x5a 0x00000000 0x5a 0x00000000 0x2 0x00000000>,
<0x03000000 0x59 0x00000000 0x59 0x00000000 0x1 0x00000000>;
status = "disabled";
pcie_intc2: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <74 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
};
};
pcie3: pcie@6c04400000 {
compatible = "sophgo,sg2044-pcie";
reg = <0x6c 0x04400000 0x0 0x00001000>,
<0x6c 0x04700000 0x0 0x00004000>,
<0x50 0x00000000 0x0 0x00001000>,
<0x6c 0x04780000 0x0 0x00001000>;
reg-names = "dbi", "atu", "config", "app";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
clocks = <&clk CLK_GATE_PCIE_1G>;
clock-names = "core";
device_type = "pci";
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc3 0>,
<0 0 0 2 &pcie_intc3 1>,
<0 0 0 3 &pcie_intc3 2>,
<0 0 0 4 &pcie_intc3 3>;
msi-parent = <&msi>;
ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>,
<0x42000000 0x0 0x20000000 0x0 0x20000000 0x0 0x04000000>,
<0x02000000 0x0 0x24000000 0x0 0x24000000 0x0 0x04000000>,
<0x43000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>,
<0x03000000 0x51 0x00000000 0x51 0x00000000 0x1 0x00000000>;
status = "disabled";
pcie_intc3: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
};
};
pcie4: pcie@6c08400000 {
compatible = "sophgo,sg2044-pcie";
reg = <0x6c 0x08400000 0x0 0x00001000>,
<0x6c 0x08700000 0x0 0x00004000>,
<0x60 0x00000000 0x0 0x00001000>,
<0x6c 0x08780000 0x0 0x00001000>;
reg-names = "dbi", "atu", "config", "app";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
clocks = <&clk CLK_GATE_PCIE_1G>;
clock-names = "core";
device_type = "pci";
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc4 0>,
<0 0 0 2 &pcie_intc4 1>,
<0 0 0 3 &pcie_intc4 2>,
<0 0 0 4 &pcie_intc4 3>;
msi-parent = <&msi>;
ranges = <0x01000000 0x0 0x00000000 0x60 0x10000000 0x0 0x00200000>,
<0x42000000 0x0 0x40000000 0x0 0x40000000 0x0 0x04000000>,
<0x02000000 0x0 0x44000000 0x0 0x44000000 0x0 0x04000000>,
<0x43000000 0x62 0x00000000 0x62 0x00000000 0x2 0x00000000>,
<0x03000000 0x61 0x00000000 0x61 0x00000000 0x1 0x00000000>;
status = "disabled";
pcie_intc4: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
};
};
msi: msi-controller@6d50000000 {
compatible = "sophgo,sg2044-msi";
reg = <0x6d 0x50000000 0x0 0x800>,
<0x0 0x7ee00000 0x0 0x40>;
reg-names = "clr", "doorbell";
#msi-cells = <0>;
msi-controller;
msi-ranges = <&intc 352 IRQ_TYPE_EDGE_RISING 512>;
status = "disabled";
};
spifmc0: spi@7001000000 {
compatible = "sophgo,sg2044-spifmc-nor";
reg = <0x70 0x01000000 0x0 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_GATE_AHB_SPIFMC>;
interrupt-parent = <&intc>;
interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_SPIFMC0>;
status = "disabled";
};
spifmc1: spi@7005000000 {
compatible = "sophgo,sg2044-spifmc-nor";
reg = <0x70 0x05000000 0x0 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_GATE_AHB_SPIFMC>;
interrupt-parent = <&intc>;
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_SPIFMC1>;
status = "disabled";
};
dmac0: dma-controller@7020000000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x70 0x20000000 0x0 0x10000>;
#dma-cells = <1>;
clock-names = "core-clk", "cfgr-clk";
clocks = <&clk CLK_GATE_SYSDMA_AXI>,
<&clk CLK_GATE_SYSDMA_AXI>;
dma-noncoherent;
interrupt-parent = <&intc>;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <8>;
snps,priority = <0 1 2 3 4 5 6 7>;
snps,block-size = <4096 4096 4096 4096
4096 4096 4096 4096>;
snps,dma-masters = <2>;
snps,data-width = <2>;
snps,axi-max-burst-len = <4>;
status = "disabled";
};
uart0: serial@7030000000 {
compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
reg = <0x70 0x30000000 0x0 0x1000>;
clock-frequency = <500000000>;
clocks = <&clk CLK_GATE_UART_500M>,
<&clk CLK_GATE_APB_UART>;
clock-names = "baudclk", "apb_pclk";
interrupt-parent = <&intc>;
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst RST_UART0>;
status = "disabled";
};
uart1: serial@7030001000 {
compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
reg = <0x70 0x30001000 0x0 0x1000>;
clock-frequency = <500000000>;
clocks = <&clk CLK_GATE_UART_500M>,
<&clk CLK_GATE_APB_UART>;
clock-names = "baudclk", "apb_pclk";
interrupt-parent = <&intc>;
interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst RST_UART1>;
status = "disabled";
};
uart2: serial@7030002000 {
compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
reg = <0x70 0x30002000 0x0 0x1000>;
clock-frequency = <500000000>;
clocks = <&clk CLK_GATE_UART_500M>,
<&clk CLK_GATE_APB_UART>;
clock-names = "baudclk", "apb_pclk";
interrupt-parent = <&intc>;
interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst RST_UART2>;
status = "disabled";
};
uart3: serial@7030003000 {
compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
reg = <0x70 0x30003000 0x0 0x1000>;
clock-frequency = <500000000>;
clocks = <&clk CLK_GATE_UART_500M>,
<&clk CLK_GATE_APB_UART>;
clock-names = "baudclk", "apb_pclk";
interrupt-parent = <&intc>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst RST_UART3>;
status = "disabled";
};
gmac0: ethernet@7030006000 {
compatible = "sophgo,sg2044-dwmac", "snps,dwmac-5.30a";
reg = <0x70 0x30006000 0x0 0x4000>;
clocks = <&clk CLK_GATE_AXI_ETH0>,
<&clk CLK_GATE_PTP_REF_I_ETH0>,
<&clk CLK_GATE_TX_ETH0>;
clock-names = "stmmaceth", "ptp_ref", "tx";
dma-noncoherent;
interrupt-parent = <&intc>;
interrupts = <296 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
resets = <&rst RST_ETH0>;
reset-names = "stmmaceth";
snps,multicast-filter-bins = <0>;
snps,perfect-filter-entries = <1>;
snps,aal;
snps,tso;
snps,txpbl = <32>;
snps,rxpbl = <32>;
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
snps,axi-config = <&gmac0_stmmac_axi_setup>;
status = "disabled";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
gmac0_mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <8>;
snps,rx-sched-wsp;
queue0 {};
queue1 {};
queue2 {};
queue3 {};
queue4 {};
queue5 {};
queue6 {};
queue7 {};
};
gmac0_mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <8>;
queue0 {};
queue1 {};
queue2 {};
queue3 {};
queue4 {};
queue5 {};
queue6 {};
queue7 {};
};
gmac0_stmmac_axi_setup: stmmac-axi-config {
snps,blen = <16 8 4 0 0 0 0>;
snps,wr_osr_lmt = <1>;
snps,rd_osr_lmt = <2>;
};
};
emmc: mmc@703000a000 {
compatible = "sophgo,sg2044-dwcmshc", "sophgo,sg2042-dwcmshc";
reg = <0x70 0x3000a000 0x0 0x1000>;
clocks = <&clk CLK_GATE_EMMC>,
<&clk CLK_GATE_AXI_EMMC>,
<&clk CLK_GATE_EMMC_100K>;
clock-names = "core", "bus", "timer";
interrupt-parent = <&intc>;
interrupts = <298 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sd: mmc@703000b000 {
compatible = "sophgo,sg2044-dwcmshc", "sophgo,sg2042-dwcmshc";
reg = <0x70 0x3000b000 0x0 0x1000>;
clocks = <&clk CLK_GATE_SD>,
<&clk CLK_GATE_AXI_SD>,
<&clk CLK_GATE_SD_100K>;
clock-names = "core", "bus", "timer";
interrupt-parent = <&intc>;
interrupts = <300 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
i2c0: i2c@7040005000 {
compatible = "sophgo,sg2044-i2c", "snps,designware-i2c";
reg = <0x70 0x40005000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
clocks = <&clk CLK_GATE_APB_I2C>;
clock-names = "ref";
interrupt-parent = <&intc>;
interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_I2C0>;
status = "disabled";
};
i2c1: i2c@7040006000 {
compatible = "sophgo,sg2044-i2c", "snps,designware-i2c";
reg = <0x70 0x40006000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
clocks = <&clk CLK_GATE_APB_I2C>;
clock-names = "ref";
interrupt-parent = <&intc>;
interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_I2C1>;
status = "disabled";
};
i2c2: i2c@7040007000 {
compatible = "sophgo,sg2044-i2c", "snps,designware-i2c";
reg = <0x70 0x40007000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
clocks = <&clk CLK_GATE_APB_I2C>;
clock-names = "ref";
interrupt-parent = <&intc>;
interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_I2C2>;
status = "disabled";
};
i2c3: i2c@7040008000 {
compatible = "sophgo,sg2044-i2c", "snps,designware-i2c";
reg = <0x70 0x40008000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
clocks = <&clk CLK_GATE_APB_I2C>;
clock-names = "ref";
interrupt-parent = <&intc>;
interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_I2C3>;
status = "disabled";
};
gpio0: gpio@7040009000 {
compatible = "snps,dw-apb-gpio";
reg = <0x70 0x40009000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_GATE_APB_GPIO>,
<&clk CLK_GATE_GPIO_DB>;
clock-names = "bus", "db";
resets = <&rst RST_GPIO0>;
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
};
};
gpio1: gpio@704000a000 {
compatible = "snps,dw-apb-gpio";
reg = <0x70 0x4000a000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_GATE_APB_GPIO>,
<&clk CLK_GATE_GPIO_DB>;
clock-names = "bus", "db";
resets = <&rst RST_GPIO1>;
portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
};
};
gpio2: gpio@704000b000 {
compatible = "snps,dw-apb-gpio";
reg = <0x70 0x4000b000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk CLK_GATE_APB_GPIO>,
<&clk CLK_GATE_GPIO_DB>;
clock-names = "bus", "db";
resets = <&rst RST_GPIO2>;
portc: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
};
};
pwm: pwm@704000c000 {
compatible = "sophgo,sg2044-pwm";
reg = <0x70 0x4000c000 0x0 0x1000>;
#pwm-cells = <3>;
clocks = <&clk CLK_GATE_APB_PWM>;
clock-names = "apb";
resets = <&rst RST_PWM>;
status = "disabled";
};
syscon: syscon@7050000000 {
compatible = "sophgo,sg2044-top-syscon", "syscon";
reg = <0x70 0x50000000 0x0 0x1000>;
#clock-cells = <1>;
clocks = <&osc>;
};
pinctrl: pinctrl@7050001000 {
compatible = "sophgo,sg2044-pinctrl";
reg = <0x70 0x50001000 0x0 0x1000>;
};
clk: clock-controller@7050002000 {
compatible = "sophgo,sg2044-clk";
reg = <0x70 0x50002000 0x0 0x1000>;
#clock-cells = <1>;
clocks = <&syscon CLK_FPLL0>, <&syscon CLK_FPLL1>,
<&syscon CLK_FPLL2>, <&syscon CLK_DPLL0>,
<&syscon CLK_DPLL1>, <&syscon CLK_DPLL2>,
<&syscon CLK_DPLL3>, <&syscon CLK_DPLL4>,
<&syscon CLK_DPLL5>, <&syscon CLK_DPLL6>,
<&syscon CLK_DPLL7>, <&syscon CLK_MPLL0>,
<&syscon CLK_MPLL1>, <&syscon CLK_MPLL2>,
<&syscon CLK_MPLL3>, <&syscon CLK_MPLL4>,
<&syscon CLK_MPLL5>;
clock-names = "fpll0", "fpll1", "fpll2", "dpll0",
"dpll1", "dpll2", "dpll3", "dpll4",
"dpll5", "dpll6", "dpll7", "mpll0",
"mpll1", "mpll2", "mpll3", "mpll4",
"mpll5";
};
rst: reset-controller@7050003000 {
compatible = "sophgo,sg2044-reset",
"sophgo,sg2042-reset";
reg = <0x70 0x50003000 0x0 0x1000>;
#reset-cells = <1>;
};
};
};