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lastdragon
2026-09-06 12:53:21 -06:00
parent 662efe3c2a
commit ad2088d178
94853 changed files with 43200404 additions and 0 deletions
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linux-7.2.3/drivers/pinctrl/aspeed/Kconfig
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# SPDX-License-Identifier: GPL-2.0-only
config PINCTRL_ASPEED
bool
depends on (ARCH_ASPEED || COMPILE_TEST) && OF
select MFD_SYSCON
select PINMUX
select PINCONF
select GENERIC_PINCONF
select REGMAP_MMIO
config PINCTRL_ASPEED_G4
bool "Aspeed G4 SoC pin control"
depends on (MACH_ASPEED_G4 || COMPILE_TEST) && OF
select PINCTRL_ASPEED
help
Say Y here to enable pin controller support for Aspeed's 4th
generation SoCs. GPIO is provided by a separate GPIO driver.
config PINCTRL_ASPEED_G5
bool "Aspeed G5 SoC pin control"
depends on (MACH_ASPEED_G5 || COMPILE_TEST) && OF
select PINCTRL_ASPEED
help
Say Y here to enable pin controller support for Aspeed's 5th
generation SoCs. GPIO is provided by a separate GPIO driver.
config PINCTRL_ASPEED_G6
bool "Aspeed G6 SoC pin control"
depends on (MACH_ASPEED_G6 || COMPILE_TEST) && OF
select PINCTRL_ASPEED
help
Say Y here to enable pin controller support for Aspeed's 6th
generation SoCs. GPIO is provided by a separate GPIO driver.
config PINCTRL_ASPEED_G7_SOC0
bool "Aspeed G7 SoC pin control"
depends on (ARCH_ASPEED || COMPILE_TEST) && OF
select PINCTRL_ASPEED
help
Say Y here to enable pin controller support for the SoC0 instance
of Aspeed's 7th generation SoCs. GPIO is provided by a separate
GPIO driver.
config PINCTRL_ASPEED_G7_SOC1
bool "Aspeed G7 SoC1 pin control"
depends on (ARCH_ASPEED || COMPILE_TEST) && OF
select MFD_SYSCON
select PINMUX
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
select REGMAP_MMIO
help
Say Y here to enable pin controller support for the SoC1 instance
of Aspeed's 7th generation SoCs. GPIO is provided by a separate
GPIO driver.
linux-7.2.3/drivers/pinctrl/aspeed/Makefile
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# SPDX-License-Identifier: GPL-2.0-only
# Aspeed pinctrl support
ccflags-y += -Woverride-init
obj-$(CONFIG_PINCTRL_ASPEED) += pinctrl-aspeed.o pinmux-aspeed.o
obj-$(CONFIG_PINCTRL_ASPEED_G4) += pinctrl-aspeed-g4.o
obj-$(CONFIG_PINCTRL_ASPEED_G5) += pinctrl-aspeed-g5.o
obj-$(CONFIG_PINCTRL_ASPEED_G6) += pinctrl-aspeed-g6.o
obj-$(CONFIG_PINCTRL_ASPEED_G7_SOC0) += pinctrl-aspeed-g7-soc0.o
obj-$(CONFIG_PINCTRL_ASPEED_G7_SOC1) += pinctrl-aspeed-g7-soc1.o
linux-7.2.3/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
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linux-7.2.3/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
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linux-7.2.3/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
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linux-7.2.3/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c
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// SPDX-License-Identifier: GPL-2.0
#include <linux/bitops.h>
#include <linux/bits.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "pinctrl-aspeed.h"
#include "pinmux-aspeed.h"
#include "../pinctrl-utils.h"
#define SCU200 0x200 /* System Reset Control #1 */
#define SCU010 0x010 /* Hardware Strap Register */
#define SCU400 0x400 /* Multi-function Pin Control #1 */
#define SCU404 0x404 /* Multi-function Pin Control #2 */
#define SCU408 0x408 /* Multi-function Pin Control #3 */
#define SCU40C 0x40C /* Multi-function Pin Control #3 */
#define SCU410 0x410 /* USB Multi-function Control Register */
#define SCU414 0x414 /* VGA Function Control Register */
#define SCU480 0x480 /* GPIO18A0 IO Control Register */
#define SCU484 0x484 /* GPIO18A1 IO Control Register */
#define SCU488 0x488 /* GPIO18A2 IO Control Register */
#define SCU48C 0x48c /* GPIO18A3 IO Control Register */
#define SCU490 0x490 /* GPIO18A4 IO Control Register */
#define SCU494 0x494 /* GPIO18A5 IO Control Register */
#define SCU498 0x498 /* GPIO18A6 IO Control Register */
#define SCU49C 0x49c /* GPIO18A7 IO Control Register */
#define SCU4A0 0x4A0 /* GPIO18B0 IO Control Register */
#define SCU4A4 0x4A4 /* GPIO18B1 IO Control Register */
#define SCU4A8 0x4A8 /* GPIO18B2 IO Control Register */
#define SCU4AC 0x4AC /* GPIO18B3 IO Control Register */
enum {
AC14,
AE15,
AD14,
AE14,
AF14,
AB13,
AB14,
AF15,
AF13,
AC13,
AD13,
AE13,
JTAG_PORT,
PCIERC0_PERST,
PCIERC1_PERST,
PORTA_MODE,
PORTA_U2,
PORTB_MODE,
PORTB_U2,
PORTA_U2_PHY,
PORTB_U2_PHY,
PORTA_U3,
PORTB_U3,
PORTA_U3_PHY,
PORTB_U3_PHY,
};
SIG_EXPR_LIST_DECL_SEMG(AC14, EMMCCLK, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 0));
SIG_EXPR_LIST_DECL_SEMG(AC14, VB1CS, VB1, VB, SIG_DESC_SET(SCU404, 0));
PIN_DECL_2(AC14, GPIO18A0, EMMCCLK, VB1CS);
SIG_EXPR_LIST_DECL_SEMG(AE15, EMMCCMD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 1));
SIG_EXPR_LIST_DECL_SEMG(AE15, VB1CK, VB1, VB, SIG_DESC_SET(SCU404, 1));
PIN_DECL_2(AE15, GPIO18A1, EMMCCMD, VB1CK);
SIG_EXPR_LIST_DECL_SEMG(AD14, EMMCDAT0, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 2));
SIG_EXPR_LIST_DECL_SEMG(AD14, VB1MOSI, VB1, VB, SIG_DESC_SET(SCU404, 2));
PIN_DECL_2(AD14, GPIO18A2, EMMCDAT0, VB1MOSI);
SIG_EXPR_LIST_DECL_SEMG(AE14, EMMCDAT1, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 3));
SIG_EXPR_LIST_DECL_SEMG(AE14, VB1MISO, VB1, VB, SIG_DESC_SET(SCU404, 3));
PIN_DECL_2(AE14, GPIO18A3, EMMCDAT1, VB1MISO);
SIG_EXPR_LIST_DECL_SEMG(AF14, EMMCDAT2, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 4));
PIN_DECL_1(AF14, GPIO18A4, EMMCDAT2);
SIG_EXPR_LIST_DECL_SEMG(AB13, EMMCDAT3, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 5));
PIN_DECL_1(AB13, GPIO18A5, EMMCDAT3);
SIG_EXPR_LIST_DECL_SEMG(AB14, EMMCCDN, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 6));
SIG_EXPR_LIST_DECL_SEMG(AB14, VB0CS, VB0, VB, SIG_DESC_SET(SCU010, 17));
PIN_DECL_2(AB14, GPIO18A6, EMMCCDN, VB0CS);
SIG_EXPR_LIST_DECL_SEMG(AF15, EMMCWPN, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 7));
SIG_EXPR_LIST_DECL_SEMG(AF15, VB0CK, VB0, VB, SIG_DESC_SET(SCU010, 17));
PIN_DECL_2(AF15, GPIO18A7, EMMCWPN, VB0CK);
SIG_EXPR_LIST_DECL_SESG(AF13, TSPRSTN, TSPRSTN, SIG_DESC_SET(SCU010, 9));
SIG_EXPR_LIST_DECL_SEMG(AF13, EMMCDAT4, EMMCG8, EMMC, SIG_DESC_SET(SCU400, 8));
SIG_EXPR_LIST_DECL_SEMG(AF13, VB0MOSI, VB0, VB, SIG_DESC_SET(SCU010, 17));
PIN_DECL_3(AF13, GPIO18B0, TSPRSTN, EMMCDAT4, VB0MOSI);
SIG_EXPR_LIST_DECL_SESG(AC13, UFSCLKI, UFSCLKI, SIG_DESC_SET(SCU010, 19));
SIG_EXPR_LIST_DECL_SEMG(AC13, EMMCDAT5, EMMCG8, EMMC, SIG_DESC_SET(SCU400, 9));
SIG_EXPR_LIST_DECL_SEMG(AC13, VB0MISO, VB0, VB, SIG_DESC_SET(SCU010, 17));
PIN_DECL_3(AC13, GPIO18B1, UFSCLKI, EMMCDAT5, VB0MISO);
SIG_EXPR_LIST_DECL_SEMG(AD13, EMMCDAT6, EMMCG8, EMMC, SIG_DESC_SET(SCU400, 10));
SIG_EXPR_LIST_DECL_SESG(AD13, DDCCLK, VGADDC, SIG_DESC_SET(SCU404, 10));
PIN_DECL_2(AD13, GPIO18B2, EMMCDAT6, DDCCLK);
SIG_EXPR_LIST_DECL_SEMG(AE13, EMMCDAT7, EMMCG8, EMMC, SIG_DESC_SET(SCU400, 11));
SIG_EXPR_LIST_DECL_SESG(AE13, DDCDAT, VGADDC, SIG_DESC_SET(SCU404, 11));
PIN_DECL_2(AE13, GPIO18B3, EMMCDAT7, DDCDAT);
GROUP_DECL(EMMCG1, AC14, AE15, AD14);
GROUP_DECL(EMMCG4, AC14, AE15, AD14, AE14, AF14, AB13);
GROUP_DECL(EMMCG8, AC14, AE15, AD14, AE14, AF14, AB13, AF13, AC13, AD13, AE13);
GROUP_DECL(EMMCWPN, AF15);
GROUP_DECL(EMMCCDN, AB14);
FUNC_DECL_(EMMC, "EMMCG1", "EMMCG4", "EMMCG8", "EMMCWPN", "EMMCCDN");
GROUP_DECL(VB1, AC14, AE15, AD14, AE14);
GROUP_DECL(VB0, AF15, AB14, AF13, AC13);
FUNC_DECL_2(VB, VB1, VB0);
FUNC_GROUP_DECL(TSPRSTN, AF13);
FUNC_GROUP_DECL(UFSCLKI, AC13);
FUNC_GROUP_DECL(VGADDC, AD13, AE13);
/* JTAG Port Selection */
#define JTAG_PORT_PSP_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x0, 0 }
#define JTAG_PORT_SSP_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x41, 0 }
#define JTAG_PORT_TSP_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x42, 0 }
#define JTAG_PORT_DDR_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x43, 0 }
#define JTAG_PORT_USB3A_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x44, 0 }
#define JTAG_PORT_USB3B_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x45, 0 }
#define JTAG_PORT_PCIEA_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x46, 0 }
#define JTAG_PORT_PCIEB_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x47, 0 }
#define JTAG_PORT_JTAGM0_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x8, 0 }
SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGPSP, JTAG0, JTAGPSP, JTAG_PORT_PSP_DESC);
SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGSSP, JTAG0, JTAGSSP, JTAG_PORT_SSP_DESC);
SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGTSP, JTAG0, JTAGTSP, JTAG_PORT_TSP_DESC);
SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGDDR, JTAG0, JTAGDDR, JTAG_PORT_DDR_DESC);
SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGUSB3A, JTAG0, JTAGUSB3A, JTAG_PORT_USB3A_DESC);
SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGUSB3B, JTAG0, JTAGUSB3B, JTAG_PORT_USB3B_DESC);
SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGPCIEA, JTAG0, JTAGPCIEA, JTAG_PORT_PCIEA_DESC);
SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGPCIEB, JTAG0, JTAGPCIEB, JTAG_PORT_PCIEB_DESC);
SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGM0, JTAG0, JTAGM0, JTAG_PORT_JTAGM0_DESC);
PIN_DECL_(JTAG_PORT, SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGPSP), SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGSSP),
SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGTSP), SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGDDR),
SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGUSB3A), SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGUSB3B),
SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGPCIEA), SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGPCIEB),
SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGM0));
GROUP_DECL(JTAG0, JTAG_PORT);
FUNC_DECL_1(JTAGPSP, JTAG0);
FUNC_DECL_1(JTAGSSP, JTAG0);
FUNC_DECL_1(JTAGTSP, JTAG0);
FUNC_DECL_1(JTAGDDR, JTAG0);
FUNC_DECL_1(JTAGUSB3A, JTAG0);
FUNC_DECL_1(JTAGUSB3B, JTAG0);
FUNC_DECL_1(JTAGPCIEA, JTAG0);
FUNC_DECL_1(JTAGPCIEB, JTAG0);
FUNC_DECL_1(JTAGM0, JTAG0);
/* PCIe Reset Control */
SIG_EXPR_LIST_DECL_SESG(PCIERC0_PERST, PCIERC0PERST, PCIERC0PERST, SIG_DESC_SET(SCU200, 21));
PIN_DECL_(PCIERC0_PERST, SIG_EXPR_LIST_PTR(PCIERC0_PERST, PCIERC0PERST));
FUNC_GROUP_DECL(PCIERC0PERST, PCIERC0_PERST);
SIG_EXPR_LIST_DECL_SESG(PCIERC1_PERST, PCIERC1PERST, PCIERC1PERST, SIG_DESC_SET(SCU200, 19));
PIN_DECL_(PCIERC1_PERST, SIG_EXPR_LIST_PTR(PCIERC1_PERST, PCIERC1PERST));
FUNC_GROUP_DECL(PCIERC1PERST, PCIERC1_PERST);
#define PORTA_MODE_HPD0_DESC { ASPEED_IP_SCU, SCU410, GENMASK(25, 24), 0, 0 }
#define PORTA_MODE_D0_DESC { ASPEED_IP_SCU, SCU410, GENMASK(25, 24), 1, 0 }
#define PORTA_MODE_H_DESC { ASPEED_IP_SCU, SCU410, GENMASK(25, 24), 2, 0 }
#define PORTA_MODE_HP_DESC { ASPEED_IP_SCU, SCU410, GENMASK(25, 24), 3, 0 }
SIG_EXPR_LIST_DECL_SEMG(PORTA_MODE, USB2AHPD0, USB2AH, USB2AHPD0, PORTA_MODE_HPD0_DESC);
SIG_EXPR_LIST_DECL_SEMG(PORTA_MODE, USB2AH, USB2AHAP, USB2AH, PORTA_MODE_H_DESC);
SIG_EXPR_LIST_DECL_SEMG(PORTA_MODE, USB2AHP, USB2AHAP, USB2AHP, PORTA_MODE_HP_DESC);
SIG_EXPR_LIST_DECL_SEMG(PORTA_MODE, USB2AD0, USB2AHAP, USB2AD0, PORTA_MODE_D0_DESC);
PIN_DECL_(PORTA_MODE, SIG_EXPR_LIST_PTR(PORTA_MODE, USB2AHPD0),
SIG_EXPR_LIST_PTR(PORTA_MODE, USB2AH), SIG_EXPR_LIST_PTR(PORTA_MODE, USB2AHP),
SIG_EXPR_LIST_PTR(PORTA_MODE, USB2AD0));
#define PORTA_U2_XHD_DESC { ASPEED_IP_SCU, SCU410, GENMASK(3, 2), 0, 0 }
#define PORTA_U2_D1_DESC { ASPEED_IP_SCU, SCU410, GENMASK(3, 2), 1, 0 }
#define PORTA_U2_XH_DESC { ASPEED_IP_SCU, SCU410, GENMASK(3, 2), 2, 0 }
#define PORTA_U2_XH2E_DESC { ASPEED_IP_SCU, SCU410, GENMASK(3, 2), 3, 0 }
SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXHD1, USB2A, USB2AXHD1, PORTA_U2_XHD_DESC,
SIG_DESC_SET(SCU410, 9));
SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXHPD1, USB2A, USB2AXHPD1, PORTA_U2_XHD_DESC,
SIG_DESC_CLEAR(SCU410, 9));
SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXH, USB2AAP, USB2AXH, PORTA_U2_XH_DESC,
SIG_DESC_SET(SCU410, 9));
SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXHP, USB2AAP, USB2AXHP, PORTA_U2_XH_DESC,
SIG_DESC_CLEAR(SCU410, 9));
SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXH2B, USB2ABP, USB2AXH2B, PORTA_U2_XH2E_DESC,
SIG_DESC_SET(SCU410, 9));
SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXHP2B, USB2ABP, USB2AXHP2B, PORTA_U2_XH2E_DESC,
SIG_DESC_CLEAR(SCU410, 9));
SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AD1, USB2ADAP, USB2AD1, PORTA_U2_D1_DESC);
PIN_DECL_(PORTA_U2, SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXHD1), SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXHPD1),
SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXH), SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXHP),
SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXH2B), SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXHP2B),
SIG_EXPR_LIST_PTR(PORTA_U2, USB2AD1));
#define PORTB_MODE_HPD0_DESC { ASPEED_IP_SCU, SCU410, GENMASK(29, 28), 0, 0 }
#define PORTB_MODE_D0_DESC { ASPEED_IP_SCU, SCU410, GENMASK(29, 28), 1, 0 }
#define PORTB_MODE_H_DESC { ASPEED_IP_SCU, SCU410, GENMASK(29, 28), 2, 0 }
#define PORTB_MODE_HP_DESC { ASPEED_IP_SCU, SCU410, GENMASK(29, 28), 3, 0 }
SIG_EXPR_LIST_DECL_SEMG(PORTB_MODE, USB2BHPD0, USB2BH, USB2BHPD0, PORTB_MODE_HPD0_DESC);
SIG_EXPR_LIST_DECL_SEMG(PORTB_MODE, USB2BH, USB2BHBP, USB2BH, PORTB_MODE_H_DESC);
SIG_EXPR_LIST_DECL_SEMG(PORTB_MODE, USB2BHP, USB2BHBP, USB2BHP, PORTB_MODE_HP_DESC);
SIG_EXPR_LIST_DECL_SEMG(PORTB_MODE, USB2BD0, USB2BHBP, USB2BD0, PORTB_MODE_D0_DESC);
PIN_DECL_(PORTB_MODE, SIG_EXPR_LIST_PTR(PORTB_MODE, USB2BHPD0),
SIG_EXPR_LIST_PTR(PORTB_MODE, USB2BH), SIG_EXPR_LIST_PTR(PORTB_MODE, USB2BHP),
SIG_EXPR_LIST_PTR(PORTB_MODE, USB2BD0));
#define PORTB_U2_XHD_DESC { ASPEED_IP_SCU, SCU410, GENMASK(7, 6), 0, 0 }
#define PORTB_U2_D1_DESC { ASPEED_IP_SCU, SCU410, GENMASK(7, 6), 1, 0 }
#define PORTB_U2_XH_DESC { ASPEED_IP_SCU, SCU410, GENMASK(7, 6), 2, 0 }
#define PORTB_U2_XH2E_DESC { ASPEED_IP_SCU, SCU410, GENMASK(7, 6), 3, 0 }
SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXHD1, USB2B, USB2BXHD1, PORTB_U2_XHD_DESC,
SIG_DESC_SET(SCU410, 10));
SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXHPD1, USB2B, USB2BXHPD1, PORTB_U2_XHD_DESC,
SIG_DESC_CLEAR(SCU410, 10));
SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXH, USB2BBP, USB2BXH, PORTB_U2_XH_DESC,
SIG_DESC_SET(SCU410, 10));
SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXHP, USB2BBP, USB2BXHP, PORTB_U2_XH_DESC,
SIG_DESC_CLEAR(SCU410, 10));
SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXH2A, USB2BAP, USB2BXH2A, PORTB_U2_XH2E_DESC,
SIG_DESC_SET(SCU410, 10));
SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXHP2A, USB2BAP, USB2BXHP2A, PORTB_U2_XH2E_DESC,
SIG_DESC_CLEAR(SCU410, 10));
SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BD1, USB2BDBP, USB2BD1, PORTB_U2_D1_DESC);
PIN_DECL_(PORTB_U2, SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXHD1), SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXHPD1),
SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXH), SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXHP),
SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXH2A), SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXHP2A),
SIG_EXPR_LIST_PTR(PORTB_U2, USB2BD1));
/*
* USB2 virtual PHY pins.
*
* PORTA_U2_PHY and PORTB_U2_PHY are logical endpoints, not package pins.
* They alias existing USB2 expressions so pin groups can model direct and
* cross-coupled routing for host and mode paths.
*
* - USB2AAP/USB2ADAP/USB2AHAP: use PORTA_U2_PHY
* - USB2ABP : use PORTB_U2_PHY
* - USB2BBP/USB2BDBP/USB2BHBP: use PORTB_U2_PHY
* - USB2BAP : use PORTA_U2_PHY
*
* They do not have any registers to configure this behaviour; the goal is
* simply for the driver to prevent conflicting selections. For example,
* selecting group USB2ABP and USB2BBP at the same time should not be
* allowed.
*/
SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AXH, USB2AAP);
SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AXHP, USB2AAP);
SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2BXH2A, USB2BAP);
SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2BXHP2A, USB2BAP);
SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AD1, USB2ADAP);
SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AH, USB2AHAP);
SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AHP, USB2AHAP);
SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AD0, USB2AHAP);
PIN_DECL_(PORTA_U2_PHY, SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AXH),
SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AXHP), SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2BXH2A),
SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2BXHP2A), SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AD1),
SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AH), SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AHP),
SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AD0));
SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2AXH2B, USB2ABP);
SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2AXHP2B, USB2ABP);
SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BXH, USB2BBP);
SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BXHP, USB2BBP);
SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BD1, USB2BDBP);
SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BH, USB2BHBP);
SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BHP, USB2BHBP);
SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BD0, USB2BHBP);
PIN_DECL_(PORTB_U2_PHY, SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2AXH2B),
SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2AXHP2B), SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BXH),
SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BXHP), SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BD1),
SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BH), SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BHP),
SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BD0));
GROUP_DECL(USB2A, PORTA_U2);
GROUP_DECL(USB2AAP, PORTA_U2, PORTA_U2_PHY);
GROUP_DECL(USB2ABP, PORTA_U2, PORTB_U2_PHY);
GROUP_DECL(USB2ADAP, PORTA_U2, PORTA_U2_PHY);
GROUP_DECL(USB2AH, PORTA_MODE);
GROUP_DECL(USB2AHAP, PORTA_MODE, PORTA_U2_PHY);
FUNC_DECL_1(USB2AXHD1, USB2A);
FUNC_DECL_1(USB2AXHPD1, USB2A);
FUNC_DECL_1(USB2AXH, USB2AAP);
FUNC_DECL_1(USB2AXHP, USB2AAP);
FUNC_DECL_1(USB2AXH2B, USB2ABP);
FUNC_DECL_1(USB2AXHP2B, USB2ABP);
FUNC_DECL_1(USB2AD1, USB2ADAP);
FUNC_DECL_1(USB2AHPD0, USB2AH);
FUNC_DECL_1(USB2AH, USB2AHAP);
FUNC_DECL_1(USB2AHP, USB2AHAP);
FUNC_DECL_1(USB2AD0, USB2AHAP);
GROUP_DECL(USB2B, PORTB_U2);
GROUP_DECL(USB2BBP, PORTB_U2, PORTB_U2_PHY);
GROUP_DECL(USB2BAP, PORTB_U2, PORTA_U2_PHY);
GROUP_DECL(USB2BDBP, PORTB_U2, PORTB_U2_PHY);
GROUP_DECL(USB2BH, PORTB_MODE);
GROUP_DECL(USB2BHBP, PORTB_MODE, PORTB_U2_PHY);
FUNC_DECL_1(USB2BXHD1, USB2B);
FUNC_DECL_1(USB2BXHPD1, USB2B);
FUNC_DECL_1(USB2BXH, USB2BBP);
FUNC_DECL_1(USB2BXHP, USB2BBP);
FUNC_DECL_1(USB2BXH2A, USB2BAP);
FUNC_DECL_1(USB2BXHP2A, USB2BAP);
FUNC_DECL_1(USB2BD1, USB2BDBP);
FUNC_DECL_1(USB2BHPD0, USB2BH);
FUNC_DECL_1(USB2BH, USB2BHBP);
FUNC_DECL_1(USB2BHP, USB2BHBP);
FUNC_DECL_1(USB2BD0, USB2BHBP);
#define PORTA_U3_XHD_DESC { ASPEED_IP_SCU, SCU410, GENMASK(1, 0), 0, 0 }
#define PORTA_U3_XH_DESC { ASPEED_IP_SCU, SCU410, GENMASK(1, 0), 2, 0 }
#define PORTA_U3_XH2E_DESC { ASPEED_IP_SCU, SCU410, GENMASK(1, 0), 3, 0 }
SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXHD, USB3A, USB3AXHD, PORTA_U3_XHD_DESC,
SIG_DESC_SET(SCU410, 9));
SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXHPD, USB3A, USB3AXHPD, PORTA_U3_XHD_DESC,
SIG_DESC_CLEAR(SCU410, 9));
SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXH, USB3AAP, USB3AXH, PORTA_U3_XH_DESC,
SIG_DESC_SET(SCU410, 9));
SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXHP, USB3AAP, USB3AXHP, PORTA_U3_XH_DESC,
SIG_DESC_CLEAR(SCU410, 9));
SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXH2B, USB3ABP, USB3AXH2B, PORTA_U3_XH2E_DESC,
SIG_DESC_SET(SCU410, 9));
SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXHP2B, USB3ABP, USB3AXHP2B, PORTA_U3_XH2E_DESC,
SIG_DESC_CLEAR(SCU410, 9));
PIN_DECL_(PORTA_U3, SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXHD), SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXHPD),
SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXH), SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXHP),
SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXH2B), SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXHP2B));
#define PORTB_U3_XHD_DESC { ASPEED_IP_SCU, SCU410, GENMASK(5, 4), 0, 0 }
#define PORTB_U3_XH_DESC { ASPEED_IP_SCU, SCU410, GENMASK(5, 4), 2, 0 }
#define PORTB_U3_XH2E_DESC { ASPEED_IP_SCU, SCU410, GENMASK(5, 4), 3, 0 }
SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXHD, USB3B, USB3BXHD, PORTB_U3_XHD_DESC,
SIG_DESC_SET(SCU410, 10));
SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXHPD, USB3B, USB3BXHPD, PORTB_U3_XHD_DESC,
SIG_DESC_CLEAR(SCU410, 10));
SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXH, USB3BBP, USB3BXH, PORTB_U3_XH_DESC,
SIG_DESC_SET(SCU410, 10));
SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXHP, USB3BBP, USB3BXHP, PORTB_U3_XH_DESC,
SIG_DESC_CLEAR(SCU410, 10));
SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXH2A, USB3BAP, USB3BXH2A, PORTB_U3_XH2E_DESC,
SIG_DESC_SET(SCU410, 10));
SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXHP2A, USB3BAP, USB3BXHP2A, PORTB_U3_XH2E_DESC,
SIG_DESC_CLEAR(SCU410, 10));
PIN_DECL_(PORTB_U3, SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXHD), SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXHPD),
SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXH), SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXHP),
SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXH2A), SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXHP2A));
/*
* USB3 virtual PHY pins.
*
* PORTA_U3_PHY and PORTB_U3_PHY are logical endpoints, not package pins.
* They alias existing USB3 expressions so pin groups can model both direct and
* cross-coupled routing to PHY A/B.
*
* - USB3AAP: PORTA_U3 + PORTA_U3_PHY (A -> PHY A)
* - USB3ABP: PORTA_U3 + PORTB_U3_PHY (A -> PHY B)
* - USB3BBP: PORTB_U3 + PORTB_U3_PHY (B -> PHY B)
* - USB3BAP: PORTB_U3 + PORTA_U3_PHY (B -> PHY A)
*
* They do not have any registers to configure this behavior; the goal is
* simply for the driver to prevent conflicting selections. For example,
* selecting group USB3ABP and USB3BBP at the same time should not be
* allowed.
*/
SIG_EXPR_LIST_ALIAS(PORTA_U3_PHY, USB3AXH, USB3AAP);
SIG_EXPR_LIST_ALIAS(PORTA_U3_PHY, USB3AXHP, USB3AAP);
SIG_EXPR_LIST_ALIAS(PORTA_U3_PHY, USB3BXH2A, USB3BAP);
SIG_EXPR_LIST_ALIAS(PORTA_U3_PHY, USB3BXHP2A, USB3BAP);
PIN_DECL_(PORTA_U3_PHY, SIG_EXPR_LIST_PTR(PORTA_U3_PHY, USB3AXH),
SIG_EXPR_LIST_PTR(PORTA_U3_PHY, USB3AXHP), SIG_EXPR_LIST_PTR(PORTA_U3_PHY, USB3BXH2A),
SIG_EXPR_LIST_PTR(PORTA_U3_PHY, USB3BXHP2A));
SIG_EXPR_LIST_ALIAS(PORTB_U3_PHY, USB3AXH2B, USB3ABP);
SIG_EXPR_LIST_ALIAS(PORTB_U3_PHY, USB3AXHP2B, USB3ABP);
SIG_EXPR_LIST_ALIAS(PORTB_U3_PHY, USB3BXH, USB3BBP);
SIG_EXPR_LIST_ALIAS(PORTB_U3_PHY, USB3BXHP, USB3BBP);
PIN_DECL_(PORTB_U3_PHY, SIG_EXPR_LIST_PTR(PORTB_U3_PHY, USB3AXH2B),
SIG_EXPR_LIST_PTR(PORTB_U3_PHY, USB3AXHP2B), SIG_EXPR_LIST_PTR(PORTB_U3_PHY, USB3BXH),
SIG_EXPR_LIST_PTR(PORTB_U3_PHY, USB3BXHP));
/* USB3A xHCI to vHUB */
GROUP_DECL(USB3A, PORTA_U3);
/* USB3A xHCI to USB3A PHY */
GROUP_DECL(USB3AAP, PORTA_U3, PORTA_U3_PHY);
/* USB3A xHCI to USB3B PHY */
GROUP_DECL(USB3ABP, PORTA_U3, PORTB_U3_PHY);
FUNC_DECL_1(USB3AXHD, USB3A);
FUNC_DECL_1(USB3AXHPD, USB3A);
FUNC_DECL_1(USB3AXH, USB3AAP);
FUNC_DECL_1(USB3AXHP, USB3AAP);
FUNC_DECL_1(USB3AXH2B, USB3ABP);
FUNC_DECL_1(USB3AXHP2B, USB3ABP);
/* USB3B xHCI to vHUB */
GROUP_DECL(USB3B, PORTB_U3);
/* USB3B xHCI to USB3A PHY */
GROUP_DECL(USB3BAP, PORTB_U3, PORTA_U3_PHY);
/* USB3B xHCI to USB3B PHY */
GROUP_DECL(USB3BBP, PORTB_U3, PORTB_U3_PHY);
FUNC_DECL_1(USB3BXHD, USB3B);
FUNC_DECL_1(USB3BXHPD, USB3B);
FUNC_DECL_1(USB3BXH, USB3BBP);
FUNC_DECL_1(USB3BXHP, USB3BBP);
FUNC_DECL_1(USB3BXH2A, USB3BAP);
FUNC_DECL_1(USB3BXHP2A, USB3BAP);
static const struct pinctrl_pin_desc aspeed_g7_soc0_pins[] = {
ASPEED_PINCTRL_PIN(AC14),
ASPEED_PINCTRL_PIN(AE15),
ASPEED_PINCTRL_PIN(AD14),
ASPEED_PINCTRL_PIN(AE14),
ASPEED_PINCTRL_PIN(AF14),
ASPEED_PINCTRL_PIN(AB13),
ASPEED_PINCTRL_PIN(AB14),
ASPEED_PINCTRL_PIN(AF15),
ASPEED_PINCTRL_PIN(AF13),
ASPEED_PINCTRL_PIN(AC13),
ASPEED_PINCTRL_PIN(AD13),
ASPEED_PINCTRL_PIN(AE13),
ASPEED_PINCTRL_PIN(JTAG_PORT),
ASPEED_PINCTRL_PIN(PCIERC0_PERST),
ASPEED_PINCTRL_PIN(PCIERC1_PERST),
ASPEED_PINCTRL_PIN(PORTA_MODE),
ASPEED_PINCTRL_PIN(PORTA_U2),
ASPEED_PINCTRL_PIN(PORTA_U3),
ASPEED_PINCTRL_PIN(PORTA_U2_PHY),
ASPEED_PINCTRL_PIN(PORTA_U3_PHY),
ASPEED_PINCTRL_PIN(PORTB_MODE),
ASPEED_PINCTRL_PIN(PORTB_U2),
ASPEED_PINCTRL_PIN(PORTB_U3),
ASPEED_PINCTRL_PIN(PORTB_U2_PHY),
ASPEED_PINCTRL_PIN(PORTB_U3_PHY),
};
static const struct aspeed_pin_group aspeed_g7_soc0_groups[] = {
ASPEED_PINCTRL_GROUP(EMMCCDN),
ASPEED_PINCTRL_GROUP(EMMCG1),
ASPEED_PINCTRL_GROUP(EMMCG4),
ASPEED_PINCTRL_GROUP(EMMCG8),
ASPEED_PINCTRL_GROUP(EMMCWPN),
ASPEED_PINCTRL_GROUP(TSPRSTN),
ASPEED_PINCTRL_GROUP(UFSCLKI),
ASPEED_PINCTRL_GROUP(VB0),
ASPEED_PINCTRL_GROUP(VB1),
ASPEED_PINCTRL_GROUP(VGADDC),
/* JTAG groups */
ASPEED_PINCTRL_GROUP(JTAG0),
/* PCIE RC groups */
ASPEED_PINCTRL_GROUP(PCIERC0PERST),
ASPEED_PINCTRL_GROUP(PCIERC1PERST),
/* USB3A groups */
ASPEED_PINCTRL_GROUP(USB3A),
ASPEED_PINCTRL_GROUP(USB3AAP),
ASPEED_PINCTRL_GROUP(USB3ABP),
/* USB3B groups */
ASPEED_PINCTRL_GROUP(USB3B),
ASPEED_PINCTRL_GROUP(USB3BAP),
ASPEED_PINCTRL_GROUP(USB3BBP),
/* USB2A groups */
ASPEED_PINCTRL_GROUP(USB2A),
ASPEED_PINCTRL_GROUP(USB2AAP),
ASPEED_PINCTRL_GROUP(USB2ABP),
ASPEED_PINCTRL_GROUP(USB2ADAP),
ASPEED_PINCTRL_GROUP(USB2AH),
ASPEED_PINCTRL_GROUP(USB2AHAP),
/* USB2B groups */
ASPEED_PINCTRL_GROUP(USB2B),
ASPEED_PINCTRL_GROUP(USB2BAP),
ASPEED_PINCTRL_GROUP(USB2BBP),
ASPEED_PINCTRL_GROUP(USB2BDBP),
ASPEED_PINCTRL_GROUP(USB2BH),
ASPEED_PINCTRL_GROUP(USB2BHBP),
};
static const struct aspeed_pin_function aspeed_g7_soc0_functions[] = {
ASPEED_PINCTRL_FUNC(EMMC),
ASPEED_PINCTRL_FUNC(TSPRSTN),
ASPEED_PINCTRL_FUNC(UFSCLKI),
ASPEED_PINCTRL_FUNC(VB),
ASPEED_PINCTRL_FUNC(VGADDC),
/* JTAG functions */
ASPEED_PINCTRL_FUNC(JTAGDDR),
ASPEED_PINCTRL_FUNC(JTAGM0),
ASPEED_PINCTRL_FUNC(JTAGPCIEA),
ASPEED_PINCTRL_FUNC(JTAGPCIEB),
ASPEED_PINCTRL_FUNC(JTAGPSP),
ASPEED_PINCTRL_FUNC(JTAGSSP),
ASPEED_PINCTRL_FUNC(JTAGTSP),
ASPEED_PINCTRL_FUNC(JTAGUSB3A),
ASPEED_PINCTRL_FUNC(JTAGUSB3B),
/* PCIE RC functions */
ASPEED_PINCTRL_FUNC(PCIERC0PERST),
ASPEED_PINCTRL_FUNC(PCIERC1PERST),
/* USB3A functions */
ASPEED_PINCTRL_FUNC(USB3AXH),
ASPEED_PINCTRL_FUNC(USB3AXH2B),
ASPEED_PINCTRL_FUNC(USB3AXHD),
ASPEED_PINCTRL_FUNC(USB3AXHP),
ASPEED_PINCTRL_FUNC(USB3AXHP2B),
ASPEED_PINCTRL_FUNC(USB3AXHPD),
/* USB3B functions */
ASPEED_PINCTRL_FUNC(USB3BXH),
ASPEED_PINCTRL_FUNC(USB3BXH2A),
ASPEED_PINCTRL_FUNC(USB3BXHD),
ASPEED_PINCTRL_FUNC(USB3BXHP),
ASPEED_PINCTRL_FUNC(USB3BXHP2A),
ASPEED_PINCTRL_FUNC(USB3BXHPD),
/* USB2A functions */
ASPEED_PINCTRL_FUNC(USB2AD0),
ASPEED_PINCTRL_FUNC(USB2AD1),
ASPEED_PINCTRL_FUNC(USB2AH),
ASPEED_PINCTRL_FUNC(USB2AHP),
ASPEED_PINCTRL_FUNC(USB2AHPD0),
ASPEED_PINCTRL_FUNC(USB2AXH),
ASPEED_PINCTRL_FUNC(USB2AXH2B),
ASPEED_PINCTRL_FUNC(USB2AXHD1),
ASPEED_PINCTRL_FUNC(USB2AXHP),
ASPEED_PINCTRL_FUNC(USB2AXHP2B),
ASPEED_PINCTRL_FUNC(USB2AXHPD1),
/* USB2B functions */
ASPEED_PINCTRL_FUNC(USB2BD0),
ASPEED_PINCTRL_FUNC(USB2BD1),
ASPEED_PINCTRL_FUNC(USB2BH),
ASPEED_PINCTRL_FUNC(USB2BHP),
ASPEED_PINCTRL_FUNC(USB2BHPD0),
ASPEED_PINCTRL_FUNC(USB2BXH),
ASPEED_PINCTRL_FUNC(USB2BXH2A),
ASPEED_PINCTRL_FUNC(USB2BXHD1),
ASPEED_PINCTRL_FUNC(USB2BXHP),
ASPEED_PINCTRL_FUNC(USB2BXHP2A),
ASPEED_PINCTRL_FUNC(USB2BXHPD1),
};
static const struct pinmux_ops aspeed_g7_soc0_pinmux_ops = {
.get_functions_count = aspeed_pinmux_get_fn_count,
.get_function_name = aspeed_pinmux_get_fn_name,
.get_function_groups = aspeed_pinmux_get_fn_groups,
.set_mux = aspeed_pinmux_set_mux,
.gpio_request_enable = aspeed_gpio_request_enable,
.strict = true,
};
static const struct pinctrl_ops aspeed_g7_soc0_pinctrl_ops = {
.get_groups_count = aspeed_pinctrl_get_groups_count,
.get_group_name = aspeed_pinctrl_get_group_name,
.get_group_pins = aspeed_pinctrl_get_group_pins,
.pin_dbg_show = aspeed_pinctrl_pin_dbg_show,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinctrl_utils_free_map,
};
static const struct pinconf_ops aspeed_g7_soc0_pinconf_ops = {
.is_generic = true,
.pin_config_get = aspeed_pin_config_get,
.pin_config_set = aspeed_pin_config_set,
.pin_config_group_get = aspeed_pin_config_group_get,
.pin_config_group_set = aspeed_pin_config_group_set,
};
/* pinctrl_desc */
static const struct pinctrl_desc aspeed_g7_soc0_pinctrl_desc = {
.name = "aspeed-g7-soc0-pinctrl",
.pins = aspeed_g7_soc0_pins,
.npins = ARRAY_SIZE(aspeed_g7_soc0_pins),
.pctlops = &aspeed_g7_soc0_pinctrl_ops,
.pmxops = &aspeed_g7_soc0_pinmux_ops,
.confops = &aspeed_g7_soc0_pinconf_ops,
};
static const struct aspeed_pin_config aspeed_g7_soc0_configs[] = {
/* GPIO18A */
{ PIN_CONFIG_DRIVE_STRENGTH, { AC14, AC14 }, SCU480, GENMASK(3, 0) },
{ PIN_CONFIG_BIAS_PULL_DOWN, { AC14, AC14 }, SCU480, GENMASK(5, 4) },
{ PIN_CONFIG_BIAS_PULL_UP, { AC14, AC14 }, SCU480, GENMASK(5, 4) },
{ PIN_CONFIG_BIAS_DISABLE, { AC14, AC14 }, SCU480, BIT(5) },
{ PIN_CONFIG_DRIVE_STRENGTH, { AE15, AE15 }, SCU484, GENMASK(3, 0) },
{ PIN_CONFIG_BIAS_PULL_DOWN, { AE15, AE15 }, SCU484, GENMASK(5, 4) },
{ PIN_CONFIG_BIAS_PULL_UP, { AE15, AE15 }, SCU484, GENMASK(5, 4) },
{ PIN_CONFIG_BIAS_DISABLE, { AE15, AE15 }, SCU484, BIT(5) },
{ PIN_CONFIG_DRIVE_STRENGTH, { AD14, AD14 }, SCU488, GENMASK(3, 0) },
{ PIN_CONFIG_BIAS_PULL_DOWN, { AD14, AD14 }, SCU488, GENMASK(5, 4) },
{ PIN_CONFIG_BIAS_PULL_UP, { AD14, AD14 }, SCU488, GENMASK(5, 4) },
{ PIN_CONFIG_BIAS_DISABLE, { AD14, AD14 }, SCU488, BIT(5) },
{ PIN_CONFIG_DRIVE_STRENGTH, { AE14, AE14 }, SCU48C, GENMASK(3, 0) },
{ PIN_CONFIG_BIAS_PULL_DOWN, { AE14, AE14 }, SCU48C, GENMASK(5, 4) },
{ PIN_CONFIG_BIAS_PULL_UP, { AE14, AE14 }, SCU48C, GENMASK(5, 4) },
{ PIN_CONFIG_BIAS_DISABLE, { AE14, AE14 }, SCU48C, BIT(5) },
{ PIN_CONFIG_DRIVE_STRENGTH, { AF14, AF14 }, SCU490, GENMASK(3, 0) },
{ PIN_CONFIG_BIAS_PULL_DOWN, { AF14, AF14 }, SCU490, GENMASK(5, 4) },
{ PIN_CONFIG_BIAS_PULL_UP, { AF14, AF14 }, SCU490, GENMASK(5, 4) },
{ PIN_CONFIG_BIAS_DISABLE, { AF14, AF14 }, SCU490, BIT(5) },
{ PIN_CONFIG_DRIVE_STRENGTH, { AB13, AB13 }, SCU494, GENMASK(3, 0) },
{ PIN_CONFIG_BIAS_PULL_DOWN, { AB13, AB13 }, SCU494, GENMASK(5, 4) },
{ PIN_CONFIG_BIAS_PULL_UP, { AB13, AB13 }, SCU494, GENMASK(5, 4) },
{ PIN_CONFIG_BIAS_DISABLE, { AB13, AB13 }, SCU494, BIT(5) },
{ PIN_CONFIG_DRIVE_STRENGTH, { AB14, AB14 }, SCU498, GENMASK(3, 0) },
{ PIN_CONFIG_BIAS_PULL_DOWN, { AB14, AB14 }, SCU498, GENMASK(5, 4) },
{ PIN_CONFIG_BIAS_PULL_UP, { AB14, AB14 }, SCU498, GENMASK(5, 4) },
{ PIN_CONFIG_BIAS_DISABLE, { AB14, AB14 }, SCU498, BIT(5) },
{ PIN_CONFIG_DRIVE_STRENGTH, { AF15, AF15 }, SCU49C, GENMASK(3, 0) },
{ PIN_CONFIG_BIAS_PULL_DOWN, { AF15, AF15 }, SCU49C, GENMASK(5, 4) },
{ PIN_CONFIG_BIAS_PULL_UP, { AF15, AF15 }, SCU49C, GENMASK(5, 4) },
{ PIN_CONFIG_BIAS_DISABLE, { AF15, AF15 }, SCU49C, BIT(5) },
/* GPIO18B */
{ PIN_CONFIG_DRIVE_STRENGTH, { AF13, AF13 }, SCU4A0, GENMASK(3, 0) },
{ PIN_CONFIG_BIAS_PULL_DOWN, { AF13, AF13 }, SCU4A0, GENMASK(5, 4) },
{ PIN_CONFIG_BIAS_PULL_UP, { AF13, AF13 }, SCU4A0, GENMASK(5, 4) },
{ PIN_CONFIG_BIAS_DISABLE, { AF13, AF13 }, SCU4A0, BIT(5) },
{ PIN_CONFIG_DRIVE_STRENGTH, { AC13, AC13 }, SCU4A4, GENMASK(3, 0) },
{ PIN_CONFIG_BIAS_PULL_DOWN, { AC13, AC13 }, SCU4A4, GENMASK(5, 4) },
{ PIN_CONFIG_BIAS_PULL_UP, { AC13, AC13 }, SCU4A4, GENMASK(5, 4) },
{ PIN_CONFIG_BIAS_DISABLE, { AC13, AC13 }, SCU4A4, BIT(5) },
{ PIN_CONFIG_DRIVE_STRENGTH, { AD13, AD13 }, SCU4A8, GENMASK(3, 0) },
{ PIN_CONFIG_BIAS_PULL_DOWN, { AD13, AD13 }, SCU4A8, GENMASK(5, 4) },
{ PIN_CONFIG_BIAS_PULL_UP, { AD13, AD13 }, SCU4A8, GENMASK(5, 4) },
{ PIN_CONFIG_BIAS_DISABLE, { AD13, AD13 }, SCU4A8, BIT(5) },
{ PIN_CONFIG_DRIVE_STRENGTH, { AE13, AE13 }, SCU4AC, GENMASK(3, 0) },
{ PIN_CONFIG_BIAS_PULL_DOWN, { AE13, AE13 }, SCU4AC, GENMASK(5, 4) },
{ PIN_CONFIG_BIAS_PULL_UP, { AE13, AE13 }, SCU4AC, GENMASK(5, 4) },
{ PIN_CONFIG_BIAS_DISABLE, { AE13, AE13 }, SCU4AC, BIT(5) },
};
static const struct aspeed_pin_config_map aspeed_g7_soc0_pin_config_map[] = {
{ PIN_CONFIG_BIAS_PULL_DOWN, -1, 2, GENMASK(1, 0) },
{ PIN_CONFIG_BIAS_PULL_UP, -1, 3, GENMASK(1, 0) },
{ PIN_CONFIG_BIAS_DISABLE, -1, 0, BIT_MASK(0) },
{ PIN_CONFIG_DRIVE_STRENGTH, 3, 0, GENMASK(3, 0) },
{ PIN_CONFIG_DRIVE_STRENGTH, 6, 1, GENMASK(3, 0) },
{ PIN_CONFIG_DRIVE_STRENGTH, 8, 2, GENMASK(3, 0) },
{ PIN_CONFIG_DRIVE_STRENGTH, 11, 3, GENMASK(3, 0) },
{ PIN_CONFIG_DRIVE_STRENGTH, 16, 4, GENMASK(3, 0) },
{ PIN_CONFIG_DRIVE_STRENGTH, 18, 5, GENMASK(3, 0) },
{ PIN_CONFIG_DRIVE_STRENGTH, 20, 6, GENMASK(3, 0) },
{ PIN_CONFIG_DRIVE_STRENGTH, 23, 7, GENMASK(3, 0) },
{ PIN_CONFIG_DRIVE_STRENGTH, 30, 8, GENMASK(3, 0) },
{ PIN_CONFIG_DRIVE_STRENGTH, 32, 9, GENMASK(3, 0) },
{ PIN_CONFIG_DRIVE_STRENGTH, 33, 10, GENMASK(3, 0) },
{ PIN_CONFIG_DRIVE_STRENGTH, 35, 11, GENMASK(3, 0) },
{ PIN_CONFIG_DRIVE_STRENGTH, 37, 12, GENMASK(3, 0) },
{ PIN_CONFIG_DRIVE_STRENGTH, 38, 13, GENMASK(3, 0) },
{ PIN_CONFIG_DRIVE_STRENGTH, 39, 14, GENMASK(3, 0) },
{ PIN_CONFIG_DRIVE_STRENGTH, 41, 15, GENMASK(3, 0) },
};
static int aspeed_g7_soc0_sig_expr_set(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr, bool enable)
{
int ret;
int i;
for (i = 0; i < expr->ndescs; i++) {
const struct aspeed_sig_desc *desc = &expr->descs[i];
u32 pattern = enable ? desc->enable : desc->disable;
u32 val = (pattern << __ffs(desc->mask));
if (!ctx->maps[desc->ip])
return -ENODEV;
WARN_ON_ONCE(desc->ip != ASPEED_IP_SCU);
ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg,
desc->mask, val);
if (ret)
return ret;
}
ret = aspeed_sig_expr_eval(ctx, expr, enable);
if (ret < 0)
return ret;
return ret ? 0 : -EPERM;
}
static const struct aspeed_pinmux_ops aspeed_g7_soc0_ops = {
.set = aspeed_g7_soc0_sig_expr_set,
};
static struct aspeed_pinctrl_data aspeed_g7_soc0_pinctrl_data = {
.pins = aspeed_g7_soc0_pins,
.npins = ARRAY_SIZE(aspeed_g7_soc0_pins),
.pinmux = {
.ops = &aspeed_g7_soc0_ops,
.groups = aspeed_g7_soc0_groups,
.ngroups = ARRAY_SIZE(aspeed_g7_soc0_groups),
.functions = aspeed_g7_soc0_functions,
.nfunctions = ARRAY_SIZE(aspeed_g7_soc0_functions),
},
.configs = aspeed_g7_soc0_configs,
.nconfigs = ARRAY_SIZE(aspeed_g7_soc0_configs),
.confmaps = aspeed_g7_soc0_pin_config_map,
.nconfmaps = ARRAY_SIZE(aspeed_g7_soc0_pin_config_map),
};
static int aspeed_g7_soc0_pinctrl_probe(struct platform_device *pdev)
{
return aspeed_pinctrl_probe(pdev, &aspeed_g7_soc0_pinctrl_desc,
&aspeed_g7_soc0_pinctrl_data);
}
static const struct of_device_id aspeed_g7_soc0_pinctrl_match[] = {
{ .compatible = "aspeed,ast2700-soc0-pinctrl" },
{}
};
MODULE_DEVICE_TABLE(of, aspeed_g7_soc0_pinctrl_match);
static struct platform_driver aspeed_g7_soc0_pinctrl_driver = {
.probe = aspeed_g7_soc0_pinctrl_probe,
.driver = {
.name = "aspeed-g7-soc0-pinctrl",
.of_match_table = aspeed_g7_soc0_pinctrl_match,
.suppress_bind_attrs = true,
},
};
static int __init aspeed_g7_soc0_pinctrl_init(void)
{
return platform_driver_register(&aspeed_g7_soc0_pinctrl_driver);
}
arch_initcall(aspeed_g7_soc0_pinctrl_init);
linux-7.2.3/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c
+1756
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File diff suppressed because it is too large Load Diff
linux-7.2.3/drivers/pinctrl/aspeed/pinctrl-aspeed.c
+659
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@@ -0,0 +1,659 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 IBM Corp.
*/
#include <linux/mfd/syscon.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/string.h>
#include "../core.h"
#include "pinctrl-aspeed.h"
int aspeed_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
return pdata->pinmux.ngroups;
}
const char *aspeed_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned int group)
{
struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
return pdata->pinmux.groups[group].name;
}
int aspeed_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int group, const unsigned int **pins,
unsigned int *npins)
{
struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
*pins = &pdata->pinmux.groups[group].pins[0];
*npins = pdata->pinmux.groups[group].npins;
return 0;
}
void aspeed_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned int offset)
{
seq_printf(s, " %s", dev_name(pctldev->dev));
}
int aspeed_pinmux_get_fn_count(struct pinctrl_dev *pctldev)
{
struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
return pdata->pinmux.nfunctions;
}
const char *aspeed_pinmux_get_fn_name(struct pinctrl_dev *pctldev,
unsigned int function)
{
struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
return pdata->pinmux.functions[function].name;
}
int aspeed_pinmux_get_fn_groups(struct pinctrl_dev *pctldev,
unsigned int function,
const char * const **groups,
unsigned int * const num_groups)
{
struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
*groups = pdata->pinmux.functions[function].groups;
*num_groups = pdata->pinmux.functions[function].ngroups;
return 0;
}
static int aspeed_sig_expr_enable(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr)
{
int ret;
pr_debug("Enabling signal %s for %s\n", expr->signal,
expr->function);
ret = aspeed_sig_expr_eval(ctx, expr, true);
if (ret < 0)
return ret;
if (!ret)
return aspeed_sig_expr_set(ctx, expr, true);
return 0;
}
static int aspeed_sig_expr_disable(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr)
{
int ret;
pr_debug("Disabling signal %s for %s\n", expr->signal,
expr->function);
ret = aspeed_sig_expr_eval(ctx, expr, true);
if (ret < 0)
return ret;
if (ret)
return aspeed_sig_expr_set(ctx, expr, false);
return 0;
}
/**
* aspeed_disable_sig() - Disable a signal on a pin by disabling all provided
* signal expressions.
*
* @ctx: The pinmux context
* @exprs: The list of signal expressions (from a priority level on a pin)
*
* Return: 0 if all expressions are disabled, otherwise a negative error code
*/
static int aspeed_disable_sig(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr **exprs)
{
int ret = 0;
if (!exprs)
return -EINVAL;
while (*exprs && !ret) {
ret = aspeed_sig_expr_disable(ctx, *exprs);
exprs++;
}
return ret;
}
/**
* aspeed_find_expr_by_name - Search for the signal expression needed to
* enable the pin's signal for the requested function.
*
* @exprs: List of signal expressions (haystack)
* @name: The name of the requested function (needle)
*
* Return: A pointer to the signal expression whose function tag matches the
* provided name, otherwise NULL.
*
*/
static const struct aspeed_sig_expr *aspeed_find_expr_by_name(
const struct aspeed_sig_expr **exprs, const char *name)
{
while (*exprs) {
if (strcmp((*exprs)->function, name) == 0)
return *exprs;
exprs++;
}
return NULL;
}
static char *get_defined_attribute(const struct aspeed_pin_desc *pdesc,
const char *(*get)(
const struct aspeed_sig_expr *))
{
char *found = NULL;
size_t len = 0;
const struct aspeed_sig_expr ***prios, **funcs, *expr;
prios = pdesc->prios;
while ((funcs = *prios)) {
while ((expr = *funcs)) {
const char *str = get(expr);
size_t delta = strlen(str) + 2;
char *expanded;
expanded = krealloc(found, len + delta + 1, GFP_KERNEL);
if (!expanded) {
kfree(found);
return expanded;
}
found = expanded;
found[len] = '\0';
len += delta;
strcat(found, str);
strcat(found, ", ");
funcs++;
}
prios++;
}
if (len < 2) {
kfree(found);
return NULL;
}
found[len - 2] = '\0';
return found;
}
static const char *aspeed_sig_expr_function(const struct aspeed_sig_expr *expr)
{
return expr->function;
}
static char *get_defined_functions(const struct aspeed_pin_desc *pdesc)
{
return get_defined_attribute(pdesc, aspeed_sig_expr_function);
}
static const char *aspeed_sig_expr_signal(const struct aspeed_sig_expr *expr)
{
return expr->signal;
}
static char *get_defined_signals(const struct aspeed_pin_desc *pdesc)
{
return get_defined_attribute(pdesc, aspeed_sig_expr_signal);
}
int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
unsigned int group)
{
int i;
int ret;
struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
const struct aspeed_pin_group *pgroup = &pdata->pinmux.groups[group];
const struct aspeed_pin_function *pfunc =
&pdata->pinmux.functions[function];
for (i = 0; i < pgroup->npins; i++) {
int pin = pgroup->pins[i];
const struct aspeed_pin_desc *pdesc = pdata->pins[pin].drv_data;
const struct aspeed_sig_expr *expr = NULL;
const struct aspeed_sig_expr **funcs;
const struct aspeed_sig_expr ***prios;
if (!pdesc)
return -EINVAL;
pr_debug("Muxing pin %s for %s\n", pdesc->name, pfunc->name);
prios = pdesc->prios;
if (!prios)
continue;
/* Disable functions at a higher priority than that requested */
while ((funcs = *prios)) {
expr = aspeed_find_expr_by_name(funcs, pfunc->name);
if (expr)
break;
ret = aspeed_disable_sig(&pdata->pinmux, funcs);
if (ret)
return ret;
prios++;
}
if (!expr) {
char *functions = get_defined_functions(pdesc);
char *signals = get_defined_signals(pdesc);
pr_warn("No function %s found on pin %s (%d). Found signal(s) %s for function(s) %s\n",
pfunc->name, pdesc->name, pin, signals,
functions);
kfree(signals);
kfree(functions);
return -ENXIO;
}
ret = aspeed_sig_expr_enable(&pdata->pinmux, expr);
if (ret)
return ret;
pr_debug("Muxed pin %s as %s for %s\n", pdesc->name, expr->signal,
expr->function);
}
return 0;
}
static bool aspeed_expr_is_gpio(const struct aspeed_sig_expr *expr)
{
/*
* We need to differentiate between GPIO and non-GPIO signals to
* implement the gpio_request_enable() interface. For better or worse
* the ASPEED pinctrl driver uses the expression names to determine
* whether an expression will mux a pin for GPIO.
*
* Generally we have the following - A GPIO such as B1 has:
*
* - expr->signal set to "GPIOB1"
* - expr->function set to "GPIOB1"
*
* Using this fact we can determine whether the provided expression is
* a GPIO expression by testing the signal name for the string prefix
* "GPIO".
*
* However, some GPIOs are input-only, and the ASPEED datasheets name
* them differently. An input-only GPIO such as T0 has:
*
* - expr->signal set to "GPIT0"
* - expr->function set to "GPIT0"
*
* It's tempting to generalise the prefix test from "GPIO" to "GPI" to
* account for both GPIOs and GPIs, but in doing so we run aground on
* another feature:
*
* Some pins in the ASPEED BMC SoCs have a "pass-through" GPIO
* function where the input state of one pin is replicated as the
* output state of another (as if they were shorted together - a mux
* configuration that is typically enabled by hardware strapping).
* This feature allows the BMC to pass e.g. power button state through
* to the host while the BMC is yet to boot, but take control of the
* button state once the BMC has booted by muxing each pin as a
* separate, pin-specific GPIO.
*
* Conceptually this pass-through mode is a form of GPIO and is named
* as such in the datasheets, e.g. "GPID0". This naming similarity
* trips us up with the simple GPI-prefixed-signal-name scheme
* discussed above, as the pass-through configuration is not what we
* want when muxing a pin as GPIO for the GPIO subsystem.
*
* On e.g. the AST2400, a pass-through function "GPID0" is grouped on
* balls A18 and D16, where we have:
*
* For ball A18:
* - expr->signal set to "GPID0IN"
* - expr->function set to "GPID0"
*
* For ball D16:
* - expr->signal set to "GPID0OUT"
* - expr->function set to "GPID0"
*
* By contrast, the pin-specific GPIO expressions for the same pins are
* as follows:
*
* For ball A18:
* - expr->signal looks like "GPIOD0"
* - expr->function looks like "GPIOD0"
*
* For ball D16:
* - expr->signal looks like "GPIOD1"
* - expr->function looks like "GPIOD1"
*
* Testing both the signal _and_ function names gives us the means
* differentiate the pass-through GPIO pinmux configuration from the
* pin-specific configuration that the GPIO subsystem is after: An
* expression is a pin-specific (non-pass-through) GPIO configuration
* if the signal prefix is "GPI" and the signal name matches the
* function name.
*/
return !strncmp(expr->signal, "GPI", 3) &&
!strcmp(expr->signal, expr->function);
}
static bool aspeed_gpio_in_exprs(const struct aspeed_sig_expr **exprs)
{
if (!exprs)
return false;
while (*exprs) {
if (aspeed_expr_is_gpio(*exprs))
return true;
exprs++;
}
return false;
}
int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset)
{
int ret;
struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
const struct aspeed_pin_desc *pdesc = pdata->pins[offset].drv_data;
const struct aspeed_sig_expr ***prios, **funcs, *expr;
if (!pdesc)
return -EINVAL;
prios = pdesc->prios;
if (!prios)
return -ENXIO;
pr_debug("Muxing pin %s for GPIO\n", pdesc->name);
/* Disable any functions of higher priority than GPIO */
while ((funcs = *prios)) {
if (aspeed_gpio_in_exprs(funcs))
break;
ret = aspeed_disable_sig(&pdata->pinmux, funcs);
if (ret)
return ret;
prios++;
}
if (!funcs) {
char *signals = get_defined_signals(pdesc);
pr_warn("No GPIO signal type found on pin %s (%d). Found: %s\n",
pdesc->name, offset, signals);
kfree(signals);
return -ENXIO;
}
expr = *funcs;
/*
* Disabling all higher-priority expressions is enough to enable the
* lowest-priority signal type. As such it has no associated
* expression.
*/
if (!expr) {
pr_debug("Muxed pin %s as GPIO\n", pdesc->name);
return 0;
}
/*
* If GPIO is not the lowest priority signal type, assume there is only
* one expression defined to enable the GPIO function
*/
ret = aspeed_sig_expr_enable(&pdata->pinmux, expr);
if (ret)
return ret;
pr_debug("Muxed pin %s as %s\n", pdesc->name, expr->signal);
return 0;
}
int aspeed_pinctrl_probe(struct platform_device *pdev,
const struct pinctrl_desc *pdesc,
struct aspeed_pinctrl_data *pdata)
{
struct device *parent;
struct pinctrl_dev *pctl;
parent = pdev->dev.parent;
if (!parent) {
dev_err(&pdev->dev, "No parent for syscon pincontroller\n");
return -ENODEV;
}
pdata->scu = syscon_node_to_regmap(parent->of_node);
if (IS_ERR(pdata->scu)) {
dev_err(&pdev->dev, "No regmap for syscon pincontroller parent\n");
return PTR_ERR(pdata->scu);
}
pdata->pinmux.maps[ASPEED_IP_SCU] = pdata->scu;
pctl = pinctrl_register(pdesc, &pdev->dev, pdata);
if (IS_ERR(pctl)) {
dev_err(&pdev->dev, "Failed to register pinctrl\n");
return PTR_ERR(pctl);
}
platform_set_drvdata(pdev, pdata);
return 0;
}
static inline bool pin_in_config_range(unsigned int offset,
const struct aspeed_pin_config *config)
{
return offset >= config->pins[0] && offset <= config->pins[1];
}
static inline const struct aspeed_pin_config *find_pinconf_config(
const struct aspeed_pinctrl_data *pdata,
unsigned int offset,
enum pin_config_param param)
{
unsigned int i;
for (i = 0; i < pdata->nconfigs; i++) {
if (param == pdata->configs[i].param &&
pin_in_config_range(offset, &pdata->configs[i]))
return &pdata->configs[i];
}
return NULL;
}
enum aspeed_pin_config_map_type { MAP_TYPE_ARG, MAP_TYPE_VAL };
static const struct aspeed_pin_config_map *find_pinconf_map(
const struct aspeed_pinctrl_data *pdata,
enum pin_config_param param,
enum aspeed_pin_config_map_type type,
s64 value)
{
int i;
for (i = 0; i < pdata->nconfmaps; i++) {
const struct aspeed_pin_config_map *elem;
bool match;
elem = &pdata->confmaps[i];
switch (type) {
case MAP_TYPE_ARG:
match = (elem->arg == -1 || elem->arg == value);
break;
case MAP_TYPE_VAL:
match = (elem->val == value);
break;
}
if (param == elem->param && match)
return elem;
}
return NULL;
}
int aspeed_pin_config_get(struct pinctrl_dev *pctldev, unsigned int offset,
unsigned long *config)
{
const enum pin_config_param param = pinconf_to_config_param(*config);
const struct aspeed_pin_config_map *pmap;
const struct aspeed_pinctrl_data *pdata;
const struct aspeed_pin_config *pconf;
unsigned int val;
int rc = 0;
u32 arg;
pdata = pinctrl_dev_get_drvdata(pctldev);
pconf = find_pinconf_config(pdata, offset, param);
if (!pconf)
return -ENOTSUPP;
rc = regmap_read(pdata->scu, pconf->reg, &val);
if (rc < 0)
return rc;
pmap = find_pinconf_map(pdata, param, MAP_TYPE_VAL,
(val & pconf->mask) >> __ffs(pconf->mask));
if (!pmap)
return -EINVAL;
if (param == PIN_CONFIG_DRIVE_STRENGTH)
arg = (u32) pmap->arg;
else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
arg = !!pmap->arg;
else
arg = 1;
if (!arg)
return -EINVAL;
*config = pinconf_to_config_packed(param, arg);
return 0;
}
int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset,
unsigned long *configs, unsigned int num_configs)
{
const struct aspeed_pinctrl_data *pdata;
unsigned int i;
int rc = 0;
pdata = pinctrl_dev_get_drvdata(pctldev);
for (i = 0; i < num_configs; i++) {
const struct aspeed_pin_config_map *pmap;
const struct aspeed_pin_config *pconf;
enum pin_config_param param;
unsigned int val;
u32 arg;
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
pconf = find_pinconf_config(pdata, offset, param);
if (!pconf)
return -ENOTSUPP;
pmap = find_pinconf_map(pdata, param, MAP_TYPE_ARG, arg);
if (WARN_ON(!pmap))
return -EINVAL;
val = pmap->val << __ffs(pconf->mask);
rc = regmap_update_bits(pdata->scu, pconf->reg,
pconf->mask, val);
if (rc < 0)
return rc;
pr_debug("%s: Set SCU%02X[0x%08X]=0x%X for param %d(=%d) on pin %d\n",
__func__, pconf->reg, pconf->mask,
val, param, arg, offset);
}
return 0;
}
int aspeed_pin_config_group_get(struct pinctrl_dev *pctldev,
unsigned int selector,
unsigned long *config)
{
const unsigned int *pins;
unsigned int npins;
int rc;
rc = aspeed_pinctrl_get_group_pins(pctldev, selector, &pins, &npins);
if (rc < 0)
return rc;
if (!npins)
return -ENODEV;
rc = aspeed_pin_config_get(pctldev, pins[0], config);
return rc;
}
int aspeed_pin_config_group_set(struct pinctrl_dev *pctldev,
unsigned int selector,
unsigned long *configs,
unsigned int num_configs)
{
const unsigned int *pins;
unsigned int npins;
int rc;
int i;
pr_debug("%s: Fetching pins for group selector %d\n",
__func__, selector);
rc = aspeed_pinctrl_get_group_pins(pctldev, selector, &pins, &npins);
if (rc < 0)
return rc;
for (i = 0; i < npins; i++) {
rc = aspeed_pin_config_set(pctldev, pins[i], configs,
num_configs);
if (rc < 0)
return rc;
}
return 0;
}
linux-7.2.3/drivers/pinctrl/aspeed/pinctrl-aspeed.h
+119
View File
@@ -0,0 +1,119 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2016 IBM Corp.
*/
#ifndef PINCTRL_ASPEED
#define PINCTRL_ASPEED
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/regmap.h>
#include "pinmux-aspeed.h"
/**
* @param The pinconf parameter type
* @pins The pin range this config struct covers, [low, high]
* @reg The register housing the configuration bits
* @mask The mask to select the bits of interest in @reg
*/
struct aspeed_pin_config {
enum pin_config_param param;
unsigned int pins[2];
unsigned int reg;
u32 mask;
};
#define ASPEED_PINCTRL_PIN(name_) \
[name_] = { \
.number = name_, \
.name = #name_, \
.drv_data = (void *) &(PIN_SYM(name_)) \
}
#define ASPEED_SB_PINCONF(param_, pin0_, pin1_, reg_, bit_) { \
.param = param_, \
.pins = {pin0_, pin1_}, \
.reg = reg_, \
.mask = BIT_MASK(bit_) \
}
#define ASPEED_PULL_DOWN_PINCONF(pin_, reg_, bit_) \
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, pin_, pin_, reg_, bit_), \
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, pin_, pin_, reg_, bit_)
#define ASPEED_PULL_UP_PINCONF(pin_, reg_, bit_) \
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_UP, pin_, pin_, reg_, bit_), \
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, pin_, pin_, reg_, bit_)
/*
* Aspeed pin configuration description.
*
* @param: pinconf configuration parameter
* @arg: The supported argument for @param, or -1 if any value is supported
* @val: The register value to write to configure @arg for @param
* @mask: The bitfield mask for @val
*
* The map is to be used in conjunction with the configuration array supplied
* by the driver implementation.
*/
struct aspeed_pin_config_map {
enum pin_config_param param;
s32 arg;
u32 val;
u32 mask;
};
struct aspeed_pinctrl_data {
struct regmap *scu;
const struct pinctrl_pin_desc *pins;
const unsigned int npins;
const struct aspeed_pin_config *configs;
const unsigned int nconfigs;
struct aspeed_pinmux_data pinmux;
const struct aspeed_pin_config_map *confmaps;
const unsigned int nconfmaps;
};
/* Aspeed pinctrl helpers */
int aspeed_pinctrl_get_groups_count(struct pinctrl_dev *pctldev);
const char *aspeed_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned int group);
int aspeed_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int group, const unsigned int **pins,
unsigned int *npins);
void aspeed_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned int offset);
int aspeed_pinmux_get_fn_count(struct pinctrl_dev *pctldev);
const char *aspeed_pinmux_get_fn_name(struct pinctrl_dev *pctldev,
unsigned int function);
int aspeed_pinmux_get_fn_groups(struct pinctrl_dev *pctldev,
unsigned int function, const char * const **groups,
unsigned int * const num_groups);
int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
unsigned int group);
int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset);
int aspeed_pinctrl_probe(struct platform_device *pdev,
const struct pinctrl_desc *pdesc,
struct aspeed_pinctrl_data *pdata);
int aspeed_pin_config_get(struct pinctrl_dev *pctldev, unsigned int offset,
unsigned long *config);
int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset,
unsigned long *configs, unsigned int num_configs);
int aspeed_pin_config_group_get(struct pinctrl_dev *pctldev,
unsigned int selector,
unsigned long *config);
int aspeed_pin_config_group_set(struct pinctrl_dev *pctldev,
unsigned int selector,
unsigned long *configs,
unsigned int num_configs);
#endif /* PINCTRL_ASPEED */
linux-7.2.3/drivers/pinctrl/aspeed/pinmux-aspeed.c
+101
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@@ -0,0 +1,101 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/* Copyright (C) 2019 IBM Corp. */
/* Pieces to enable drivers to implement the .set callback */
#include "pinmux-aspeed.h"
static const char *const aspeed_pinmux_ips[] = {
[ASPEED_IP_SCU] = "SCU",
[ASPEED_IP_GFX] = "GFX",
[ASPEED_IP_LPC] = "LPC",
};
static inline void aspeed_sig_desc_print_val(
const struct aspeed_sig_desc *desc, bool enable, u32 rv)
{
pr_debug("Want %s%X[0x%08X]=0x%X, got 0x%X from 0x%08X\n",
aspeed_pinmux_ips[desc->ip], desc->reg,
desc->mask, enable ? desc->enable : desc->disable,
(rv & desc->mask) >> __ffs(desc->mask), rv);
}
/**
* aspeed_sig_desc_eval() - Query the enabled or disabled state of a signal
* descriptor.
*
* @desc: The signal descriptor of interest
* @enabled: True to query the enabled state, false to query disabled state
* @map: The IP block's regmap instance
*
* Return: 1 if the descriptor's bitfield is configured to the state
* selected by @enabled, 0 if not, and less than zero if an unrecoverable
* failure occurred
*
* Evaluation of descriptor state is non-trivial in that it is not a binary
* outcome: The bitfields can be greater than one bit in size and thus can take
* a value that is neither the enabled nor disabled state recorded in the
* descriptor (typically this means a different function to the one of interest
* is enabled). Thus we must explicitly test for either condition as required.
*/
int aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc,
bool enabled, struct regmap *map)
{
int ret;
unsigned int raw;
u32 want;
if (!map)
return -ENODEV;
ret = regmap_read(map, desc->reg, &raw);
if (ret)
return ret;
aspeed_sig_desc_print_val(desc, enabled, raw);
want = enabled ? desc->enable : desc->disable;
return ((raw & desc->mask) >> __ffs(desc->mask)) == want;
}
/**
* aspeed_sig_expr_eval - Query the enabled or disabled state for a
* mux function's signal on a pin
*
* @ctx: The driver context for the pinctrl IP
* @expr: An expression controlling the signal for a mux function on a pin
* @enabled: True to query the enabled state, false to query disabled state
*
* Return: 1 if the expression composed by @enabled evaluates true, 0 if not,
* and less than zero if an unrecoverable failure occurred.
*
* A mux function is enabled or disabled if the function's signal expression
* for each pin in the function's pin group evaluates true for the desired
* state. An signal expression evaluates true if all of its associated signal
* descriptors evaluate true for the desired state.
*
* If an expression's state is described by more than one bit, either through
* multi-bit bitfields in a single signal descriptor or through multiple signal
* descriptors of a single bit then it is possible for the expression to be in
* neither the enabled nor disabled state. Thus we must explicitly test for
* either condition as required.
*/
int aspeed_sig_expr_eval(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr, bool enabled)
{
int ret;
int i;
if (ctx->ops->eval)
return ctx->ops->eval(ctx, expr, enabled);
for (i = 0; i < expr->ndescs; i++) {
const struct aspeed_sig_desc *desc = &expr->descs[i];
ret = aspeed_sig_desc_eval(desc, enabled, ctx->maps[desc->ip]);
if (ret <= 0)
return ret;
}
return 1;
}
linux-7.2.3/drivers/pinctrl/aspeed/pinmux-aspeed.h
+821
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@@ -0,0 +1,821 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* Copyright (C) 2019 IBM Corp. */
#ifndef ASPEED_PINMUX_H
#define ASPEED_PINMUX_H
#include <linux/regmap.h>
/*
* The ASPEED SoCs provide typically more than 200 pins for GPIO and other
* functions. The SoC function enabled on a pin is determined on a priority
* basis where a given pin can provide a number of different signal types.
*
* The signal active on a pin is described by both a priority level and
* compound logical expressions involving multiple operators, registers and
* bits. Some difficulty arises as the pin's function bit masks for each
* priority level are frequently not the same (i.e. cannot just flip a bit to
* change from a high to low priority signal), or even in the same register.
* Further, not all signals can be unmuxed, as some expressions depend on
* values in the hardware strapping register (which may be treated as
* read-only).
*
* SoC Multi-function Pin Expression Examples
* ------------------------------------------
*
* Here are some sample mux configurations from the AST2400 and AST2500
* datasheets to illustrate the corner cases, roughly in order of least to most
* corner. The signal priorities are in decending order from P0 (highest).
*
* D6 is a pin with a single function (beside GPIO); a high priority signal
* that participates in one function:
*
* Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
* -----+---------+-----------+-----------------------------+-----------+---------------+----------
* D6 GPIOA0 MAC1LINK SCU80[0]=1 GPIOA0
* -----+---------+-----------+-----------------------------+-----------+---------------+----------
*
* C5 is a multi-signal pin (high and low priority signals). Here we touch
* different registers for the different functions that enable each signal:
*
* -----+---------+-----------+-----------------------------+-----------+---------------+----------
* C5 GPIOA4 SCL9 SCU90[22]=1 TIMER5 SCU80[4]=1 GPIOA4
* -----+---------+-----------+-----------------------------+-----------+---------------+----------
*
* E19 is a single-signal pin with two functions that influence the active
* signal. In this case both bits have the same meaning - enable a dedicated
* LPC reset pin. However it's not always the case that the bits in the
* OR-relationship have the same meaning.
*
* -----+---------+-----------+-----------------------------+-----------+---------------+----------
* E19 GPIOB4 LPCRST# SCU80[12]=1 | Strap[14]=1 GPIOB4
* -----+---------+-----------+-----------------------------+-----------+---------------+----------
*
* For example, pin B19 has a low-priority signal that's enabled by two
* distinct SoC functions: A specific SIOPBI bit in register SCUA4, and an ACPI
* bit in the STRAP register. The ACPI bit configures signals on pins in
* addition to B19. Both of the low priority functions as well as the high
* priority function must be disabled for GPIOF1 to be used.
*
* Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
* -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
* B19 GPIOF1 NDCD4 SCU80[25]=1 SIOPBI# SCUA4[12]=1 | Strap[19]=0 GPIOF1
* -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
*
* For pin E18, the SoC ANDs the expected state of three bits to determine the
* pin's active signal:
*
* * SCU3C[3]: Enable external SOC reset function
* * SCU80[15]: Enable SPICS1# or EXTRST# function pin
* * SCU90[31]: Select SPI interface CS# output
*
* -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
* E18 GPIOB7 EXTRST# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=0 SPICS1# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=1 GPIOB7
* -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
*
* (Bits SCU3C[3] and SCU80[15] appear to only be used in the expressions for
* selecting the signals on pin E18)
*
* Pin T5 is a multi-signal pin with a more complex configuration:
*
* Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
* -----+---------+-----------+------------------------------+-----------+---------------+----------
* T5 GPIOL1 VPIDE SCU90[5:4]!=0 & SCU84[17]=1 NDCD1 SCU84[17]=1 GPIOL1
* -----+---------+-----------+------------------------------+-----------+---------------+----------
*
* The high priority signal configuration is best thought of in terms of its
* exploded form, with reference to the SCU90[5:4] bits:
*
* * SCU90[5:4]=00: disable
* * SCU90[5:4]=01: 18 bits (R6/G6/B6) video mode.
* * SCU90[5:4]=10: 24 bits (R8/G8/B8) video mode.
* * SCU90[5:4]=11: 30 bits (R10/G10/B10) video mode.
*
* Re-writing:
*
* -----+---------+-----------+------------------------------+-----------+---------------+----------
* T5 GPIOL1 VPIDE (SCU90[5:4]=1 & SCU84[17]=1) NDCD1 SCU84[17]=1 GPIOL1
* | (SCU90[5:4]=2 & SCU84[17]=1)
* | (SCU90[5:4]=3 & SCU84[17]=1)
* -----+---------+-----------+------------------------------+-----------+---------------+----------
*
* For reference the SCU84[17] bit configure the "UART1 NDCD1 or Video VPIDE
* function pin", where the signal itself is determined by whether SCU94[5:4]
* is disabled or in one of the 18, 24 or 30bit video modes.
*
* Other video-input-related pins require an explicit state in SCU90[5:4], e.g.
* W1 and U5:
*
* -----+---------+-----------+------------------------------+-----------+---------------+----------
* W1 GPIOL6 VPIB0 SCU90[5:4]=3 & SCU84[22]=1 TXD1 SCU84[22]=1 GPIOL6
* U5 GPIOL7 VPIB1 SCU90[5:4]=3 & SCU84[23]=1 RXD1 SCU84[23]=1 GPIOL7
* -----+---------+-----------+------------------------------+-----------+---------------+----------
*
* The examples of T5 and W1 are particularly fertile, as they also demonstrate
* that despite operating as part of the video input bus each signal needs to
* be enabled individually via it's own SCU84 (in the cases of T5 and W1)
* register bit. This is a little crazy if the bus doesn't have optional
* signals, but is used to decent effect with some of the UARTs where not all
* signals are required. However, this isn't done consistently - UART1 is
* enabled on a per-pin basis, and by contrast, all signals for UART6 are
* enabled by a single bit.
*
* Further, the high and low priority signals listed in the table above share
* a configuration bit. The VPI signals should operate in concert in a single
* function, but the UART signals should retain the ability to be configured
* independently. This pushes the implementation down the path of tagging a
* signal's expressions with the function they participate in, rather than
* defining masks affecting multiple signals per function. The latter approach
* fails in this instance where applying the configuration for the UART pin of
* interest will stomp on the state of other UART signals when disabling the
* VPI functions on the current pin.
*
* Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
* -----+------------+-----------+---------------------------+-----------+---------------+------------
* A12 RGMII1TXCK GPIOT0 SCUA0[0]=1 RMII1TXEN Strap[6]=0 RGMII1TXCK
* B12 RGMII1TXCTL GPIOT1 SCUA0[1]=1 – Strap[6]=0 RGMII1TXCTL
* -----+------------+-----------+---------------------------+-----------+---------------+------------
*
* A12 demonstrates that the "Other" signal isn't always GPIO - in this case
* GPIOT0 is a high-priority signal and RGMII1TXCK is Other. Thus, GPIO
* should be treated like any other signal type with full function expression
* requirements, and not assumed to be the default case. Separately, GPIOT0 and
* GPIOT1's signal descriptor bits are distinct, therefore we must iterate all
* pins in the function's group to disable the higher-priority signals such
* that the signal for the function of interest is correctly enabled.
*
* Finally, three priority levels aren't always enough; the AST2500 brings with
* it 18 pins of five priority levels, however the 18 pins only use three of
* the five priority levels.
*
* Ultimately the requirement to control pins in the examples above drive the
* design:
*
* * Pins provide signals according to functions activated in the mux
* configuration
*
* * Pins provide up to five signal types in a priority order
*
* * For priorities levels defined on a pin, each priority provides one signal
*
* * Enabling lower priority signals requires higher priority signals be
* disabled
*
* * A function represents a set of signals; functions are distinct if they
* do not share a subset of signals (and may be distinct if they are a
* strict subset).
*
* * Signals participate in one or more functions or groups
*
* * A function is described by an expression of one or more signal
* descriptors, which compare bit values in a register
*
* * A signal expression is the smallest set of signal descriptors whose
* comparisons must evaluate 'true' for a signal to be enabled on a pin.
*
* * A signal participating in a function is active on a pin if evaluating all
* signal descriptors in the pin's signal expression for the function yields
* a 'true' result
*
* * A signal at a given priority on a given pin is active if any of the
* functions in which the signal participates are active, and no higher
* priority signal on the pin is active
*
* * GPIO is configured per-pin
*
* And so:
*
* * To disable a signal, any function(s) activating the signal must be
* disabled
*
* * Each pin must know the signal expressions of functions in which it
* participates, for the purpose of enabling the Other function. This is done
* by deactivating all functions that activate higher priority signals on the
* pin.
*
* As a concrete example:
*
* * T5 provides three signals types: VPIDE, NDCD1 and GPIO
*
* * The VPIDE signal participates in 3 functions: VPI18, VPI24 and VPI30
*
* * The NDCD1 signal participates in just its own NDCD1 function
*
* * VPIDE is high priority, NDCD1 is low priority, and GPIOL1 is the least
* prioritised
*
* * The prerequisit for activating the NDCD1 signal is that the VPI18, VPI24
* and VPI30 functions all be disabled
*
* * Similarly, all of VPI18, VPI24, VPI30 and NDCD1 functions must be disabled
* to provide GPIOL6
*
* Considerations
* --------------
*
* If pinctrl allows us to allocate a pin we can configure a function without
* concern for the function of already allocated pins, if pin groups are
* created with respect to the SoC functions in which they participate. This is
* intuitive, but it did not feel obvious from the bit/pin relationships.
*
* Conversely, failing to allocate all pins in a group indicates some bits (as
* well as pins) required for the group's configuration will already be in use,
* likely in a way that's inconsistent with the requirements of the failed
* group.
*
* Implementation
* --------------
*
* Beyond the documentation below the various structures and helper macros that
* allow the implementation to hang together are defined. The macros are fairly
* dense, so below we walk through some raw examples of the configuration
* tables in an effort to clarify the concepts.
*
* The complexity of configuring the mux combined with the scale of the pins
* and functions was a concern, so the table design along with the macro jungle
* is an attempt to address it. The rough principles of the approach are:
*
* 1. Use a data-driven solution rather than embedding state into code
* 2. Minimise editing to the specifics of the given mux configuration
* 3. Detect as many errors as possible at compile time
*
* Addressing point 3 leads to naming of symbols in terms of the four
* properties associated with a given mux configuration: The pin, the signal,
* the group and the function. In this way copy/paste errors cause duplicate
* symbols to be defined, which prevents successful compilation. Failing to
* properly parent the tables leads to unused symbol warnings, and use of
* designated initialisers and additional warnings ensures that there are
* no override errors in the pin, group and function arrays.
*
* Addressing point 2 drives the development of the macro jungle, as it
* centralises the definition noise at the cost of taking some time to
* understand.
*
* Here's a complete, concrete "pre-processed" example of the table structures
* used to describe the D6 ball from the examples above:
*
* ```
* static const struct aspeed_sig_desc sig_descs_MAC1LINK_MAC1LINK[] = {
* {
* .ip = ASPEED_IP_SCU,
* .reg = 0x80,
* .mask = BIT(0),
* .enable = 1,
* .disable = 0
* },
* };
*
* static const struct aspeed_sig_expr sig_expr_MAC1LINK_MAC1LINK = {
* .signal = "MAC1LINK",
* .function = "MAC1LINK",
* .ndescs = ARRAY_SIZE(sig_descs_MAC1LINK_MAC1LINK),
* .descs = &(sig_descs_MAC1LINK_MAC1LINK)[0],
* };
*
* static const struct aspeed_sig_expr *sig_exprs_MAC1LINK_MAC1LINK[] = {
* &sig_expr_MAC1LINK_MAC1LINK,
* NULL,
* };
*
* static const struct aspeed_sig_desc sig_descs_GPIOA0_GPIOA0[] = { };
*
* static const struct aspeed_sig_expr sig_expr_GPIOA0_GPIOA0 = {
* .signal = "GPIOA0",
* .function = "GPIOA0",
* .ndescs = ARRAY_SIZE(sig_descs_GPIOA0_GPIOA0),
* .descs = &(sig_descs_GPIOA0_GPIOA0)[0],
* };
*
* static const struct aspeed_sig_expr *sig_exprs_GPIOA0_GPIOA0[] = {
* &sig_expr_GPIOA0_GPIOA0,
* NULL
* };
*
* static const struct aspeed_sig_expr **pin_exprs_0[] = {
* sig_exprs_MAC1LINK_MAC1LINK,
* sig_exprs_GPIOA0_GPIOA0,
* NULL
* };
*
* static const struct aspeed_pin_desc pin_0 = { "0", (&pin_exprs_0[0]) };
* static const int group_pins_MAC1LINK[] = { 0 };
* static const char *func_groups_MAC1LINK[] = { "MAC1LINK" };
*
* static struct pinctrl_pin_desc aspeed_g4_pins[] = {
* [0] = { .number = 0, .name = "D6", .drv_data = &pin_0 },
* };
*
* static const struct aspeed_pin_group aspeed_g4_groups[] = {
* {
* .name = "MAC1LINK",
* .pins = &(group_pins_MAC1LINK)[0],
* .npins = ARRAY_SIZE(group_pins_MAC1LINK),
* },
* };
*
* static const struct aspeed_pin_function aspeed_g4_functions[] = {
* {
* .name = "MAC1LINK",
* .groups = &func_groups_MAC1LINK[0],
* .ngroups = ARRAY_SIZE(func_groups_MAC1LINK),
* },
* };
* ```
*
* At the end of the day much of the above code is compressed into the
* following two lines:
*
* ```
* #define D6 0
* SSSF_PIN_DECL(D6, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0));
* ```
*
* The two examples below show just the differences from the example above.
*
* Ball E18 demonstrates a function, EXTRST, that requires multiple descriptors
* be set for it to be muxed:
*
* ```
* static const struct aspeed_sig_desc sig_descs_EXTRST_EXTRST[] = {
* {
* .ip = ASPEED_IP_SCU,
* .reg = 0x3C,
* .mask = BIT(3),
* .enable = 1,
* .disable = 0
* },
* {
* .ip = ASPEED_IP_SCU,
* .reg = 0x80,
* .mask = BIT(15),
* .enable = 1,
* .disable = 0
* },
* {
* .ip = ASPEED_IP_SCU,
* .reg = 0x90,
* .mask = BIT(31),
* .enable = 0,
* .disable = 1
* },
* };
*
* static const struct aspeed_sig_expr sig_expr_EXTRST_EXTRST = {
* .signal = "EXTRST",
* .function = "EXTRST",
* .ndescs = ARRAY_SIZE(sig_descs_EXTRST_EXTRST),
* .descs = &(sig_descs_EXTRST_EXTRST)[0],
* };
* ...
* ```
*
* For ball E19, we have multiple functions enabling a single signal, LPCRST#.
* The data structures look like:
*
* static const struct aspeed_sig_desc sig_descs_LPCRST_LPCRST[] = {
* {
* .ip = ASPEED_IP_SCU,
* .reg = 0x80,
* .mask = BIT(12),
* .enable = 1,
* .disable = 0
* },
* };
*
* static const struct aspeed_sig_expr sig_expr_LPCRST_LPCRST = {
* .signal = "LPCRST",
* .function = "LPCRST",
* .ndescs = ARRAY_SIZE(sig_descs_LPCRST_LPCRST),
* .descs = &(sig_descs_LPCRST_LPCRST)[0],
* };
*
* static const struct aspeed_sig_desc sig_descs_LPCRST_LPCRSTS[] = {
* {
* .ip = ASPEED_IP_SCU,
* .reg = 0x70,
* .mask = BIT(14),
* .enable = 1,
* .disable = 0
* },
* };
*
* static const struct aspeed_sig_expr sig_expr_LPCRST_LPCRSTS = {
* .signal = "LPCRST",
* .function = "LPCRSTS",
* .ndescs = ARRAY_SIZE(sig_descs_LPCRST_LPCRSTS),
* .descs = &(sig_descs_LPCRST_LPCRSTS)[0],
* };
*
* static const struct aspeed_sig_expr *sig_exprs_LPCRST_LPCRST[] = {
* &sig_expr_LPCRST_LPCRST,
* &sig_expr_LPCRST_LPCRSTS,
* NULL,
* };
* ...
* ```
*
* Both expressions listed in the sig_exprs_LPCRST_LPCRST array need to be set
* to disabled for the associated GPIO to be muxed.
*
*/
#define ASPEED_IP_SCU 0
#define ASPEED_IP_GFX 1
#define ASPEED_IP_LPC 2
#define ASPEED_NR_PINMUX_IPS 3
/**
* A signal descriptor, which describes the register, bits and the
* enable/disable values that should be compared or written.
*
* @ip: The IP block identifier, used as an index into the regmap array in
* struct aspeed_pinctrl_data
* @reg: The register offset with respect to the base address of the IP block
* @mask: The mask to apply to the register. The lowest set bit of the mask is
* used to derive the shift value.
* @enable: The value that enables the function. Value should be in the LSBs,
* not at the position of the mask.
* @disable: The value that disables the function. Value should be in the
* LSBs, not at the position of the mask.
*/
struct aspeed_sig_desc {
unsigned int ip;
unsigned int reg;
u32 mask;
u32 enable;
u32 disable;
};
/**
* Describes a signal expression. The expression is evaluated by ANDing the
* evaluation of the descriptors.
*
* @signal: The signal name for the priority level on the pin. If the signal
* type is GPIO, then the signal name must begin with the
* prefix "GPI", e.g. GPIOA0, GPIT0 etc.
* @function: The name of the function the signal participates in for the
* associated expression. For pin-specific GPIO, the function
* name must match the signal name.
* @ndescs: The number of signal descriptors in the expression
* @descs: Pointer to an array of signal descriptors that comprise the
* function expression
*/
struct aspeed_sig_expr {
const char *signal;
const char *function;
int ndescs;
const struct aspeed_sig_desc *descs;
};
/**
* A struct capturing the list of expressions enabling signals at each priority
* for a given pin. The signal configuration for a priority level is evaluated
* by ORing the evaluation of the signal expressions in the respective
* priority's list.
*
* @name: A name for the pin
* @prios: A pointer to an array of expression list pointers
*
*/
struct aspeed_pin_desc {
const char *name;
const struct aspeed_sig_expr ***prios;
};
/* Macro hell */
#define SIG_DESC_IP_BIT(ip, reg, idx, val) \
{ ip, reg, BIT_MASK(idx), val, (((val) + 1) & 1) }
/**
* Short-hand macro for describing an SCU descriptor enabled by the state of
* one bit. The disable value is derived.
*
* @reg: The signal's associated register, offset from base
* @idx: The signal's bit index in the register
* @val: The value (0 or 1) that enables the function
*/
#define SIG_DESC_BIT(reg, idx, val) \
SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, val)
#define SIG_DESC_IP_SET(ip, reg, idx) SIG_DESC_IP_BIT(ip, reg, idx, 1)
/**
* A further short-hand macro expanding to an SCU descriptor enabled by a set
* bit.
*
* @reg: The register, offset from base
* @idx: The bit index in the register
*/
#define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1)
#define SIG_DESC_CLEAR(reg, idx) { ASPEED_IP_SCU, reg, BIT_MASK(idx), 0, 0 }
#define SIG_DESC_LIST_SYM(sig, group) sig_descs_ ## sig ## _ ## group
#define SIG_DESC_LIST_DECL(sig, group, ...) \
static const struct aspeed_sig_desc SIG_DESC_LIST_SYM(sig, group)[] = \
{ __VA_ARGS__ }
#define SIG_EXPR_SYM(sig, group) sig_expr_ ## sig ## _ ## group
#define SIG_EXPR_DECL_(sig, group, func) \
static const struct aspeed_sig_expr SIG_EXPR_SYM(sig, group) = \
{ \
.signal = #sig, \
.function = #func, \
.ndescs = ARRAY_SIZE(SIG_DESC_LIST_SYM(sig, group)), \
.descs = &(SIG_DESC_LIST_SYM(sig, group))[0], \
}
/**
* Declare a signal expression.
*
* @sig: A macro symbol name for the signal (is subjected to stringification
* and token pasting)
* @func: The function in which the signal is participating
* @...: Signal descriptors that define the signal expression
*
* For example, the following declares the ROMD8 signal for the ROM16 function:
*
* SIG_EXPR_DECL(ROMD8, ROM16, ROM16, SIG_DESC_SET(SCU90, 6));
*
* And with multiple signal descriptors:
*
* SIG_EXPR_DECL(ROMD8, ROM16S, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
* { HW_STRAP1, GENMASK(1, 0), 0, 0 });
*/
#define SIG_EXPR_DECL(sig, group, func, ...) \
SIG_DESC_LIST_DECL(sig, group, __VA_ARGS__); \
SIG_EXPR_DECL_(sig, group, func)
/**
* Declare a pointer to a signal expression
*
* @sig: The macro symbol name for the signal (subjected to token pasting)
* @func: The macro symbol name for the function (subjected to token pasting)
*/
#define SIG_EXPR_PTR(sig, group) (&SIG_EXPR_SYM(sig, group))
#define SIG_EXPR_LIST_SYM(sig, group) sig_exprs_ ## sig ## _ ## group
/**
* Declare a signal expression list for reference in a struct aspeed_pin_prio.
*
* @sig: A macro symbol name for the signal (is subjected to token pasting)
* @...: Signal expression structure pointers (use SIG_EXPR_PTR())
*
* For example, the 16-bit ROM bus can be enabled by one of two possible signal
* expressions:
*
* SIG_EXPR_DECL(ROMD8, ROM16, ROM16, SIG_DESC_SET(SCU90, 6));
* SIG_EXPR_DECL(ROMD8, ROM16S, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
* { HW_STRAP1, GENMASK(1, 0), 0, 0 });
* SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
* SIG_EXPR_PTR(ROMD8, ROM16S));
*/
#define SIG_EXPR_LIST_DECL(sig, group, ...) \
static const struct aspeed_sig_expr *SIG_EXPR_LIST_SYM(sig, group)[] =\
{ __VA_ARGS__, NULL }
#define stringify(x) #x
#define istringify(x) stringify(x)
/**
* Create an expression symbol alias from (signal, group) to (pin, signal).
*
* @pin: The pin number
* @sig: The signal name
* @group: The name of the group of which the pin is a member that is
* associated with the function's signal
*
* Using an alias in this way enables detection of copy/paste errors (defining
* the signal for a group multiple times) whilst enabling multiple pin groups
* to exist for a signal without intrusive side-effects on defining the list of
* signals available on a pin.
*/
#define SIG_EXPR_LIST_ALIAS(pin, sig, group) \
static const struct aspeed_sig_expr *\
SIG_EXPR_LIST_SYM(pin, sig)[ARRAY_SIZE(SIG_EXPR_LIST_SYM(sig, group))] \
__attribute__((alias(istringify(SIG_EXPR_LIST_SYM(sig, group)))))
/**
* A short-hand macro for declaring a function expression and an expression
* list with a single expression (SE) and a single group (SG) of pins.
*
* @pin: The pin the signal will be routed to
* @sig: The signal that will be routed to the pin for the function
* @func: A macro symbol name for the function
* @...: Function descriptors that define the function expression
*
* For example, signal NCTS6 participates in its own function with one group:
*
* SIG_EXPR_LIST_DECL_SINGLE(A18, NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
*/
#define SIG_EXPR_LIST_DECL_SESG(pin, sig, func, ...) \
SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \
SIG_EXPR_DECL_(sig, func, func); \
SIG_EXPR_LIST_DECL(sig, func, SIG_EXPR_PTR(sig, func)); \
SIG_EXPR_LIST_ALIAS(pin, sig, func)
/**
* Similar to the above, but for pins with a single expression (SE) and
* multiple groups (MG) of pins.
*
* @pin: The pin the signal will be routed to
* @sig: The signal that will be routed to the pin for the function
* @group: The name of the function's pin group in which the pin participates
* @func: A macro symbol name for the function
* @...: Function descriptors that define the function expression
*/
#define SIG_EXPR_LIST_DECL_SEMG(pin, sig, group, func, ...) \
SIG_DESC_LIST_DECL(sig, group, __VA_ARGS__); \
SIG_EXPR_DECL_(sig, group, func); \
SIG_EXPR_LIST_DECL(sig, group, SIG_EXPR_PTR(sig, group)); \
SIG_EXPR_LIST_ALIAS(pin, sig, group)
/**
* Similar to the above, but for pins with a dual expressions (DE)
* and a single group (SG) of pins.
*
* @pin: The pin the signal will be routed to
* @sig: The signal that will be routed to the pin for the function
* @group: The name of the function's pin group in which the pin participates
* @func: A macro symbol name for the function
* @...: Function descriptors that define the function expression
*/
#define SIG_EXPR_LIST_DECL_DESG(pin, sig, f0, f1) \
SIG_EXPR_LIST_DECL(sig, f0, \
SIG_EXPR_PTR(sig, f0), \
SIG_EXPR_PTR(sig, f1)); \
SIG_EXPR_LIST_ALIAS(pin, sig, f0)
#define SIG_EXPR_LIST_PTR(sig, group) SIG_EXPR_LIST_SYM(sig, group)
#define PIN_EXPRS_SYM(pin) pin_exprs_ ## pin
#define PIN_EXPRS_PTR(pin) (&PIN_EXPRS_SYM(pin)[0])
#define PIN_SYM(pin) pin_ ## pin
#define PIN_DECL_(pin, ...) \
static const struct aspeed_sig_expr **PIN_EXPRS_SYM(pin)[] = \
{ __VA_ARGS__, NULL }; \
static const struct aspeed_pin_desc PIN_SYM(pin) = \
{ #pin, PIN_EXPRS_PTR(pin) }
/**
* Declare a single signal pin
*
* @pin: The pin number
* @other: Macro name for "other" functionality (subjected to stringification)
* @sig: Macro name for the signal (subjected to stringification)
*
* For example:
*
* #define E3 80
* SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC);
* PIN_DECL_1(E3, GPIOK0, SCL5);
*/
#define PIN_DECL_1(pin, other, sig) \
SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, sig), \
SIG_EXPR_LIST_PTR(pin, other))
/**
* Single signal, single function pin declaration
*
* @pin: The pin number
* @other: Macro name for "other" functionality (subjected to stringification)
* @sig: Macro name for the signal (subjected to stringification)
* @...: Signal descriptors that define the function expression
*
* For example:
*
* SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2));
*/
#define SSSF_PIN_DECL(pin, other, sig, ...) \
SIG_EXPR_LIST_DECL_SESG(pin, sig, sig, __VA_ARGS__); \
SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, sig), \
SIG_EXPR_LIST_PTR(pin, other)); \
FUNC_GROUP_DECL(sig, pin)
/**
* Declare a two-signal pin
*
* @pin: The pin number
* @other: Macro name for "other" functionality (subjected to stringification)
* @high: Macro name for the highest priority signal functions
* @low: Macro name for the low signal functions
*
* For example:
*
* #define A8 56
* SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
* SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
* { HW_STRAP1, GENMASK(1, 0), 0, 0 });
* SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
* SIG_EXPR_PTR(ROMD8, ROM16S));
* SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
* PIN_DECL_2(A8, GPIOH0, ROMD8, NCTS6);
*/
#define PIN_DECL_2(pin, other, high, low) \
SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
PIN_DECL_(pin, \
SIG_EXPR_LIST_PTR(pin, high), \
SIG_EXPR_LIST_PTR(pin, low), \
SIG_EXPR_LIST_PTR(pin, other))
#define PIN_DECL_3(pin, other, high, medium, low) \
SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
PIN_DECL_(pin, \
SIG_EXPR_LIST_PTR(pin, high), \
SIG_EXPR_LIST_PTR(pin, medium), \
SIG_EXPR_LIST_PTR(pin, low), \
SIG_EXPR_LIST_PTR(pin, other))
#define PIN_DECL_4(pin, other, prio1, prio2, prio3, prio4) \
SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
PIN_DECL_(pin, \
SIG_EXPR_LIST_PTR(pin, prio1), \
SIG_EXPR_LIST_PTR(pin, prio2), \
SIG_EXPR_LIST_PTR(pin, prio3), \
SIG_EXPR_LIST_PTR(pin, prio4), \
SIG_EXPR_LIST_PTR(pin, other))
#define GROUP_SYM(group) group_pins_ ## group
#define GROUP_DECL(group, ...) \
static const int GROUP_SYM(group)[] = { __VA_ARGS__ }
#define FUNC_SYM(func) func_groups_ ## func
#define FUNC_DECL_(func, ...) \
static const char *FUNC_SYM(func)[] = { __VA_ARGS__ }
#define FUNC_DECL_1(func, group) FUNC_DECL_(func, #group)
#define FUNC_DECL_2(func, one, two) FUNC_DECL_(func, #one, #two)
#define FUNC_DECL_3(func, one, two, three) FUNC_DECL_(func, #one, #two, #three)
#define FUNC_GROUP_DECL(func, ...) \
GROUP_DECL(func, __VA_ARGS__); \
FUNC_DECL_(func, #func)
#define GPIO_PIN_DECL(pin, gpio) \
SIG_EXPR_LIST_DECL_SESG(pin, gpio, gpio); \
PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, gpio))
struct aspeed_pin_group {
const char *name;
const unsigned int *pins;
const unsigned int npins;
};
#define ASPEED_PINCTRL_GROUP(name_) { \
.name = #name_, \
.pins = &(GROUP_SYM(name_))[0], \
.npins = ARRAY_SIZE(GROUP_SYM(name_)), \
}
struct aspeed_pin_function {
const char *name;
const char *const *groups;
unsigned int ngroups;
};
#define ASPEED_PINCTRL_FUNC(name_, ...) { \
.name = #name_, \
.groups = &FUNC_SYM(name_)[0], \
.ngroups = ARRAY_SIZE(FUNC_SYM(name_)), \
}
struct aspeed_pinmux_data;
struct aspeed_pinmux_ops {
int (*eval)(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr, bool enabled);
int (*set)(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr, bool enabled);
};
struct aspeed_pinmux_data {
struct device *dev;
struct regmap *maps[ASPEED_NR_PINMUX_IPS];
const struct aspeed_pinmux_ops *ops;
const struct aspeed_pin_group *groups;
const unsigned int ngroups;
const struct aspeed_pin_function *functions;
const unsigned int nfunctions;
};
int aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc, bool enabled,
struct regmap *map);
int aspeed_sig_expr_eval(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr, bool enabled);
static inline int aspeed_sig_expr_set(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr,
bool enabled)
{
return ctx->ops->set(ctx, expr, enabled);
}
#endif /* ASPEED_PINMUX_H */