81 lines
2.8 KiB
YAML
81 lines
2.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-aon.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra264 AON Pinmux Controller
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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properties:
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compatible:
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const: nvidia,tegra264-pinmux-aon
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reg:
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maxItems: 1
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patternProperties:
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"^pinmux(-[a-z0-9-]+)?$":
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type: object
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# pin groups
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additionalProperties:
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$ref: nvidia,tegra264-pinmux-common.yaml
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properties:
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nvidia,pins:
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items:
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enum: [ soc_gpio00_paa0, vcomp_alert_paa1, ao_retention_n_paa2,
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batt_oc_paa3, bootv_ctl_n_paa4, power_on_paa5,
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hdmi_cec_paa6, soc_gpio07_paa7, soc_gpio08_pbb0,
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soc_gpio09_pbb1, gen2_i2c_scl_pcc0, gen2_i2c_sda_pcc1,
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gen3_i2c_scl_pcc2, gen3_i2c_sda_pcc3, gp_pwm4_pcc4,
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uart0_tx_pcc5, uart0_rx_pcc6, spi2_sck_pcc7,
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spi2_miso_pdd0, spi2_mosi_pdd1, spi2_cs0_n_pdd2,
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soc_gpio21_pdd3, soc_gpio22_pdd4, soc_gpio23_pdd5,
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soc_gpio24_pdd6, soc_gpio25_pdd7, soc_gpio26_pee0,
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soc_gpio27_pee1, soc_gpio28_pee2, soc_gpio29_pee3,
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drive_ao_retention_n_paa2, drive_batt_oc_paa3,
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drive_power_on_paa5, drive_vcomp_alert_paa1,
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drive_bootv_ctl_n_paa4, drive_soc_gpio00_paa0,
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drive_soc_gpio07_paa7, drive_soc_gpio08_pbb0,
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drive_soc_gpio09_pbb1, drive_hdmi_cec_paa6,
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drive_gen2_i2c_scl_pcc0, drive_gen2_i2c_sda_pcc1,
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drive_gen3_i2c_scl_pcc2, drive_gen3_i2c_sda_pcc3,
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drive_gp_pwm4_pcc4, drive_uart0_tx_pcc5,
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drive_uart0_rx_pcc6, drive_spi2_sck_pcc7,
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drive_spi2_miso_pdd0, drive_spi2_mosi_pdd1,
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drive_spi2_cs0_n_pdd2, drive_soc_gpio21_pdd3,
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drive_soc_gpio22_pdd4, drive_soc_gpio23_pdd5,
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drive_soc_gpio24_pdd6, drive_soc_gpio25_pdd7,
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drive_soc_gpio26_pee0, drive_soc_gpio27_pee1,
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drive_soc_gpio28_pee2, drive_soc_gpio29_pee3 ]
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/pinctrl/pinctrl-tegra.h>
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pinmux@c7a2000 {
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compatible = "nvidia,tegra264-pinmux-aon";
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reg = <0xc7a2000 0x2000>;
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinmux-default {
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uart0 {
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nvidia,pins = "uart0_tx_pcc5";
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nvidia,function = "uarta_txd";
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};
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};
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};
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