88 lines
2.3 KiB
YAML
88 lines
2.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/soc/renesas/renesas,rzn1-gpioirqmux.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/N1 SoCs GPIO Interrupt Multiplexer
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description: |
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The Renesas RZ/N1 GPIO Interrupt Multiplexer multiplexes GPIO interrupt
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lines to the interrupt controller available in the SoC.
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It selects up to 8 of the 96 GPIO interrupt lines available and connect them
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to 8 output interrupt lines.
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maintainers:
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- Herve Codina <herve.codina@bootlin.com>
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properties:
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compatible:
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items:
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- enum:
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- renesas,r9a06g032-gpioirqmux
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- const: renesas,rzn1-gpioirqmux
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reg:
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maxItems: 1
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"#address-cells":
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const: 0
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"#interrupt-cells":
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const: 1
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interrupt-map-mask:
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items:
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- const: 0x7f
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interrupt-map:
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description: |
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Specifies the mapping from external GPIO interrupt lines to the output
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interrupts. The array has up to 8 items defining the mapping related to
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the output line 0 (GIC 103) up to the output line 7 (GIC 110).
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The child interrupt number set in arrays items is computed using the
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following formula:
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gpio_bank * 32 + gpio_number
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with:
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- gpio_bank: The GPIO bank number
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- 0 for GPIO0A,
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- 1 for GPIO1A,
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- 2 for GPIO2A
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- gpio_number: Number of the gpio in the bank (0..31)
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minItems: 1
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maxItems: 8
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#interrupt-cells"
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- interrupt-map-mask
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- interrupt-map
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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gic: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <3>;
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};
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interrupt-controller@51000480 {
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compatible = "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioirqmux";
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reg = <0x51000480 0x20>;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0x7f>;
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interrupt-map =
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<32 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* line 0, GPIO1A.0 */
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<89 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* line 1, GPIO2A.25 */
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<9 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; /* line 3, GPIO0A.9 */
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};
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