305 lines
16 KiB
ReStructuredText
305 lines
16 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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ACPI PRM CXL Address Translation
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================================
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Document
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--------
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CXL Revision 3.2, Version 1.0
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License
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-------
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SPDX-License Identifier: CC-BY-4.0
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Creator/Contributors
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--------------------
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- Robert Richter, AMD et al.
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Summary of the Change
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---------------------
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The CXL Fixed Memory Window Structures (CFMWS) describe zero or more Host
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Physical Address (HPA) windows associated with one or more CXL Host Bridges.
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Each HPA range of a CXL Host Bridge is represented by a CFMWS entry. An HPA
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range may include addresses currently assigned to CXL.mem devices, or an OS may
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assign ranges from an address window to a device.
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Host-managed Device Memory is Device-attached memory that is mapped to system
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coherent address space and accessible to the Host using standard write-back
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semantics. The managed address range is configured in the CXL HDM Decoder
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registers of the device. An HDM Decoder in a device is responsible for
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converting HPA into DPA by stripping off specific address bits.
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CXL devices and CXL bridges use the same HPA space. It is common across all
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components that belong to the same host domain. The view of the address region
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must be consistent on the CXL.mem path between the Host and the Device.
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This is described in the *CXL 3.2 specification* (Table 1-1, 3.3.1,
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8.2.4.20, 9.13.1, 9.18.1.3). [#cxl-spec-3.2]_
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Depending on the interconnect architecture of the platform, components attached
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to a host may not share the same host physical address space. Those platforms
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need address translation to convert an HPA between the host and the attached
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component, such as a CXL device. The translation mechanism is host-specific and
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implementation dependent.
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For example, x86 AMD platforms use a Data Fabric that manages access to physical
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memory. Devices have their own memory space and can be configured to use
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'Normalized addresses' different from System Physical Addresses (SPA). Address
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translation is then needed. For details, see
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:doc:`x86 AMD Address Translation </admin-guide/RAS/address-translation>`.
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Those AMD platforms provide PRM [#prm-spec]_ handlers in firmware to perform
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various types of address translation, including for CXL endpoints. AMD Zen5
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systems implement the ACPI PRM CXL Address Translation firmware call. The ACPI
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PRM handler has a specific GUID to uniquely identify platforms with support for
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Normalized addressing. This is documented in the *ACPI v6.5 Porting Guide*
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(Address Translation - CXL DPA to System Physical Address). [#amd-ppr-58088]_
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When in Normalized address mode, HDM decoder address ranges must be configured
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and handled differently. Hardware addresses used in the HDM decoder
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configurations of an endpoint are not SPA and need to be translated from the
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address range of the endpoint to that of the CXL host bridge. This is especially
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important for finding an endpoint's associated CXL Host Bridge and HPA window
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described in the CFMWS. Additionally, the interleave decoding is done by the
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Data Fabric and the endpoint does not perform decoding when converting HPA to
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DPA. Instead, interleaving is switched off for the endpoint (1-way). Finally,
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address translation might also be needed to inspect the endpoint's hardware
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addresses, such as during profiling, tracing, or error handling.
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For example, with Normalized addressing the HDM decoders could look as follows::
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-------------------------------
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| Root Decoder (CFMWS) |
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| SPA Range: 0x850000000 |
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| Size: 0x8000000000 (512 GB) |
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| Interleave Ways: 1 |
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-------------------------------
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v
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-------------------------------
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| Host Bridge Decoder (HDM) |
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| SPA Range: 0x850000000 |
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| Size: 0x8000000000 (512 GB) |
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| Interleave Ways: 4 |
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| Targets: endpoint5,8,11,13 |
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| Granularity: 256 |
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-------------------------------
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-----------------------------+------------------------------
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v v v v
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------------------- ------------------- ------------------- -------------------
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| endpoint5 | | endpoint8 | | endpoint11 | | endpoint13 |
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| decoder5.0 | | decoder8.0 | | decoder11.0 | | decoder13.0 |
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| PCIe: | | PCIe: | | PCIe: | | PCIe: |
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| 0000:e2:00.0 | | 0000:e3:00.0 | | 0000:e4:00.0 | | 0000:e1:00.0 |
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| DPA: | | DPA: | | DPA: | | DPA: |
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| Start: 0x0 | | Start: 0x0 | | Start: 0x0 | | Start: 0x0 |
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| Size: | | Size: | | Size: | | Size: |
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| 0x2000000000 | | 0x2000000000 | | 0x2000000000 | | 0x2000000000 |
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| (128 GB) | | (128 GB) | | (128 GB) | | (128 GB) |
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| Interleaving: | | Interleaving: | | Interleaving: | | Interleaving: |
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| Ways: 1 | | Ways: 1 | | Ways: 1 | | Ways: 1 |
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| Gran: 256 | | Gran: 256 | | Gran: 256 | | Gran: 256 |
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------------------- ------------------- ------------------- -------------------
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| | | |
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v v v v
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DPA DPA DPA DPA
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This shows the representation in sysfs:
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.. code-block:: none
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/sys/bus/cxl/devices/endpoint5/decoder5.0/interleave_granularity:256
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/sys/bus/cxl/devices/endpoint5/decoder5.0/interleave_ways:1
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/sys/bus/cxl/devices/endpoint5/decoder5.0/size:0x2000000000
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/sys/bus/cxl/devices/endpoint5/decoder5.0/start:0x0
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/sys/bus/cxl/devices/endpoint8/decoder8.0/interleave_granularity:256
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/sys/bus/cxl/devices/endpoint8/decoder8.0/interleave_ways:1
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/sys/bus/cxl/devices/endpoint8/decoder8.0/size:0x2000000000
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/sys/bus/cxl/devices/endpoint8/decoder8.0/start:0x0
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/sys/bus/cxl/devices/endpoint11/decoder11.0/interleave_granularity:256
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/sys/bus/cxl/devices/endpoint11/decoder11.0/interleave_ways:1
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/sys/bus/cxl/devices/endpoint11/decoder11.0/size:0x2000000000
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/sys/bus/cxl/devices/endpoint11/decoder11.0/start:0x0
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/sys/bus/cxl/devices/endpoint13/decoder13.0/interleave_granularity:256
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/sys/bus/cxl/devices/endpoint13/decoder13.0/interleave_ways:1
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/sys/bus/cxl/devices/endpoint13/decoder13.0/size:0x2000000000
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/sys/bus/cxl/devices/endpoint13/decoder13.0/start:0x0
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Note that the endpoint interleaving configurations use direct mapping (1-way).
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With PRM calls, the kernel can determine the following mappings:
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.. code-block:: none
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cxl decoder5.0: address mapping found for 0000:e2:00.0 (hpa -> spa):
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0x0+0x2000000000 -> 0x850000000+0x8000000000 ways:4 granularity:256
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cxl decoder8.0: address mapping found for 0000:e3:00.0 (hpa -> spa):
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0x0+0x2000000000 -> 0x850000000+0x8000000000 ways:4 granularity:256
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cxl decoder11.0: address mapping found for 0000:e4:00.0 (hpa -> spa):
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0x0+0x2000000000 -> 0x850000000+0x8000000000 ways:4 granularity:256
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cxl decoder13.0: address mapping found for 0000:e1:00.0 (hpa -> spa):
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0x0+0x2000000000 -> 0x850000000+0x8000000000 ways:4 granularity:256
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The corresponding CXL host bridge (HDM) decoders and root decoder (CFMWS) match
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the calculated endpoint mappings shown:
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.. code-block:: none
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/sys/bus/cxl/devices/port1/decoder1.0/interleave_granularity:256
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/sys/bus/cxl/devices/port1/decoder1.0/interleave_ways:4
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/sys/bus/cxl/devices/port1/decoder1.0/size:0x8000000000
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/sys/bus/cxl/devices/port1/decoder1.0/start:0x850000000
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/sys/bus/cxl/devices/port1/decoder1.0/target_list:0,1,2,3
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/sys/bus/cxl/devices/port1/decoder1.0/target_type:expander
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/sys/bus/cxl/devices/root0/decoder0.0/interleave_granularity:256
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/sys/bus/cxl/devices/root0/decoder0.0/interleave_ways:1
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/sys/bus/cxl/devices/root0/decoder0.0/size:0x8000000000
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/sys/bus/cxl/devices/root0/decoder0.0/start:0x850000000
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/sys/bus/cxl/devices/root0/decoder0.0/target_list:7
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The following changes to the specification are needed:
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* Allow a CXL device to be in an HPA space other than the host's address space.
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* Allow the platform to use implementation-specific address translation when
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crossing memory domains on the CXL.mem path between the host and the device.
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* Define a PRM handler method for converting device addresses to SPAs.
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* Specify that the platform shall provide the PRM handler method to the
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Operating System to detect Normalized addressing and for determining Endpoint
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SPA ranges and interleaving configurations.
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* Add reference to:
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| Platform Runtime Mechanism Specification, Version 1.1 – November 2020
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| https://uefi.org/sites/default/files/resources/PRM_Platform_Runtime_Mechanism_1_1_release_candidate.pdf
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Benefits of the Change
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----------------------
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Without the change, the Operating System may be unable to determine the memory
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region and Root Decoder for an Endpoint and its corresponding HDM decoder.
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Region creation would fail. Platforms with a different interconnect architecture
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would fail to set up and use CXL.
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References
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----------
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.. [#cxl-spec-3.2] Compute Express Link Specification, Revision 3.2, Version 1.0,
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https://www.computeexpresslink.org/
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.. [#amd-ppr-58088] AMD Family 1Ah Models 00h–0Fh and Models 10h–1Fh,
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ACPI v6.5 Porting Guide, Publication # 58088,
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https://www.amd.com/en/search/documentation/hub.html
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.. [#prm-spec] Platform Runtime Mechanism, Version: 1.1,
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https://uefi.org/sites/default/files/resources/PRM_Platform_Runtime_Mechanism_1_1_release_candidate.pdf
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Detailed Description of the Change
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----------------------------------
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The following describes the necessary changes to the *CXL 3.2 specification*
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[#cxl-spec-3.2]_:
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Add the following reference to the table:
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Table 1-2. Reference Documents
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+----------------------------+-------------------+---------------------------+
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| Document | Chapter Reference | Document No./Location |
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+============================+===================+===========================+
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| Platform Runtime Mechanism | Chapter 8, 9 | https://www.uefi.org/acpi |
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| Version: 1.1 | | |
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+----------------------------+-------------------+---------------------------+
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Add the following paragraphs to the end of the section:
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**8.2.4.20 CXL HDM Decoder Capability Structure**
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"A device may use an HPA space that is not common to other components of the
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host domain. The platform is responsible for address translation when crossing
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HPA spaces. The Operating System must determine the interleaving configuration
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and perform address translation to the HPA ranges of the HDM decoders as needed.
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The translation mechanism is host-specific and implementation dependent.
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The platform indicates support of independent HPA spaces and the need for
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address translation by providing a Platform Runtime Mechanism (PRM) handler. The
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OS shall use that handler to perform the necessary translations from the DPA
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space to the HPA space. The handler is defined in Section 9.18.4 *PRM Handler
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for CXL DPA to System Physical Address Translation*."
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Add the following section and sub-section including tables:
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**9.18.4 PRM Handler for CXL DPA to System Physical Address Translation**
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"A platform may be configured to use 'Normalized addresses'. Host physical
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address (HPA) spaces are component-specific and differ from system physical
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addresses (SPAs). The endpoint has its own physical address space. All requests
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presented to the device already use Device Physical Addresses (DPAs). The CXL
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endpoint decoders have interleaving disabled (1-way interleaving) and the device
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does not perform HPA decoding to determine a DPA.
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The platform provides a PRM handler for CXL DPA to System Physical Address
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Translation. The PRM handler translates a Device Physical Address (DPA) to a
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System Physical Address (SPA) for a specified CXL endpoint. In the address space
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of the host, SPA and HPA are equivalent, and the OS shall use this handler to
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determine the HPA that corresponds to a device address, for example when
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configuring HDM decoders on platforms with Normalized addressing. The GUID and
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the parameter buffer format of the handler are specified in section 9.18.4.1. If
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the OS identifies the PRM handler, the platform supports Normalized addressing
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and the OS must perform DPA address translation as needed."
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**9.18.4.1 PRM Handler Invocation**
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"The OS calls the PRM handler for CXL DPA to System Physical Address Translation
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using the direct invocation mechanism. Details of calling a PRM handler are
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described in the Platform Runtime Mechanism (PRM) specification.
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The PRM handler is identified by the following GUID:
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EE41B397-25D4-452C-AD54-48C6E3480B94
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The caller allocates and prepares a Parameter Buffer, then passes the PRM
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handler GUID and a pointer to the Parameter Buffer to invoke the handler. The
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Parameter Buffer is described in Table 9-32."
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**Table 9-32. PRM Parameter Buffer used for CXL DPA to System Physical Address Translation**
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+-------------+-----------+------------------------------------------------------------------------+
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| Byte Offset | Length in | Description |
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| | Bytes | |
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+=============+===========+========================================================================+
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| 00h | 8 | **CXL Device Physical Address (DPA)**: CXL DPA (e.g., from |
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| | | CXL Component Event Log) |
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+-------------+-----------+------------------------------------------------------------------------+
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| 08h | 4 | **CXL Endpoint SBDF**: |
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| | | |
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| | | - Byte 3 - PCIe Segment |
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| | | - Byte 2 - Bus Number |
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| | | - Byte 1: |
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| | | - Device Number Bits[7:3] |
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| | | - Function Number Bits[2:0] |
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| | | - Byte 0 - RESERVED (MBZ) |
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+-------------+-----------+------------------------------------------------------------------------+
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| 0Ch | 8 | **Output Buffer**: Virtual Address Pointer to the buffer, |
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| | | as defined in Table 9-33. |
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+-------------+-----------+------------------------------------------------------------------------+
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**Table 9-33. PRM Output Buffer used for CXL DPA to System Physical Address Translation**
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+-------------+-----------+------------------------------------------------------------------------+
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| Byte Offset | Length in | Description |
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| | Bytes | |
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+=============+===========+========================================================================+
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| 00h | 8 | **System Physical Address (SPA)**: The SPA converted |
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| | | from the CXL DPA. |
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+-------------+-----------+------------------------------------------------------------------------+
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