817 lines
16 KiB
Devicetree
817 lines
16 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2026 Rockchip Electronics Co., Ltd.
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*/
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <arm64/rockchip/rockchip-pinconf.dtsi>
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&pinctrl {
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cam-clk0 {
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/omit-if-no-ref/
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cam_clk0: cam-clk0 {
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rockchip,pins =
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/* cam_clk0_out */
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<1 RK_PB5 1 &pcfg_pull_none>;
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};
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};
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cam-clk1 {
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/omit-if-no-ref/
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cam_clk1: cam-clk1 {
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rockchip,pins =
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/* cam_clk1_out */
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<1 RK_PB6 1 &pcfg_pull_none>;
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};
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};
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cam-spi {
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/omit-if-no-ref/
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cam_spi_bus4: cam-spi-bus4 {
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rockchip,pins =
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/* cam_spi_d0 */
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<0 RK_PB5 4 &pcfg_pull_up_drv_level_2>,
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/* cam_spi_d1 */
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<0 RK_PB2 4 &pcfg_pull_up_drv_level_2>,
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/* cam_spi_d2 */
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<0 RK_PB1 4 &pcfg_pull_up_drv_level_2>,
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/* cam_spi_d3 */
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<0 RK_PB0 4 &pcfg_pull_up_drv_level_2>;
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};
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/omit-if-no-ref/
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cam_spi_clk: cam-spi-clk {
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rockchip,pins =
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/* cam_spi_clk */
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<0 RK_PB4 4 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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cam_spi_cs0n: cam-spi-cs0n {
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rockchip,pins =
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/* cam_spi_cs0n */
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<0 RK_PB3 4 &pcfg_pull_none>;
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};
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};
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clk {
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/omit-if-no-ref/
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clk_32k: clk-32k {
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rockchip,pins =
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/* clk_32k */
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<0 RK_PA0 2 &pcfg_pull_none>;
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};
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};
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clk-24m {
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/omit-if-no-ref/
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clk_24m_out: clk-24m-out {
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rockchip,pins =
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/* clk_24m_out */
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<0 RK_PA0 3 &pcfg_pull_none>;
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};
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};
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cpu {
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/omit-if-no-ref/
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cpu: cpu {
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rockchip,pins =
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/* cpu_avs */
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<0 RK_PA1 2 &pcfg_pull_none>;
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};
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};
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emmc {
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/omit-if-no-ref/
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emmc_bus4: emmc-bus4 {
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rockchip,pins =
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/* emmc_d0 */
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<1 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
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/* emmc_d1 */
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<1 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
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/* emmc_d2 */
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<1 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
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/* emmc_d3 */
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<1 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
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};
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/omit-if-no-ref/
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emmc_clk: emmc-clk {
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rockchip,pins =
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/* emmc_clk */
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<1 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
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};
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/omit-if-no-ref/
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emmc_cmd: emmc-cmd {
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rockchip,pins =
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/* emmc_cmd */
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<1 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
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};
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};
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fspi {
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/omit-if-no-ref/
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fspi_bus4: fspi-bus4 {
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rockchip,pins =
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/* fspi_d0 */
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<1 RK_PA1 2 &pcfg_pull_none>,
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/* fspi_d1 */
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<1 RK_PA2 2 &pcfg_pull_none>,
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/* fspi_d2 */
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<1 RK_PA3 2 &pcfg_pull_none>,
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/* fspi_d3 */
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<1 RK_PA0 2 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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fspi_cs0: fspi-cs0 {
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rockchip,pins =
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/* fspi_cs0n */
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<1 RK_PA5 2 &pcfg_pull_up>;
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};
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/omit-if-no-ref/
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fspi_clk: fspi-clk {
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rockchip,pins =
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/* fspi_clk */
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<1 RK_PA4 2 &pcfg_pull_none>;
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};
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};
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i2c0 {
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/omit-if-no-ref/
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i2c0m0_xfer: i2c0m0-xfer {
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rockchip,pins =
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/* i2c0_scl_m0 */
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<0 RK_PA5 3 &pcfg_pull_none_smt>,
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/* i2c0_sda_m0 */
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<0 RK_PA6 3 &pcfg_pull_none_smt>;
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};
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/omit-if-no-ref/
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i2c0m1_xfer: i2c0m1-xfer {
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rockchip,pins =
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/* i2c0_scl_m1 */
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<1 RK_PB4 5 &pcfg_pull_none_smt>,
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/* i2c0_sda_m1 */
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<1 RK_PB3 5 &pcfg_pull_none_smt>;
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};
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/omit-if-no-ref/
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i2c0m2_xfer: i2c0m2-xfer {
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rockchip,pins =
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/* i2c0_scl_m2 */
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<1 RK_PB5 2 &pcfg_pull_none_smt>,
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/* i2c0_sda_m2 */
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<1 RK_PB6 2 &pcfg_pull_none_smt>;
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};
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};
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i2c1 {
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/omit-if-no-ref/
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i2c1m0_xfer: i2c1m0-xfer {
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rockchip,pins =
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/* i2c1_scl_m0 */
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<0 RK_PB0 1 &pcfg_pull_none_smt>,
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/* i2c1_sda_m0 */
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<0 RK_PB1 1 &pcfg_pull_none_smt>;
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};
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/omit-if-no-ref/
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i2c1m1_xfer: i2c1m1-xfer {
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rockchip,pins =
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/* i2c1_scl_m1 */
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<2 RK_PA4 4 &pcfg_pull_none_smt>,
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/* i2c1_sda_m1 */
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<2 RK_PA5 4 &pcfg_pull_none_smt>;
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};
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};
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i2c2 {
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/omit-if-no-ref/
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i2c2m0_xfer: i2c2m0-xfer {
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rockchip,pins =
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/* i2c2_scl_m0 */
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<0 RK_PB2 1 &pcfg_pull_none_smt>,
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/* i2c2_sda_m0 */
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<0 RK_PB3 1 &pcfg_pull_none_smt>;
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};
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/omit-if-no-ref/
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i2c2m1_xfer: i2c2m1-xfer {
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rockchip,pins =
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/* i2c2_scl_m1 */
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<2 RK_PA6 4 &pcfg_pull_none_smt>,
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/* i2c2_sda_m1 */
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<2 RK_PA7 4 &pcfg_pull_none_smt>;
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};
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};
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i2c3 {
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/omit-if-no-ref/
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i2c3m0_xfer: i2c3m0-xfer {
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rockchip,pins =
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/* i2c3_scl_m0 */
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<0 RK_PB4 1 &pcfg_pull_none_smt>,
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/* i2c3_sda_m0 */
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<0 RK_PB5 1 &pcfg_pull_none_smt>;
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};
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/omit-if-no-ref/
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i2c3m1_xfer: i2c3m1-xfer {
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rockchip,pins =
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/* i2c3_scl_m1 */
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<2 RK_PB3 4 &pcfg_pull_none_smt>,
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/* i2c3_sda_m1 */
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<2 RK_PB2 4 &pcfg_pull_none_smt>;
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};
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};
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i2c4 {
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/omit-if-no-ref/
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i2c4m0_xfer: i2c4m0-xfer {
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rockchip,pins =
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/* i2c4_scl_m0 */
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<2 RK_PB0 4 &pcfg_pull_none_smt>,
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/* i2c4_sda_m0 */
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<2 RK_PB1 4 &pcfg_pull_none_smt>;
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};
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/omit-if-no-ref/
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i2c4m1_xfer: i2c4m1-xfer {
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rockchip,pins =
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/* i2c4_scl_m1 */
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<1 RK_PB7 2 &pcfg_pull_none_smt>,
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/* i2c4_sda_m1 */
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<1 RK_PC0 2 &pcfg_pull_none_smt>;
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};
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};
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jtag {
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/omit-if-no-ref/
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jtagm0: jtagm0 {
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rockchip,pins =
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/* jtag_tck_m0 */
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<0 RK_PA5 5 &pcfg_pull_none>,
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/* jtag_tms_m0 */
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<0 RK_PA6 5 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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jtagm1: jtagm1 {
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rockchip,pins =
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/* jtag_tck_m1 */
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<0 RK_PB4 3 &pcfg_pull_none>,
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/* jtag_tms_m1 */
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<0 RK_PB5 3 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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jtagm2: jtagm2 {
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rockchip,pins =
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/* jtag_tck_m2 */
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<1 RK_PB4 3 &pcfg_pull_none>,
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/* jtag_tms_m2 */
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<1 RK_PB3 3 &pcfg_pull_none>;
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};
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};
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psram-spi {
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/omit-if-no-ref/
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psram_spi_bus4: psram-spi-bus4 {
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rockchip,pins =
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/* psram_spi_d0 */
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<0 RK_PA2 4 &pcfg_pull_none>,
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/* psram_spi_d1 */
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<0 RK_PA1 4 &pcfg_pull_none>,
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/* psram_spi_d2 */
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<0 RK_PA5 4 &pcfg_pull_none>,
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/* psram_spi_d3 */
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<0 RK_PA6 4 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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psram_spi_clk: psram-spi-clk {
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rockchip,pins =
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/* psram_spi_clk */
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<0 RK_PA0 4 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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psram_spi_cs0n: psram-spi-cs0n {
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rockchip,pins =
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/* psram_spi_cs0n */
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<0 RK_PA4 4 &pcfg_pull_none>;
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};
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};
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pwm0 {
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/omit-if-no-ref/
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pwm0m0_ch0: pwm0m0-ch0 {
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rockchip,pins =
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/* pwm0m0_ch0 */
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<0 RK_PA1 1 &pcfg_pull_none_drv_level_0>;
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};
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/omit-if-no-ref/
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pwm0m0_ch1: pwm0m0-ch1 {
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rockchip,pins =
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/* pwm0m0_ch1 */
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<0 RK_PA5 2 &pcfg_pull_none_drv_level_0>;
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};
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/omit-if-no-ref/
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pwm0m0_ch2: pwm0m0-ch2 {
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rockchip,pins =
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/* pwm0m0_ch2 */
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<0 RK_PA6 2 &pcfg_pull_none_drv_level_0>;
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};
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/omit-if-no-ref/
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pwm0m0_ch3: pwm0m0-ch3 {
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rockchip,pins =
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/* pwm0m0_ch3 */
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<0 RK_PA2 1 &pcfg_pull_none_drv_level_0>;
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};
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/omit-if-no-ref/
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pwm0m1_ch0: pwm0m1-ch0 {
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rockchip,pins =
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/* pwm0m1_ch0 */
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<2 RK_PA0 3 &pcfg_pull_none_drv_level_0>;
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};
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/omit-if-no-ref/
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pwm0m1_ch1: pwm0m1-ch1 {
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rockchip,pins =
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/* pwm0m1_ch1 */
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<2 RK_PA1 3 &pcfg_pull_none_drv_level_0>;
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};
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/omit-if-no-ref/
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pwm0m1_ch2: pwm0m1-ch2 {
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rockchip,pins =
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/* pwm0m1_ch2 */
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<2 RK_PA2 3 &pcfg_pull_none_drv_level_0>;
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};
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/omit-if-no-ref/
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pwm0m1_ch3: pwm0m1-ch3 {
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rockchip,pins =
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/* pwm0m1_ch3 */
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<2 RK_PB0 3 &pcfg_pull_none_drv_level_0>;
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};
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/omit-if-no-ref/
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pwm0m2_ch1: pwm0m2-ch1 {
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rockchip,pins =
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/* pwm0m2_ch1 */
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<1 RK_PB7 1 &pcfg_pull_none_drv_level_0>;
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};
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/omit-if-no-ref/
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pwm0m2_ch2: pwm0m2-ch2 {
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rockchip,pins =
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/* pwm0m2_ch2 */
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<1 RK_PC0 1 &pcfg_pull_none_drv_level_0>;
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};
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};
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pwm1 {
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/omit-if-no-ref/
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pwm1m0_ch0: pwm1m0-ch0 {
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rockchip,pins =
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/* pwm1m0_ch0 */
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<0 RK_PB0 3 &pcfg_pull_none_drv_level_0>;
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};
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/omit-if-no-ref/
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pwm1m0_ch1: pwm1m0-ch1 {
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rockchip,pins =
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/* pwm1m0_ch1 */
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<0 RK_PB1 3 &pcfg_pull_none_drv_level_0>;
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};
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/omit-if-no-ref/
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pwm1m0_ch2: pwm1m0-ch2 {
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rockchip,pins =
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/* pwm1m0_ch2 */
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<0 RK_PB2 3 &pcfg_pull_none_drv_level_0>;
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};
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/omit-if-no-ref/
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pwm1m0_ch3: pwm1m0-ch3 {
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rockchip,pins =
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/* pwm1m0_ch3 */
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<0 RK_PB3 3 &pcfg_pull_none_drv_level_0>;
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};
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/omit-if-no-ref/
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pwm1m1_ch0: pwm1m1-ch0 {
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rockchip,pins =
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/* pwm1m1_ch0 */
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<2 RK_PA3 3 &pcfg_pull_none_drv_level_0>;
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};
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/omit-if-no-ref/
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pwm1m1_ch1: pwm1m1-ch1 {
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rockchip,pins =
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/* pwm1m1_ch1 */
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<2 RK_PA4 3 &pcfg_pull_none_drv_level_0>;
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};
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/omit-if-no-ref/
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pwm1m1_ch2: pwm1m1-ch2 {
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rockchip,pins =
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/* pwm1m1_ch2 */
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<2 RK_PA5 3 &pcfg_pull_none_drv_level_0>;
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};
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/omit-if-no-ref/
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pwm1m1_ch3: pwm1m1-ch3 {
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rockchip,pins =
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/* pwm1m1_ch3 */
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<2 RK_PB1 3 &pcfg_pull_none_drv_level_0>;
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};
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};
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pwm2 {
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/omit-if-no-ref/
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pwm2m0_ch0: pwm2m0-ch0 {
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rockchip,pins =
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/* pwm2m0_ch0 */
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<1 RK_PB0 4 &pcfg_pull_none_drv_level_0>;
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};
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/omit-if-no-ref/
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pwm2m0_ch1: pwm2m0-ch1 {
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rockchip,pins =
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/* pwm2m0_ch1 */
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<1 RK_PA7 4 &pcfg_pull_none_drv_level_0>;
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};
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/omit-if-no-ref/
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pwm2m0_ch2: pwm2m0-ch2 {
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rockchip,pins =
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/* pwm2m0_ch2 */
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<1 RK_PB4 4 &pcfg_pull_none_drv_level_0>;
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};
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/omit-if-no-ref/
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pwm2m0_ch3: pwm2m0-ch3 {
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rockchip,pins =
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/* pwm2m0_ch3 */
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<1 RK_PB3 4 &pcfg_pull_none_drv_level_0>;
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};
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/omit-if-no-ref/
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pwm2m1_ch0: pwm2m1-ch0 {
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rockchip,pins =
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/* pwm2m1_ch0 */
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<2 RK_PA6 3 &pcfg_pull_none_drv_level_0>;
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};
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/omit-if-no-ref/
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pwm2m1_ch1: pwm2m1-ch1 {
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rockchip,pins =
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/* pwm2m1_ch1 */
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<2 RK_PA7 3 &pcfg_pull_none_drv_level_0>;
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};
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/omit-if-no-ref/
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pwm2m1_ch2: pwm2m1-ch2 {
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rockchip,pins =
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/* pwm2m1_ch2 */
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<2 RK_PB2 3 &pcfg_pull_none_drv_level_0>;
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};
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/omit-if-no-ref/
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pwm2m1_ch3: pwm2m1-ch3 {
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rockchip,pins =
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/* pwm2m1_ch3 */
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<2 RK_PB3 3 &pcfg_pull_none_drv_level_0>;
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};
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};
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pwr {
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/omit-if-no-ref/
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pwr: pwr {
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rockchip,pins =
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/* pwr_ctrl0 */
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<0 RK_PA3 1 &pcfg_pull_none>,
|
|
/* pwr_ctrl1 */
|
|
<0 RK_PA4 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
rtc_32k {
|
|
/omit-if-no-ref/
|
|
rtc_32k: rtc-32k {
|
|
rockchip,pins =
|
|
/* rtc_32k_out */
|
|
<0 RK_PA0 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
sai {
|
|
/omit-if-no-ref/
|
|
sai: sai {
|
|
rockchip,pins =
|
|
/* sai_lrck */
|
|
<2 RK_PB1 5 &pcfg_pull_none>,
|
|
/* sai_mclk */
|
|
<2 RK_PB0 5 &pcfg_pull_none>,
|
|
/* sai_sclk */
|
|
<2 RK_PA7 5 &pcfg_pull_none>,
|
|
/* sai_sdi */
|
|
<2 RK_PA6 5 &pcfg_pull_none>,
|
|
/* sai_sdo */
|
|
<2 RK_PB2 5 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
sdmmc0 {
|
|
/omit-if-no-ref/
|
|
sdmmc0_bus4: sdmmc0-bus4 {
|
|
rockchip,pins =
|
|
/* sdmmc0_d0 */
|
|
<1 RK_PB0 1 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc0_d1 */
|
|
<1 RK_PA7 1 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc0_d2 */
|
|
<1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc0_d3 */
|
|
<1 RK_PB3 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sdmmc0_clk: sdmmc0-clk {
|
|
rockchip,pins =
|
|
/* sdmmc0_clk */
|
|
<1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sdmmc0_cmd: sdmmc0-cmd {
|
|
rockchip,pins =
|
|
/* sdmmc0_cmd */
|
|
<1 RK_PB2 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sdmmc0_det: sdmmc0-det {
|
|
rockchip,pins =
|
|
/* sdmmc0_det */
|
|
<1 RK_PA6 1 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
sdmmc1 {
|
|
/omit-if-no-ref/
|
|
sdmmc1_bus4: sdmmc1-bus4 {
|
|
rockchip,pins =
|
|
/* sdmmc1_d0 */
|
|
<2 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc1_d1 */
|
|
<2 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc1_d2 */
|
|
<2 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
|
|
/* sdmmc1_d3 */
|
|
<2 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sdmmc1_clk: sdmmc1-clk {
|
|
rockchip,pins =
|
|
/* sdmmc1_clk */
|
|
<2 RK_PA2 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
sdmmc1_cmd: sdmmc1-cmd {
|
|
rockchip,pins =
|
|
/* sdmmc1_cmd */
|
|
<2 RK_PA3 1 &pcfg_pull_up_drv_level_2>;
|
|
};
|
|
};
|
|
|
|
spi0 {
|
|
/omit-if-no-ref/
|
|
spi0m0_clk: spi0m0-clk {
|
|
rockchip,pins =
|
|
/* spi0_clk_m0 */
|
|
<2 RK_PB0 2 &pcfg_pull_none>,
|
|
/* spi0_miso_m0 */
|
|
<2 RK_PB3 2 &pcfg_pull_none>,
|
|
/* spi0_mosi_m0 */
|
|
<2 RK_PB1 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
spi0m0_cs0: spi0m0-cs0 {
|
|
rockchip,pins =
|
|
/* spi0_cs0n_m0 */
|
|
<2 RK_PB2 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
spi0m0_cs1: spi0m0-cs1 {
|
|
rockchip,pins =
|
|
/* spi0_cs1n_m0 */
|
|
<2 RK_PA7 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
spi0m1_clk: spi0m1-clk {
|
|
rockchip,pins =
|
|
/* spi0_clk_m1 */
|
|
<2 RK_PA2 5 &pcfg_pull_none>,
|
|
/* spi0_miso_m1 */
|
|
<2 RK_PA4 5 &pcfg_pull_none>,
|
|
/* spi0_mosi_m1 */
|
|
<2 RK_PA1 5 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
spi0m1_cs0: spi0m1-cs0 {
|
|
rockchip,pins =
|
|
/* spi0_cs0n_m1 */
|
|
<2 RK_PA3 5 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
spi0m1_cs1: spi0m1-cs1 {
|
|
rockchip,pins =
|
|
/* spi0_cs1n_m1 */
|
|
<2 RK_PA0 5 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart0 {
|
|
/omit-if-no-ref/
|
|
uart0m0_xfer: uart0m0-xfer {
|
|
rockchip,pins =
|
|
/* uart0_rx_m0 */
|
|
<0 RK_PA6 1 &pcfg_pull_up>,
|
|
/* uart0_tx_m0 */
|
|
<0 RK_PA5 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart0m1_xfer: uart0m1-xfer {
|
|
rockchip,pins =
|
|
/* uart0_rx_m1 */
|
|
<0 RK_PB5 2 &pcfg_pull_up>,
|
|
/* uart0_tx_m1 */
|
|
<0 RK_PB4 2 &pcfg_pull_up>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart0m2_xfer: uart0m2-xfer {
|
|
rockchip,pins =
|
|
/* uart0_rx_m2 */
|
|
<1 RK_PB3 2 &pcfg_pull_up>,
|
|
/* uart0_tx_m2 */
|
|
<1 RK_PB4 2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
uart1 {
|
|
/omit-if-no-ref/
|
|
uart1m0_xfer: uart1m0-xfer {
|
|
rockchip,pins =
|
|
/* uart1_rx_m0 */
|
|
<0 RK_PB2 2 &pcfg_pull_up>,
|
|
/* uart1_tx_m0 */
|
|
<0 RK_PB3 2 &pcfg_pull_up>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart1m0_ctsn: uart1m0-ctsn {
|
|
rockchip,pins =
|
|
/* uart1m0_ctsn */
|
|
<0 RK_PB5 5 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
uart1m0_rtsn: uart1m0-rtsn {
|
|
rockchip,pins =
|
|
/* uart1m0_rtsn */
|
|
<0 RK_PB4 5 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart1m1_xfer: uart1m1-xfer {
|
|
rockchip,pins =
|
|
/* uart1_rx_m1 */
|
|
<1 RK_PA7 2 &pcfg_pull_up>,
|
|
/* uart1_tx_m1 */
|
|
<1 RK_PB0 2 &pcfg_pull_up>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart1m1_ctsn: uart1m1-ctsn {
|
|
rockchip,pins =
|
|
/* uart1m1_ctsn */
|
|
<1 RK_PB2 2 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
uart1m1_rtsn: uart1m1-rtsn {
|
|
rockchip,pins =
|
|
/* uart1m1_rtsn */
|
|
<1 RK_PB1 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart1m2_xfer: uart1m2-xfer {
|
|
rockchip,pins =
|
|
/* uart1_rx_m2 */
|
|
<2 RK_PA7 1 &pcfg_pull_up>,
|
|
/* uart1_tx_m2 */
|
|
<2 RK_PA6 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart1m2_ctsn: uart1m2-ctsn {
|
|
rockchip,pins =
|
|
/* uart1m2_ctsn */
|
|
<2 RK_PA5 2 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
uart1m2_rtsn: uart1m2-rtsn {
|
|
rockchip,pins =
|
|
/* uart1m2_rtsn */
|
|
<2 RK_PA4 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart1m3_xfer: uart1m3-xfer {
|
|
rockchip,pins =
|
|
/* uart1_rx_m3 */
|
|
<2 RK_PA3 2 &pcfg_pull_up>,
|
|
/* uart1_tx_m3 */
|
|
<2 RK_PA2 2 &pcfg_pull_up>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart1m3_ctsn: uart1m3-ctsn {
|
|
rockchip,pins =
|
|
/* uart1m3_ctsn */
|
|
<2 RK_PA1 2 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
uart1m3_rtsn: uart1m3-rtsn {
|
|
rockchip,pins =
|
|
/* uart1m3_rtsn */
|
|
<2 RK_PA0 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart2 {
|
|
/omit-if-no-ref/
|
|
uart2m0_xfer: uart2m0-xfer {
|
|
rockchip,pins =
|
|
/* uart2_rx_m0 */
|
|
<0 RK_PB1 2 &pcfg_pull_up>,
|
|
/* uart2_tx_m0 */
|
|
<0 RK_PB0 2 &pcfg_pull_up>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart2m0_ctsn: uart2m0-ctsn {
|
|
rockchip,pins =
|
|
/* uart2m0_ctsn */
|
|
<0 RK_PB3 5 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
uart2m0_rtsn: uart2m0-rtsn {
|
|
rockchip,pins =
|
|
/* uart2m0_rtsn */
|
|
<0 RK_PB2 5 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart2m1_xfer: uart2m1-xfer {
|
|
rockchip,pins =
|
|
/* uart2_rx_m1 */
|
|
<2 RK_PB1 1 &pcfg_pull_up>,
|
|
/* uart2_tx_m1 */
|
|
<2 RK_PB0 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart2m1_ctsn: uart2m1-ctsn {
|
|
rockchip,pins =
|
|
/* uart2m1_ctsn */
|
|
<2 RK_PB3 1 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
uart2m1_rtsn: uart2m1-rtsn {
|
|
rockchip,pins =
|
|
/* uart2m1_rtsn */
|
|
<2 RK_PB2 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart2m2_xfer: uart2m2-xfer {
|
|
rockchip,pins =
|
|
/* uart2_rx_m2 */
|
|
<1 RK_PB6 3 &pcfg_pull_up>,
|
|
/* uart2_tx_m2 */
|
|
<1 RK_PB5 3 &pcfg_pull_up>;
|
|
};
|
|
|
|
/omit-if-no-ref/
|
|
uart2m2_ctsn: uart2m2-ctsn {
|
|
rockchip,pins =
|
|
/* uart2m2_ctsn */
|
|
<1 RK_PC0 3 &pcfg_pull_none>;
|
|
};
|
|
/omit-if-no-ref/
|
|
uart2m2_rtsn: uart2m2-rtsn {
|
|
rockchip,pins =
|
|
/* uart2m2_rtsn */
|
|
<1 RK_PB7 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
};
|