767 lines
17 KiB
Devicetree
767 lines
17 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/amlogic,t7-pwrc.h>
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#include "amlogic-t7-reset.h"
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#include <dt-bindings/clock/amlogic,t7-scmi.h>
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#include <dt-bindings/clock/amlogic,t7-pll-clkc.h>
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#include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu100>;
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};
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core1 {
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cpu = <&cpu101>;
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};
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core2 {
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cpu = <&cpu102>;
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};
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core3 {
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cpu = <&cpu103>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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};
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cpu100: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x100>;
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enable-method = "psci";
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d-cache-line-size = <32>;
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d-cache-size = <0x8000>;
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d-cache-sets = <32>;
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i-cache-line-size = <32>;
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i-cache-size = <0x8000>;
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i-cache-sets = <32>;
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next-level-cache = <&l2_cache_l>;
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};
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cpu101: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x101>;
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enable-method = "psci";
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d-cache-line-size = <32>;
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d-cache-size = <0x8000>;
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d-cache-sets = <32>;
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i-cache-line-size = <32>;
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i-cache-size = <0x8000>;
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i-cache-sets = <32>;
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next-level-cache = <&l2_cache_l>;
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};
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cpu102: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x102>;
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enable-method = "psci";
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d-cache-line-size = <32>;
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d-cache-size = <0x8000>;
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d-cache-sets = <32>;
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i-cache-line-size = <32>;
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i-cache-size = <0x8000>;
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i-cache-sets = <32>;
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next-level-cache = <&l2_cache_l>;
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};
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cpu103: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x103>;
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enable-method = "psci";
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d-cache-line-size = <32>;
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d-cache-size = <0x8000>;
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d-cache-sets = <32>;
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i-cache-line-size = <32>;
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i-cache-size = <0x8000>;
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i-cache-sets = <32>;
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next-level-cache = <&l2_cache_l>;
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a73";
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reg = <0x0 0x0>;
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enable-method = "psci";
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d-cache-line-size = <64>;
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d-cache-size = <0x10000>;
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d-cache-sets = <64>;
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i-cache-line-size = <64>;
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i-cache-size = <0x10000>;
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i-cache-sets = <64>;
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next-level-cache = <&l2_cache_b>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a73";
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reg = <0x0 0x1>;
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enable-method = "psci";
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d-cache-line-size = <64>;
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d-cache-size = <0x10000>;
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d-cache-sets = <64>;
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i-cache-line-size = <64>;
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i-cache-size = <0x10000>;
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i-cache-sets = <64>;
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next-level-cache = <&l2_cache_b>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a73";
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reg = <0x0 0x2>;
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enable-method = "psci";
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d-cache-line-size = <64>;
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d-cache-size = <0x10000>;
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d-cache-sets = <64>;
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i-cache-line-size = <64>;
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i-cache-size = <0x10000>;
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i-cache-sets = <64>;
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next-level-cache = <&l2_cache_b>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a73";
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reg = <0x0 0x3>;
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enable-method = "psci";
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d-cache-line-size = <64>;
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d-cache-size = <0x10000>;
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d-cache-sets = <64>;
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i-cache-line-size = <64>;
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i-cache-size = <0x10000>;
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i-cache-sets = <64>;
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next-level-cache = <&l2_cache_b>;
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};
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l2_cache_l: l2-cache-cluster0 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x40000>; /* L2. 256 KB */
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cache-line-size = <64>;
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cache-sets = <512>;
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};
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l2_cache_b: l2-cache-cluster1 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x100000>; /* L2. 1 Mb */
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cache-line-size = <64>;
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cache-sets = <512>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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sm: secure-monitor {
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compatible = "amlogic,meson-gxbb-sm";
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pwrc: power-controller {
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compatible = "amlogic,t7-pwrc";
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#power-domain-cells = <1>;
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};
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};
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sram@f7042000 {
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compatible = "mmio-sram";
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reg = <0x0 0xf7042000 0x0 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0xf7042000 0x100>;
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scmi_shmem: sram@0 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0x100>;
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};
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};
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firmware {
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scmi: scmi {
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compatible = "arm,scmi-smc";
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arm,smc-id = <0x820000c1>;
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shmem = <&scmi_shmem>;
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic: interrupt-controller@fff01000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x0 0xfff01000 0 0x1000>,
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<0x0 0xfff02000 0 0x2000>,
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<0x0 0xfff04000 0 0x2000>,
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<0x0 0xfff06000 0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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apb4: bus@fe000000 {
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compatible = "simple-bus";
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reg = <0x0 0xfe000000 0x0 0x480000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
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clkc_periphs: clock-controller@0 {
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compatible = "amlogic,t7-peripherals-clkc";
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reg = <0x0 0x0 0x0 0x1c8>;
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#clock-cells = <1>;
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clocks = <&xtal>,
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<&scmi_clk CLKID_SYS_CLK>,
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<&scmi_clk CLKID_FIXED_PLL>,
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<&scmi_clk CLKID_FCLK_DIV2>,
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<&scmi_clk CLKID_FCLK_DIV2P5>,
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<&scmi_clk CLKID_FCLK_DIV3>,
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<&scmi_clk CLKID_FCLK_DIV4>,
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<&scmi_clk CLKID_FCLK_DIV5>,
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<&scmi_clk CLKID_FCLK_DIV7>,
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<&hifi CLKID_HIFI_PLL>,
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<&gp0 CLKID_GP0_PLL>,
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<&gp1 CLKID_GP1_PLL>,
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<&mpll CLKID_MPLL1>,
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<&mpll CLKID_MPLL2>,
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<&mpll CLKID_MPLL3>;
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clock-names = "xtal",
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"sys",
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"fix",
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"fdiv2",
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"fdiv2p5",
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"fdiv3",
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"fdiv4",
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"fdiv5",
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"fdiv7",
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"hifi",
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"gp0",
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"gp1",
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"mpll1",
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"mpll2",
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"mpll3";
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};
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reset: reset-controller@2000 {
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compatible = "amlogic,t7-reset";
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reg = <0x0 0x2000 0x0 0x98>;
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#reset-cells = <1>;
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};
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watchdog@2100 {
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compatible = "amlogic,t7-wdt";
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reg = <0x0 0x2100 0x0 0x10>;
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clocks = <&xtal>;
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};
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periphs_pinctrl: pinctrl@4000 {
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compatible = "amlogic,t7-periphs-pinctrl";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gpio: bank@4000 {
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reg = <0x0 0x4000 0x0 0x0064>,
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<0x0 0x40c0 0x0 0x0220>;
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reg-names = "mux", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&periphs_pinctrl 0 0 157>;
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};
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emmc_ctrl_pins: emmc-ctrl {
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mux-0 {
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groups = "emmc_cmd";
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function = "emmc";
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bias-pull-up;
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};
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mux-1 {
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groups = "emmc_clk";
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function = "emmc";
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bias-disable;
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};
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};
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emmc_data_4b_pins: emmc-data-4b {
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mux {
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groups = "emmc_nand_d0",
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"emmc_nand_d1",
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"emmc_nand_d2",
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"emmc_nand_d3";
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function = "emmc";
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bias-pull-up;
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};
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};
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emmc_data_8b_pins: emmc-data-8b {
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mux {
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groups = "emmc_nand_d0",
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"emmc_nand_d1",
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"emmc_nand_d2",
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"emmc_nand_d3",
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"emmc_nand_d4",
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"emmc_nand_d5",
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"emmc_nand_d6",
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"emmc_nand_d7";
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function = "emmc";
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bias-pull-up;
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};
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};
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emmc_ds_pins: emmc-ds {
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mux {
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groups = "emmc_nand_ds";
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function = "emmc";
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bias-pull-down;
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};
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};
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emmc_clk_gate_pins: emmc-clk-gate {
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mux {
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groups = "GPIOB_8";
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function = "gpio_periphs";
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bias-pull-down;
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};
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};
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i2c0_ao_d_pins: i2c0-ao-d {
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mux {
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groups = "i2c0_ao_sck_d",
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"i2c0_ao_sda_d";
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function = "i2c0_ao";
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bias-disable;
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drive-strength-microamp = <3000>;
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};
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};
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pwm_a_pins: pwm-a {
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mux {
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groups = "pwm_a";
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function = "pwm_a";
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bias-disable;
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};
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};
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pwm_ao_a_pins: pwm-ao-a {
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mux {
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groups = "pwm_ao_a";
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function = "pwm_ao_a";
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bias-disable;
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};
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};
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pwm_ao_b_pins: pwm-ao-b {
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mux {
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groups = "pwm_ao_b";
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function = "pwm_ao_b";
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bias-disable;
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};
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};
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pwm_ao_c_d_pins: pwm-ao-c-d {
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mux {
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groups = "pwm_ao_c_d";
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function = "pwm_ao_c";
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bias-disable;
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};
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};
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pwm_ao_c_e_pins: pwm-ao-c-e {
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mux {
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groups = "pwm_ao_c_e";
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function = "pwm_ao_c";
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bias-disable;
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};
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};
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pwm_ao_c_hiz_pins: pwm-ao-c-hiz {
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mux {
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groups = "pwm_ao_c_hiz";
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function = "pwm_ao_c_hiz";
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bias-disable;
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};
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};
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pwm_ao_d_pins: pwm-ao-d {
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mux {
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groups = "pwm_ao_d";
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function = "pwm_ao_d";
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bias-disable;
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};
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};
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pwm_ao_e_pins: pwm-ao-e {
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mux {
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groups = "pwm_ao_e";
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function = "pwm_ao_e";
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bias-disable;
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};
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};
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pwm_ao_f_pins: pwm-ao-f {
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mux {
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groups = "pwm_ao_f";
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function = "pwm_ao_f";
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bias-disable;
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};
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};
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pwm_ao_g_pins: pwm-ao-g {
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mux {
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groups = "pwm_ao_g";
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function = "pwm_ao_g";
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bias-disable;
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};
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};
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pwm_ao_g_hiz_pins: pwm-ao-g-hiz {
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mux {
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groups = "pwm_ao_g_hiz";
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function = "pwm_ao_g_hiz";
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bias-disable;
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};
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};
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pwm_ao_h_pins: pwm-ao-h {
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mux {
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groups = "pwm_ao_h";
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function = "pwm_ao_h";
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bias-disable;
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};
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};
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pwm_b_pins: pwm-b {
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mux {
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groups = "pwm_b";
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function = "pwm_b";
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bias-disable;
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};
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};
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pwm_c_pins: pwm-c {
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mux {
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groups = "pwm_c";
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function = "pwm_c";
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bias-disable;
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};
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};
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pwm_d_pins: pwm-d {
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mux {
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groups = "pwm_d";
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function = "pwm_d";
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bias-disable;
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};
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};
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pwm_e_pins: pwm-e {
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mux {
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groups = "pwm_e";
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function = "pwm_e";
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bias-disable;
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};
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};
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pwm_f_pins: pwm-f {
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mux {
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groups = "pwm_f";
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function = "pwm_f";
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bias-disable;
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};
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};
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pwm_vs_pins: pwm-vs {
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mux {
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groups = "pwm_vs";
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function = "pwm_vs";
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bias-disable;
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};
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};
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sdcard_pins: sdcard {
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mux {
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groups = "sdcard_d0",
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"sdcard_d1",
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"sdcard_d2",
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"sdcard_d3",
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"sdcard_clk",
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"sdcard_cmd";
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function = "sdcard";
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bias-pull-up;
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};
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};
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sdcard_clk_gate_pins: sdcard-clk-gate {
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mux {
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groups = "GPIOC_4";
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function = "gpio_periphs";
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
sdio_pins: sdio {
|
|
mux {
|
|
groups = "sdio_d0",
|
|
"sdio_d1",
|
|
"sdio_d2",
|
|
"sdio_d3",
|
|
"sdio_clk",
|
|
"sdio_cmd";
|
|
function = "sdio";
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
sdio_clk_gate_pins: sdio-clk-gate {
|
|
mux {
|
|
groups = "GPIOX_4";
|
|
function = "gpio_periphs";
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpio_intc: interrupt-controller@4080 {
|
|
compatible = "amlogic,t7-gpio-intc",
|
|
"amlogic,meson-gpio-intc";
|
|
reg = <0x0 0x4080 0x0 0x20>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
amlogic,channel-interrupts =
|
|
<10 11 12 13 14 15 16 17 18 19 20 21>;
|
|
};
|
|
|
|
uart_a: serial@78000 {
|
|
compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart";
|
|
reg = <0x0 0x78000 0x0 0x18>;
|
|
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gp0: clock-controller@8080 {
|
|
compatible = "amlogic,t7-gp0-pll";
|
|
reg = <0x0 0x8080 0x0 0x20>;
|
|
clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
|
|
clock-names = "in0";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
gp1: clock-controller@80c0 {
|
|
compatible = "amlogic,t7-gp1-pll";
|
|
reg = <0x0 0x80c0 0x0 0x14>;
|
|
clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
|
|
clock-names = "in0";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
hifi: clock-controller@8100 {
|
|
compatible = "amlogic,t7-hifi-pll";
|
|
reg = <0x0 0x8100 0x0 0x20>;
|
|
clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
|
|
clock-names = "in0";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
pcie: clock-controller@8140 {
|
|
compatible = "amlogic,t7-pcie-pll";
|
|
reg = <0x0 0x8140 0x0 0x1c>;
|
|
clocks = <&scmi_clk CLKID_PCIE_OSC>;
|
|
clock-names = "in0";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
mpll: clock-controller@8180 {
|
|
compatible = "amlogic,t7-mpll";
|
|
reg = <0x0 0x8180 0x0 0x28>;
|
|
clocks = <&scmi_clk CLKID_FIXED_PLL_DCO>;
|
|
clock-names = "in0";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
hdmi: clock-controller@81c0 {
|
|
compatible = "amlogic,t7-hdmi-pll";
|
|
reg = <0x0 0x81c0 0x0 0x20>;
|
|
clocks = <&scmi_clk CLKID_HDMI_PLL_OSC>;
|
|
clock-names = "in0";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
mclk: clock-controller@8300 {
|
|
compatible = "amlogic,t7-mclk-pll";
|
|
reg = <0x0 0x8300 0x0 0x18>;
|
|
clocks = <&scmi_clk CLKID_MCLK_PLL_OSC>,
|
|
<&xtal>,
|
|
<&scmi_clk CLKID_FCLK_50M>;
|
|
clock-names = "in0", "in1", "in2";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
sec_ao: ao-secure@10220 {
|
|
compatible = "amlogic,t7-ao-secure",
|
|
"amlogic,meson-gx-ao-secure",
|
|
"syscon";
|
|
reg = <0x0 0x10220 0x0 0x140>;
|
|
amlogic,has-chip-id;
|
|
};
|
|
|
|
pwm_ao_ef: pwm@30000 {
|
|
compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm";
|
|
reg = <0x0 0x30000 0x0 0x24>;
|
|
clocks = <&clkc_periphs CLKID_PWM_AO_E>,
|
|
<&clkc_periphs CLKID_PWM_AO_F>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm_ao_gh: pwm@32000 {
|
|
compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm";
|
|
reg = <0x0 0x32000 0x0 0x24>;
|
|
clocks = <&clkc_periphs CLKID_PWM_AO_G>,
|
|
<&clkc_periphs CLKID_PWM_AO_H>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm_ab: pwm@58000 {
|
|
compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm";
|
|
reg = <0x0 0x58000 0x0 0x24>;
|
|
clocks = <&clkc_periphs CLKID_PWM_A>,
|
|
<&clkc_periphs CLKID_PWM_B>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm_cd: pwm@5a000 {
|
|
compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm";
|
|
reg = <0x0 0x5a000 0x0 0x24>;
|
|
clocks = <&clkc_periphs CLKID_PWM_C>,
|
|
<&clkc_periphs CLKID_PWM_D>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm_ef: pwm@5c000 {
|
|
compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm";
|
|
reg = <0x0 0x5c000 0x0 0x24>;
|
|
clocks = <&clkc_periphs CLKID_PWM_E>,
|
|
<&clkc_periphs CLKID_PWM_F>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm_ao_ab: pwm@5e000 {
|
|
compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm";
|
|
reg = <0x0 0x5e000 0x0 0x24>;
|
|
clocks = <&clkc_periphs CLKID_PWM_AO_A>,
|
|
<&clkc_periphs CLKID_PWM_AO_B>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm_ao_cd: pwm@60000 {
|
|
compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm";
|
|
reg = <0x0 0x60000 0x0 0x24>;
|
|
clocks = <&clkc_periphs CLKID_PWM_AO_C>,
|
|
<&clkc_periphs CLKID_PWM_AO_D>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sd_emmc_a: mmc@88000 {
|
|
compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc";
|
|
reg = <0x0 0x88000 0x0 0x800>;
|
|
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_A>,
|
|
<&clkc_periphs CLKID_SD_EMMC_A>,
|
|
<&scmi_clk CLKID_FCLK_DIV2>;
|
|
clock-names = "core", "clkin0", "clkin1";
|
|
resets = <&reset RESET_SD_EMMC_A>;
|
|
assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_A_SEL>;
|
|
assigned-clock-parents = <&xtal>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sd_emmc_b: mmc@8a000 {
|
|
compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc";
|
|
reg = <0x0 0x8a000 0x0 0x800>;
|
|
interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_B>,
|
|
<&clkc_periphs CLKID_SD_EMMC_B>,
|
|
<&scmi_clk CLKID_FCLK_DIV2>;
|
|
clock-names = "core", "clkin0", "clkin1";
|
|
resets = <&reset RESET_SD_EMMC_B>;
|
|
assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_B_SEL>;
|
|
assigned-clock-parents = <&xtal>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sd_emmc_c: mmc@8c000 {
|
|
compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc";
|
|
reg = <0x0 0x8c000 0x0 0x800>;
|
|
interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_C>,
|
|
<&clkc_periphs CLKID_SD_EMMC_C>,
|
|
<&scmi_clk CLKID_FCLK_DIV2>;
|
|
clock-names = "core", "clkin0", "clkin1";
|
|
resets = <&reset RESET_SD_EMMC_C>;
|
|
assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_C_SEL>;
|
|
assigned-clock-parents = <&xtal>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
};
|
|
};
|