326 lines
8.0 KiB
Devicetree
326 lines
8.0 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
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/*
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* Copyright (c) 2019-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
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* D-82229 Seefeld, Germany.
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* Author: Alexander Stein
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*/
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#include <dt-bindings/firmware/imx/rsrc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/thermal/thermal.h>
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#include "imx8qm.dtsi"
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/ {
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model = "TQ-Systems i.MX8QM TQMa8QM";
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compatible = "tq,imx8qm-tqma8qm", "fsl,imx8qm";
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/* Due to missing workaround for ERR050104 */
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cpus {
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/delete-node/ cpu-map;
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/delete-node/ cpu@100;
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/delete-node/ cpu@101;
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};
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memory@80000000 {
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device_type = "memory";
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/*
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* DRAM base addr, size : 1024 MiB DRAM
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* should be corrected by bootloader
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*/
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reg = <0x00000000 0x80000000 0 0x40000000>;
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};
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reg_tqma8x_v3v3: regulator-tqma8x-v3v3 {
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compatible = "regulator-fixed";
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regulator-name = "V_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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/* SW7 controlled by SCU */
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reg_1v8_io1: regulator-v1v8-io1 {
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compatible = "regulator-fixed";
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regulator-name = "V_1V8_IO1";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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/* LDO4 controlled by SCU */
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reg_3v3_emmc: regulator-v3v3-emmc {
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compatible = "regulator-fixed";
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regulator-name = "V_3V3_EMMC";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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&acm {
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status = "okay";
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};
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&adc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_adc0>;
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vref-supply = <®_vref_v1v8>;
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status = "okay";
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};
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/* TQMa8QM only uses industrial grade, reduce trip points accordingly */
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&cpu_alert0 {
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temperature = <95000>;
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};
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&cpu_crit0 {
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temperature = <100000>;
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};
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&cpu_alert1 {
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temperature = <95000>;
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};
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&cpu_crit1 {
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temperature = <100000>;
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};
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&gpu_alert0 {
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temperature = <95000>;
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};
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&gpu_crit0 {
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temperature = <100000>;
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};
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&gpu_alert1 {
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temperature = <95000>;
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};
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&gpu_crit1 {
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temperature = <100000>;
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};
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&drc_alert0 {
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temperature = <95000>;
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};
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&drc_crit0 {
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temperature = <100000>;
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};
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/* end of temperature grade adjustments */
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&flexspi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexspi0>;
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status = "okay";
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flash0: flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <66000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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vcc-supply = <®_1v8_io1>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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};
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_lpi2c1>;
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pinctrl-1 = <&pinctrl_lpi2c1gpio>;
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scl-gpios = <&lsio_gpio0 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&lsio_gpio0 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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se97: temperature-sensor@1b {
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compatible = "nxp,se97b", "jedec,jc-42.4-temp";
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reg = <0x1b>;
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};
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pcf85063: rtc@51 {
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compatible = "nxp,pcf85063a";
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reg = <0x51>;
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quartz-load-femtofarads = <7000>;
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};
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at24c02: eeprom@53 {
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compatible = "nxp,se97b", "atmel,24c02";
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reg = <0x53>;
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pagesize = <16>;
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read-only;
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vcc-supply = <®_tqma8x_v3v3>;
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};
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m24c64: eeprom@57 {
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compatible = "atmel,24c64";
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reg = <0x57>;
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pagesize = <32>;
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vcc-supply = <®_tqma8x_v3v3>;
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};
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};
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&mu_m0 {
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status = "okay";
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};
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&mu1_m0 {
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status = "okay";
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};
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&mu2_m0 {
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status = "okay";
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};
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&thermal_zones {
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/delete-node/ cpu1-thermal;
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pmic0-thermal {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
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trips {
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pmic_alert0: trip0 {
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temperature = <110000>;
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hysteresis = <2000>;
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type = "passive";
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};
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pmic_crit0: trip1 {
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temperature = <125000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&pmic_alert0>;
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cooling-device =
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<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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bus-width = <8>;
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vmmc-supply = <®_3v3_emmc>;
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vqmmc-supply = <®_1v8_io1>;
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no-sd;
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no-sdio;
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non-removable;
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status = "okay";
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};
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&vpu {
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compatible = "nxp,imx8qm-vpu";
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status = "okay";
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};
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&vpu_core0 {
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memory-region = <&decoder_boot>, <&decoder_rpc>;
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status = "okay";
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};
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&vpu_core1 {
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memory-region = <&encoder1_boot>, <&encoder1_rpc>;
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status = "okay";
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};
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&vpu_core2 {
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memory-region = <&encoder2_boot>, <&encoder2_rpc>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_lpi2c1: lpi2c1grp {
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fsl,pins = <IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004d>,
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<IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004d>;
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};
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pinctrl_lpi2c1gpio: lpi2c1gpiogrp {
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fsl,pins = <IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 0x0600004d>,
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<IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0x0600004d>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>,
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<IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021>,
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<IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021>,
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<IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021>,
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<IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021>,
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<IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021>,
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<IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021>,
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<IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021>,
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<IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021>,
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<IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021>,
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<IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041>,
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<IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021>;
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};
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pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
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fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040>,
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<IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021>,
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<IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021>,
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<IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021>,
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<IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021>,
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<IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021>,
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<IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021>,
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<IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021>,
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<IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021>,
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<IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021>,
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<IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041>,
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<IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021>;
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};
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pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
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fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040>,
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<IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021>,
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<IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021>,
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<IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021>,
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<IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021>,
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<IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021>,
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<IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021>,
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<IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021>,
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<IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021>,
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<IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021>,
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<IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041>,
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<IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021>;
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};
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pinctrl_flexspi0: flexspi0grp {
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fsl,pins = <IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0000004d>,
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<IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0000004d>,
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<IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0000004d>,
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<IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0000004d>,
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<IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0000004d>,
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<IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0000004d>,
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<IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0000004d>,
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<IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0000004d>,
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<IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0000004d>,
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<IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0000004d>,
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<IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0000004d>,
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<IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0000004d>,
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<IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0000004d>,
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<IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0000004d>,
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<IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0000004d>,
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<IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0000004d>;
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};
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};
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