166 lines
3.3 KiB
Devicetree
166 lines
3.3 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the RZ/G3L SMARC EVK board
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*
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* Copyright (C) 2026 Renesas Electronics Corp.
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*/
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/dts-v1/;
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/* Switch selection settings */
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#define RZ_BOOT_MODE3 1
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#define SW_SD2_EN 0
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#define SW_DPI_EN 0
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#define SW_GPIO4 1
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#define SW_I3C_EN 0
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#define PMOD_GPIO4 0
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#define PMOD_GPIO6 0
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#define PMOD_GPIO7 0
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#define KEY_1_GPIO RZG3L_GPIO(J, 3)
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#define KEY_2_GPIO RZG3L_GPIO(6, 4)
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#define KEY_3_GPIO RZG3L_GPIO(6, 5)
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h>
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#include "r9a08g046l48.dtsi"
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#include "rzg3l-smarc-som.dtsi"
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#include "renesas-smarc2.dtsi"
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/ {
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model = "Renesas SMARC EVK version 2 based on r9a08g046l48";
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compatible = "renesas,smarc2-evk", "renesas,rzg3l-smarcm",
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"renesas,r9a08g046l48", "renesas,r9a08g046";
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aliases {
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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serial3 = &scif0;
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};
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#if !SW_SD2_EN && !SW_I3C_EN
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snd_rzg3l: sound {
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compatible = "simple-audio-card";
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simple-audio-card,name = "snd_rzg3l";
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#address-cells = <1>;
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#size-cells = <0>;
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ssi_link_play: simple-audio-card,dai-link@0 {
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reg = <0>;
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format = "i2s";
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bitclock-master = <&cpu_dai>;
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frame-master = <&cpu_dai>;
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mclk-fs = <256>;
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cpu_dai: cpu {
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sound-dai = <&ssi0>;
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};
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codec_dai: codec {
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sound-dai = <&da7212>;
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clocks = <&versa3 1>;
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};
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};
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};
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#endif
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};
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&i2c2 {
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pinctrl-0 = <&i2c2_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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#if !SW_I3C_EN
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&i2c3 {
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pinctrl-0 = <&i2c3_pins>;
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pinctrl-names = "default";
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status = "okay";
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da7212: codec@1a {
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compatible = "dlg,da7212";
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reg = <0x1a>;
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clocks = <&versa3 1>;
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clock-names = "mclk";
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#sound-dai-cells = <0>;
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dlg,micbias1-lvl = <2500>;
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dlg,micbias2-lvl = <2500>;
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dlg,dmic-data-sel = "lrise_rfall";
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dlg,dmic-samplephase = "between_clkedge";
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dlg,dmic-clkrate = <3000000>;
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VDDA-supply = <®_1p8v>;
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VDDSP-supply = <®_3p3v>;
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VDDMIC-supply = <®_3p3v>;
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VDDIO-supply = <®_1p8v>;
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};
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};
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#endif
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&keys {
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#if !RZ_BOOT_MODE3 || !SW_GPIO4 || PMOD_GPIO4
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/delete-node/ key-1;
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#endif
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#if SW_DPI_EN || PMOD_GPIO6
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/delete-node/ key-2;
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#endif
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#if SW_DPI_EN || PMOD_GPIO7
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/delete-node/ key-3;
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#endif
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};
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&pinctrl {
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audio_clk_pins: audio-clock {
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pinmux = <RZG3L_PORT_PINMUX(H, 4, 6)>, /* AUDIO_CLK_B */
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<RZG3L_PORT_PINMUX(H, 5, 6)>; /* AUDIO_CLK_C */
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};
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i2c2_pins: i2c2 {
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pinmux = <RZG3L_PORT_PINMUX(A, 4, 4)>, /* RIIC2_SCL */
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<RZG3L_PORT_PINMUX(A, 5, 4)>; /* RIIC2_SDA */
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};
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i2c3_pins: i2c3 {
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pinmux = <RZG3L_PORT_PINMUX(2, 0, 4)>, /* RIIC3_SCL */
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<RZG3L_PORT_PINMUX(2, 1, 4)>; /* RIIC3_SDA */
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};
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scif0_pins: scif0 {
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pins = "SCIF0_TXD", "SCIF0_RXD";
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power-source = <1800>;
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};
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ssi0_pins: ssi0 {
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pinmux = <RZG3L_PORT_PINMUX(H, 0, 9)>, /* SSIF0_RXD */
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<RZG3L_PORT_PINMUX(H, 1, 9)>, /* SSIF0_BCK */
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<RZG3L_PORT_PINMUX(H, 2, 9)>, /* SSIF0_RCK */
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<RZG3L_PORT_PINMUX(H, 3, 9)>; /* SSIF0_TXD */
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};
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};
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&scif0 {
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pinctrl-0 = <&scif0_pins>;
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pinctrl-names = "default";
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};
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#if !SW_SD2_EN
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&ssi0 {
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clocks = <&cpg CPG_MOD R9A08G046_SSI0_PCLK2>,
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<&cpg CPG_MOD R9A08G046_SSI0_PCLK_SFR>,
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<&versa3 2>, <&versa3 3>;
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pinctrl-0 = <&audio_clk_pins>, <&ssi0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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#endif
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