169 lines
5.6 KiB
Plaintext
169 lines
5.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/**
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* DT overlay for enabling ICSSG0 dual EMAC on AM642 EVM
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*
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* AM642 EVM Product link: https://www.ti.com/tool/TMDS64EVM
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* DP83TG720 daughter card link: https://www.ti.com/tool/DP83TG720-IND-SPE-EVM
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*
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* Copyright (C) 2020-2026 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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#include "k3-pinctrl.h"
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&{/} {
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icssg0_eth: icssg0-eth {
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compatible = "ti,am642-icssg-prueth";
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pinctrl-names = "default";
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pinctrl-0 = <&pru_icssg0_rgmii1_pins_default>, <&pru_icssg0_rgmii2_pins_default>;
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sram = <&oc_sram>;
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dmas = <&main_pktdma 0xc100 15>, /* egress slice 0 */
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<&main_pktdma 0xc101 15>, /* egress slice 0 */
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<&main_pktdma 0xc102 15>, /* egress slice 0 */
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<&main_pktdma 0xc103 15>, /* egress slice 0 */
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<&main_pktdma 0xc104 15>, /* egress slice 1 */
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<&main_pktdma 0xc105 15>, /* egress slice 1 */
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<&main_pktdma 0xc106 15>, /* egress slice 1 */
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<&main_pktdma 0xc107 15>, /* egress slice 1 */
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<&main_pktdma 0x4100 15>, /* ingress slice 0 */
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<&main_pktdma 0x4101 15>; /* ingress slice 1 */
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dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
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"tx1-0", "tx1-1", "tx1-2", "tx1-3",
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"rx0", "rx1";
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interrupt-parent = <&icssg0_intc>;
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interrupts = <24 0 2>, <25 1 3>;
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interrupt-names = "tx_ts0", "tx_ts1";
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ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>;
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firmware-name = "ti-pruss/am64x-sr2-pru0-prueth-fw.elf",
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"ti-pruss/am64x-sr2-rtu0-prueth-fw.elf",
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"ti-pruss/am64x-sr2-txpru0-prueth-fw.elf",
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"ti-pruss/am64x-sr2-pru1-prueth-fw.elf",
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"ti-pruss/am64x-sr2-rtu1-prueth-fw.elf",
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"ti-pruss/am64x-sr2-txpru1-prueth-fw.elf";
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ti,pruss-gp-mux-sel = <2>, /* MII mode */
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<2>,
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<2>,
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<2>, /* MII mode */
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<2>,
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<2>;
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ti,mii-g-rt = <&icssg0_mii_g_rt>;
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ti,mii-rt = <&icssg0_mii_rt>;
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ti,iep = <&icssg0_iep0>, <&icssg0_iep1>;
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ti,pa-stats = <&icssg0_pa_stats>;
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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icssg0_emac0: port@0 {
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reg = <0>;
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phy-handle = <&icssg0_phy00>;
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phy-mode = "rgmii-id";
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ti,syscon-rgmii-delay = <&main_conf 0x4100>;
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/* Filled in by bootloader */
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local-mac-address = [00 00 00 00 00 00];
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};
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icssg0_emac1: port@1 {
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reg = <1>;
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phy-handle = <&icssg0_phy01>;
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phy-mode = "rgmii-id";
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ti,syscon-rgmii-delay = <&main_conf 0x4104>;
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/* Filled in by bootloader */
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local-mac-address = [00 00 00 00 00 00];
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};
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};
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};
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};
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&main_pmx0 {
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pru_icssg0_mdio_pins_default: pru-icssg0-mdio-pins {
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pinctrl-single,pins = <
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/* (P3) PRG0_MDIO0_MDC */
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AM64X_IOPAD(0x0204, PIN_OUTPUT, 0)
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/* (P2) PRG0_MDIO0_MDIO */
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AM64X_IOPAD(0x0200, PIN_INPUT, 0)
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/* (P16) GPIO0_32 - GPMC0_ADVn_ALE - GPIO_ETH0/1_RESETn# */
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AM64X_IOPAD(0x0084, PIN_OUTPUT, 7)
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>;
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};
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pru_icssg0_rgmii1_pins_default: pru-icssg0-rgmii1-pins {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0160, PIN_INPUT, 2) /* (Y1) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */
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AM64X_IOPAD(0x0164, PIN_INPUT, 2) /* (R4) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */
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AM64X_IOPAD(0x0168, PIN_INPUT, 2) /* (U2) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */
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AM64X_IOPAD(0x016c, PIN_INPUT, 2) /* (V2) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */
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AM64X_IOPAD(0x0178, PIN_INPUT, 2) /* (T3) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */
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AM64X_IOPAD(0x0170, PIN_INPUT, 2) /* (AA2) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */
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AM64X_IOPAD(0x018c, PIN_OUTPUT, 2) /* (Y3) PRG0_PRU0_GPO11.PRG0_RGMII1_TD0 */
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AM64X_IOPAD(0x0190, PIN_OUTPUT, 2) /* (AA3) PRG0_PRU0_GPO12.PRG0_RGMII1_TD1 */
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AM64X_IOPAD(0x0194, PIN_OUTPUT, 2) /* (R6) PRG0_PRU0_GPO13.PRG0_RGMII1_TD2 */
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AM64X_IOPAD(0x0198, PIN_OUTPUT, 2) /* (V4) PRG0_PRU0_GPO14.PRG0_RGMII1_TD3 */
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AM64X_IOPAD(0x01a0, PIN_OUTPUT, 2) /* (U4) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */
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AM64X_IOPAD(0x019c, PIN_OUTPUT, 2) /* (T5) PRG0_PRU0_GPO15.PRG0_RGMII1_TX_CTL */
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>;
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};
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pru_icssg0_rgmii2_pins_default: pru-icssg0-rgmii2-pins {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x01b0, PIN_INPUT, 2) /* (Y2) PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */
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AM64X_IOPAD(0x01b4, PIN_INPUT, 2) /* (W2) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */
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AM64X_IOPAD(0x01b8, PIN_INPUT, 2) /* (V3) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */
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AM64X_IOPAD(0x01bc, PIN_INPUT, 2) /* (T4) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */
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AM64X_IOPAD(0x01c8, PIN_INPUT, 2) /* (R5) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */
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AM64X_IOPAD(0x01c0, PIN_INPUT, 2) /* (W3) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */
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AM64X_IOPAD(0x01dc, PIN_OUTPUT, 2) /* (W4) PRG0_PRU1_GPO11.PRG0_RGMII2_TD0 */
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AM64X_IOPAD(0x01e0, PIN_OUTPUT, 2) /* (Y4) PRG0_PRU1_GPO12.PRG0_RGMII2_TD1 */
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AM64X_IOPAD(0x01e4, PIN_OUTPUT, 2) /* (T6) PRG0_PRU1_GPO13.PRG0_RGMII2_TD2 */
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AM64X_IOPAD(0x01e8, PIN_OUTPUT, 2) /* (U6) PRG0_PRU1_GPO14.PRG0_RGMII2_TD3 */
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AM64X_IOPAD(0x01f0, PIN_OUTPUT, 2) /* (AA4) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */
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AM64X_IOPAD(0x01ec, PIN_OUTPUT, 2) /* (U5) PRG0_PRU1_GPO15.PRG0_RGMII2_TX_CTL */
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>;
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};
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icssg0_iep0_pins_default: icssg0-iep0-pins {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x01ac, PIN_OUTPUT, 2) /* (W1) PRG0_PRU0_GPO19.PRG0_IEP0_EDC_SYNC_OUT0 */
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>;
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};
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};
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&icssg0_mdio {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pru_icssg0_mdio_pins_default>;
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#address-cells = <1>;
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#size-cells = <0>;
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icssg0_phy00: ethernet-phy@0 {
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reg = <0x0>;
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};
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icssg0_phy01: ethernet-phy@a {
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reg = <0xa>;
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};
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};
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&icssg0_iep0 {
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pinctrl-names = "default";
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pinctrl-0 = <&icssg0_iep0_pins_default>;
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};
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&main_gpio0 {
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phy-line-hog {
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gpio-hog;
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gpios = <32 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "phy-hog-line";
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};
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};
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