285 lines
6.9 KiB
ArmAsm
285 lines
6.9 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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#include <linux/linkage.h>
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#include <asm/asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/bitsperlong.h>
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#include <asm/frame.h>
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#include <asm/nospec-branch.h>
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#include "kvm-asm-offsets.h"
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#include "vmenter.h"
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#define SVM_vmcb01_pa (SVM_vmcb01 + KVM_VMCB_pa)
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.section .noinstr.text, "ax"
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.macro RESTORE_GUEST_SPEC_CTRL
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/* No need to do anything if SPEC_CTRL is unset or V_SPEC_CTRL is set */
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ALTERNATIVE_2 "", \
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"jmp 800f", X86_FEATURE_MSR_SPEC_CTRL, \
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"", X86_FEATURE_V_SPEC_CTRL
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.endm
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.macro RESTORE_HOST_SPEC_CTRL
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/* No need to do anything if SPEC_CTRL is unset or V_SPEC_CTRL is set */
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ALTERNATIVE_2 "", \
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"jmp 900f", X86_FEATURE_MSR_SPEC_CTRL, \
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"", X86_FEATURE_V_SPEC_CTRL
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.endm
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#define SVM_CLEAR_CPU_BUFFERS \
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ALTERNATIVE "", __CLEAR_CPU_BUFFERS, X86_FEATURE_CLEAR_CPU_BUF_VM
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/**
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* __svm_vcpu_run - Run a vCPU via a transition to SVM guest mode
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* @svm: struct vcpu_svm *
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* @enter_flags: u32
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*/
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SYM_FUNC_START(__svm_vcpu_run)
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push %_ASM_BP
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mov %_ASM_SP, %_ASM_BP
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#ifdef CONFIG_X86_64
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push %r15
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push %r14
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push %r13
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push %r12
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#else
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push %edi
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push %esi
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#endif
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push %_ASM_BX
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/*
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* Save variables needed after vmexit on the stack, in inverse
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* order compared to when they are needed.
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*/
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/* Accessed directly from the stack in RESTORE_HOST_SPEC_CTRL. */
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push %_ASM_ARG2
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/* Needed to restore access to percpu variables. */
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__ASM_SIZE(push) PER_CPU_VAR(svm_data + SD_save_area_pa)
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/* Finally save @svm. */
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push %_ASM_ARG1
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.ifnc _ASM_ARG1, _ASM_DI
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/*
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* Stash @svm in RDI early. On 32-bit, arguments are in RAX, RCX
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* and RDX which are clobbered by RESTORE_GUEST_SPEC_CTRL.
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*/
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mov %_ASM_ARG1, %_ASM_DI
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.endif
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/* Clobbers RAX, RCX, RDX (and ESI on 32-bit), consumes RDI (@svm). */
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RESTORE_GUEST_SPEC_CTRL
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801:
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/*
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* Use a single vmcb (vmcb01 because it's always valid) for
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* context switching guest state via VMLOAD/VMSAVE, that way
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* the state doesn't need to be copied between vmcb01 and
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* vmcb02 when switching vmcbs for nested virtualization.
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*/
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mov SVM_vmcb01_pa(%_ASM_DI), %_ASM_AX
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1: vmload %_ASM_AX
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2:
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/* Get svm->current_vmcb->pa into RAX. */
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mov SVM_current_vmcb(%_ASM_DI), %_ASM_AX
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mov KVM_VMCB_pa(%_ASM_AX), %_ASM_AX
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/*
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* Load guest registers. Intentionally omit %_ASM_AX and %_ASM_SP as
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* context switched by hardware
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*/
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LOAD_REGS %_ASM_DI, SVM_vcpu_arch_regs, \
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%_ASM_CX, %_ASM_DX, %_ASM_BX, %_ASM_BP, %_ASM_SI
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#ifdef CONFIG_X86_64
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LOAD_REGS %_ASM_DI, SVM_vcpu_arch_regs, \
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%r8, %r9, %r10, %r11, %r12, %r13, %r14, %r15
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#endif
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LOAD_REGS %_ASM_DI, SVM_vcpu_arch_regs, %_ASM_DI
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/* Clobbers EFLAGS.ZF */
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SVM_CLEAR_CPU_BUFFERS
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/* Enter guest mode */
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3: vmrun %_ASM_AX
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4:
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/* Pop @svm to RAX while it's the only available register. */
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pop %_ASM_AX
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/*
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* Save all guest registers. Intentionally omit %_ASM_AX and %_ASM_SP as
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* context switched by hardware
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*/
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STORE_REGS %_ASM_AX, SVM_vcpu_arch_regs, \
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%_ASM_CX, %_ASM_DX, %_ASM_BX, %_ASM_BP, %_ASM_SI, %_ASM_DI
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#ifdef CONFIG_X86_64
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STORE_REGS %_ASM_AX, SVM_vcpu_arch_regs, \
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%r8, %r9, %r10, %r11, %r12, %r13, %r14, %r15
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#endif
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/* @svm can stay in RDI from now on. */
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mov %_ASM_AX, %_ASM_DI
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mov SVM_vmcb01_pa(%_ASM_DI), %_ASM_AX
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5: vmsave %_ASM_AX
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6:
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/* Restores GSBASE among other things, allowing access to percpu data. */
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pop %_ASM_AX
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7: vmload %_ASM_AX
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8:
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/* IMPORTANT: Stuff the RSB immediately after VM-Exit, before RET! */
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FILL_RETURN_BUFFER %_ASM_AX, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_VMEXIT
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/*
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* Clobbers RAX, RCX, RDX (and ESI, EDI on 32-bit), consumes RDI (@svm)
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* and RSP (pointer to @spec_ctrl_intercepted).
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*/
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RESTORE_HOST_SPEC_CTRL
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901:
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/*
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* Mitigate RETBleed for AMD/Hygon Zen uarch. RET should be
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* untrained as soon as we exit the VM and are back to the
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* kernel. This should be done before re-enabling interrupts
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* because interrupt handlers won't sanitize 'ret' if the return is
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* from the kernel.
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*/
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UNTRAIN_RET_VM
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/*
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* Clear all general purpose registers except RSP and RAX to prevent
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* speculative use of the guest's values, even those that are reloaded
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* via the stack. In theory, an L1 cache miss when restoring registers
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* could lead to speculative execution with the guest's values.
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* Zeroing XORs are dirt cheap, i.e. the extra paranoia is essentially
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* free. RSP and RAX are exempt as they are restored by hardware
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* during VM-Exit.
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*/
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CLEAR_REGS %ecx, %edx, %ebx, %ebp, %esi, %edi
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#ifdef CONFIG_X86_64
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CLEAR_REGS %r8d, %r9d, %r10d, %r11d, %r12d, %r13d, %r14d, %r15d
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#endif
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/* "Pop" @enter_flags. */
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pop %_ASM_BX
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pop %_ASM_BX
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#ifdef CONFIG_X86_64
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pop %r12
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pop %r13
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pop %r14
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pop %r15
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#else
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pop %esi
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pop %edi
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#endif
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pop %_ASM_BP
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RET
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800:
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RESTORE_GUEST_SPEC_CTRL_BODY SVM_spec_ctrl(%_ASM_DI), 801b
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jmp 801b
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900:
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RESTORE_HOST_SPEC_CTRL_BODY SVM_spec_ctrl(%_ASM_DI), (%_ASM_SP), 901b
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jmp 901b
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10: cmpb $0, _ASM_RIP(virt_rebooting)
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jne 2b
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ud2
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30: cmpb $0, _ASM_RIP(virt_rebooting)
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jne 4b
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ud2
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50: cmpb $0, _ASM_RIP(virt_rebooting)
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jne 6b
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ud2
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70: cmpb $0, _ASM_RIP(virt_rebooting)
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jne 8b
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ud2
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_ASM_EXTABLE(1b, 10b)
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_ASM_EXTABLE(3b, 30b)
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_ASM_EXTABLE(5b, 50b)
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_ASM_EXTABLE(7b, 70b)
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SYM_FUNC_END(__svm_vcpu_run)
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#ifdef CONFIG_KVM_AMD_SEV
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#define SEV_ES_GPRS_BASE 0x300
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/**
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* __svm_sev_es_vcpu_run - Run a SEV-ES vCPU via a transition to SVM guest mode
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* @svm: struct vcpu_svm *
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* @enter_flags: u32
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*/
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SYM_FUNC_START(__svm_sev_es_vcpu_run)
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FRAME_BEGIN
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/*
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* Save non-volatile (callee-saved) registers to the host save area.
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* Except for RAX and RSP, all GPRs are restored on #VMEXIT, but not
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* saved on VMRUN.
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*/
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STORE_REGS %rdx, SEV_ES_GPRS_BASE, %rbp, %r15, %r14, %r13, %r12, %rbx
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/*
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* Save volatile registers that hold arguments that are needed after
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* #VMEXIT (RDI=@svm and RSI=@enter_flags).
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*/
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STORE_REGS %rdx, SEV_ES_GPRS_BASE, %rdi, %rsi
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/* Clobbers RAX, RCX, and RDX (@hostsa), consumes RDI (@svm). */
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RESTORE_GUEST_SPEC_CTRL
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801:
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/* Get svm->current_vmcb->pa into RAX. */
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mov SVM_current_vmcb(%rdi), %rax
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mov KVM_VMCB_pa(%rax), %rax
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/* Clobbers EFLAGS.ZF */
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SVM_CLEAR_CPU_BUFFERS
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/* Enter guest mode */
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1: vmrun %rax
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2:
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/* IMPORTANT: Stuff the RSB immediately after VM-Exit, before RET! */
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FILL_RETURN_BUFFER %rax, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_VMEXIT
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/* Clobbers RAX, RCX, RDX, consumes RDI (@svm) and RSI (@enter_flags). */
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RESTORE_HOST_SPEC_CTRL
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901:
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/*
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* Mitigate RETBleed for AMD/Hygon Zen uarch. RET should be
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* untrained as soon as we exit the VM and are back to the
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* kernel. This should be done before re-enabling interrupts
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* because interrupt handlers won't sanitize RET if the return is
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* from the kernel.
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*/
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UNTRAIN_RET_VM
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FRAME_END
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RET
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800:
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RESTORE_GUEST_SPEC_CTRL_BODY SVM_spec_ctrl(%_ASM_DI), 801b
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jmp 801b
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900:
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RESTORE_HOST_SPEC_CTRL_BODY SVM_spec_ctrl(%_ASM_DI), %esi, 901b
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jmp 901b
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3: cmpb $0, virt_rebooting(%rip)
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jne 2b
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ud2
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_ASM_EXTABLE(1b, 3b)
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SYM_FUNC_END(__svm_sev_es_vcpu_run)
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#endif /* CONFIG_KVM_AMD_SEV */
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