287 lines
8.1 KiB
YAML
287 lines
8.1 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/qcom,milos-mdss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Milos Display MDSS
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maintainers:
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- Luca Weiss <luca.weiss@fairphone.com>
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description:
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Milos MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
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DPU display controller, DSI and DP interfaces etc.
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$ref: /schemas/display/msm/mdss-common.yaml#
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properties:
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compatible:
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const: qcom,milos-mdss
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clocks:
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items:
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- description: Display AHB
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- description: Display hf AXI
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- description: Display core
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iommus:
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maxItems: 1
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interconnects:
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items:
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- description: Interconnect path from mdp0 port to the data bus
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- description: Interconnect path from CPU to the reg bus
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interconnect-names:
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items:
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- const: mdp0-mem
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- const: cpu-cfg
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patternProperties:
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"^display-controller@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: qcom,milos-dpu
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"^displayport-controller@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: qcom,milos-dp
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"^dsi@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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contains:
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const: qcom,milos-dsi-ctrl
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"^phy@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: qcom,milos-dsi-phy-4nm
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required:
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- compatible
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
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#include <dt-bindings/clock/qcom,milos-dispcc.h>
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#include <dt-bindings/clock/qcom,milos-gcc.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,milos-rpmh.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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display-subsystem@ae00000 {
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compatible = "qcom,milos-mdss";
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reg = <0x0ae00000 0x1000>;
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reg-names = "mdss";
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&gcc GCC_DISP_HF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>;
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resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
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interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&cnoc_main SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
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interconnect-names = "mdp0-mem",
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"cpu-cfg";
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power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
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iommus = <&apps_smmu 0x1c00 0x2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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display-controller@ae01000 {
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compatible = "qcom,milos-dpu";
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reg = <0x0ae01000 0x8f000>,
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<0x0aeb0000 0x3000>;
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reg-names = "mdp",
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"vbif";
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interrupts-extended = <&mdss 0>;
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clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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clock-names = "nrt_bus",
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"iface",
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"lut",
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"core",
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"vsync";
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assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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assigned-clock-rates = <19200000>;
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operating-points-v2 = <&mdp_opp_table>;
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power-domains = <&rpmhpd RPMHPD_CX>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpu_intf1_out: endpoint {
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remote-endpoint = <&mdss_dsi0_in>;
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};
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};
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};
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mdp_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-342000000 {
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opp-hz = /bits/ 64 <342000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-402000000 {
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opp-hz = /bits/ 64 <402000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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opp-535000000 {
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opp-hz = /bits/ 64 <535000000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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required-opps = <&rpmhpd_opp_nom_l1>;
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};
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opp-630000000 {
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opp-hz = /bits/ 64 <630000000>;
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required-opps = <&rpmhpd_opp_turbo>;
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};
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};
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};
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dsi@ae94000 {
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compatible = "qcom,milos-dsi-ctrl", "qcom,mdss-dsi-ctrl";
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reg = <0x0ae94000 0x1000>;
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reg-names = "dsi_ctrl";
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interrupts-extended = <&mdss 4>;
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clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
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<&dispcc DISP_CC_MDSS_ESC0_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&gcc GCC_DISP_HF_AXI_CLK>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus";
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assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
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assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
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<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
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operating-points-v2 = <&mdss_dsi_opp_table>;
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power-domains = <&rpmhpd RPMHPD_CX>;
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phys = <&mdss_dsi0_phy>;
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phy-names = "dsi";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdss_dsi0_in: endpoint {
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remote-endpoint = <&dpu_intf1_out>;
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};
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};
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port@1 {
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reg = <1>;
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mdss_dsi0_out: endpoint {
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};
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};
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};
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mdss_dsi_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-187500000 {
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opp-hz = /bits/ 64 <187500000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-358000000 {
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opp-hz = /bits/ 64 <358000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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};
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};
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mdss_dsi0_phy: phy@ae95000 {
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compatible = "qcom,milos-dsi-phy-4nm";
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reg = <0x0ae95000 0x200>,
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<0x0ae95200 0x300>,
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<0x0ae95500 0x400>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface",
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"ref";
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#clock-cells = <1>;
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#phy-cells = <0>;
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};
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};
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...
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