108 lines
3.7 KiB
ReStructuredText
108 lines
3.7 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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======================================
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Motorcomm yt8xxx PHY properties (_DSD)
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======================================
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This document describes ACPI _DSD device properties for Motorcomm yt8xxx
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Ethernet PHYs supported by the in-kernel driver in
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``drivers/net/phy/motorcomm.c``.
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The properties are exposed on the PHY device object under the MDIO bus ACPI
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device (the same objects that are registered via
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``fwnode_mdiobus_register_phy()``). MAC-side connection properties such as
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``phy-handle`` and ``phy-mode`` are documented in [acpi-mdio-phy]_.
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Property names and semantics are intentionally aligned with the Devicetree
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binding [motorcomm-yt8xxx]_ so that the same driver code path
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(``device_property_*`` on ``&phydev->mdio.dev``) can consume firmware
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described either as Devicetree or ACPI _DSD.
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UUID and placement
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==================
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Per [acpi-dsd-properties-rules]_ and [acpi-mdio-phy]_, properties must be
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placed in an _DSD package using the standard Device Properties UUID::
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ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301")
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Properties
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==========
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Unless noted otherwise, integer properties use the same allowed values and
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defaults as [motorcomm-yt8xxx]_.
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``rx-internal-delay-ps`` (u32, optional)
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RGMII RX internal delay in picoseconds. Only meaningful when the link is
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using RGMII modes with RX internal delay; see [motorcomm-yt8xxx]_.
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``tx-internal-delay-ps`` (u32, optional)
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RGMII TX internal delay in picoseconds. Only meaningful when the link is
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using RGMII modes with TX internal delay; see [motorcomm-yt8xxx]_.
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``motorcomm,clk-out-frequency-hz`` (u32, optional)
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Clock output frequency on the PHY clock output pin. Allowed values and
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default are defined in [motorcomm-yt8xxx]_.
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``motorcomm,keep-pll-enabled`` (boolean, optional)
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If true, keep the PLL enabled even when there is no link (useful for using
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the clock output without an Ethernet link). See [motorcomm-yt8xxx]_.
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``motorcomm,auto-sleep-disabled`` (boolean, optional)
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If true, disable the PHY auto-sleep behavior described in
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[motorcomm-yt8xxx]_.
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``motorcomm,rx-clk-drv-microamp`` (u32, optional)
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Drive strength for the ``rx_clk`` RGMII pad in microamps. Allowed values
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depend on the configured RGMII LDO voltage; see [motorcomm-yt8xxx]_.
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``motorcomm,rx-data-drv-microamp`` (u32, optional)
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Drive strength for the ``rx_data`` and ``rx_ctl`` RGMII pads in microamps.
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See [motorcomm-yt8xxx]_.
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``motorcomm,tx-clk-adj-enabled`` (boolean, optional)
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Enables adjustments related to ``motorcomm,tx-clk-*-inverted`` usage; see
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[motorcomm-yt8xxx]_.
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``motorcomm,tx-clk-10-inverted`` (boolean, optional)
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``motorcomm,tx-clk-100-inverted`` (boolean, optional)
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``motorcomm,tx-clk-1000-inverted`` (boolean, optional)
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Per-speed TX clock inversion options; see [motorcomm-yt8xxx]_.
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ASL example (illustrative)
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==========================
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The example below only shows PHY-local _DSD properties. A real platform
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still needs a MAC ``phy-handle`` and ``phy-mode`` package as in
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[acpi-mdio-phy]_.
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.. code-block:: none
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Scope (\_SB.MDI0)
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{
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Device (PHY4)
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{
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Name (_ADR, 0x4)
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Name (_DSD, Package () {
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ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
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Package () {
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Package (2) { "rx-internal-delay-ps", 2100 },
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Package (2) { "tx-internal-delay-ps", 150 },
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Package (2) { "motorcomm,clk-out-frequency-hz", 0 },
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Package (2) { "motorcomm,keep-pll-enabled", 1 },
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Package (2) { "motorcomm,auto-sleep-disabled", 1 },
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}
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})
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}
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}
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References
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==========
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.. [acpi-mdio-phy] Documentation/firmware-guide/acpi/dsd/phy.rst
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.. [acpi-dsd-properties-rules]
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Documentation/firmware-guide/acpi/DSD-properties-rules.rst
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.. [motorcomm-yt8xxx]
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Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml
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