104 lines
2.8 KiB
Devicetree
104 lines
2.8 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2026 Stefan Dösinger <stefandoesinger@gmail.com>
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0>;
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};
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};
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/* Base bus clock and default for the UART. It will be replaced once a clock driver has
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* been added.
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*/
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uartclk: uartclk-26000000 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <26000000>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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clock-frequency = <26000000>;
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interrupt-parent = <&gic>;
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/* I don't think uboot sets CNTVOFF and the stock kernel doesn't use the
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* arm timer at all. Since this is a single CPU system I don't think it
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* really matters that the offset is random though.
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*/
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arm,cpu-registers-not-fw-configured;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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/* The GIC has a non-standard way of configuring ints between level-low/level
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* high or rising edge/falling edge at 0xf2202070 and onwards. See AP_INT_MODE_BASE
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* and AP_PPI_MODE_REG in the ZTE kernel, although the offsets in the kernel source
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* seem wrong.
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*
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* Everything defaults to active-high/rising edge, but the timer is active-low. We
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* currently rely on the boot loader to change timer IRQs to active-low for us for
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* now.
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*/
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gic: interrupt-controller@f2000000 {
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compatible = "arm,gic-v3";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xf2000000 0x10000>,
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<0xf2040000 0x20000>;
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};
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uart0: serial@131000 {
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compatible = "arm,pl011", "arm,primecell";
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arm,primecell-periphid = <0x0018c011>;
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reg = <0x00131000 0x1000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk>, <&uartclk>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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uart1: serial@1408000 {
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compatible = "arm,pl011", "arm,primecell";
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arm,primecell-periphid = <0x0018c011>;
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reg = <0x01408000 0x1000>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk>, <&uartclk>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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uart2: serial@140d000 {
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compatible = "arm,pl011", "arm,primecell";
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arm,primecell-periphid = <0x0018c011>;
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reg = <0x0140d000 0x1000>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk>, <&uartclk>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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};
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};
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