1171 lines
31 KiB
Devicetree
1171 lines
31 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/*
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* Copyright (c) Toradex
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*
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* Common dtsi for Verdin iMX95 SoM
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*
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* https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
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*/
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#include <dt-bindings/net/ti-dp83867.h>
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#include "imx95.dtsi"
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/ {
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aliases {
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can0 = &flexcan1;
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can1 = &flexcan2;
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eeprom0 = &som_eeprom;
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ethernet0 = &enetc_port0;
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ethernet1 = &enetc_port1;
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i2c0 = &lpi2c2;
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i2c1 = &lpi2c4;
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i2c2 = &lpi2c3;
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i2c3 = &i3c2;
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i2c4 = &lpi2c5;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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mmc2 = &usdhc3;
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rtc0 = &rtc_i2c;
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rtc1 = &scmi_bbm;
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serial0 = &lpuart7;
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serial1 = &lpuart8;
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serial2 = &lpuart1;
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serial3 = &lpuart2;
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serial4 = &lpuart6;
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usb0 = &usb2;
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usb1 = &usb3;
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};
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chosen {
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stdout-path = "serial2:115200n8";
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};
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connector {
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compatible = "gpio-usb-b-connector", "usb-b-connector";
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/* Verdin USB_1_ID (SODIMM 161) */
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id-gpios = <&som_gpio_expander 5 GPIO_ACTIVE_HIGH>;
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label = "USB_1";
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self-powered;
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vbus-supply = <®_usb1_vbus>;
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port {
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usb_dr_connector: endpoint {
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remote-endpoint = <&usb1_id>;
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};
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};
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};
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verdin_gpio_keys: gpio-keys {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ctrl_wake1_mico>;
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status = "disabled";
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verdin_key_wakeup: key-wakeup {
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/* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
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gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
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label = "Wake-Up";
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linux,code = <KEY_WAKEUP>;
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wakeup-source;
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};
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-max-microvolt = <1800000>;
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regulator-min-microvolt = <1800000>;
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regulator-name = "On-module +V1.8";
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};
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/*
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* By default we enable CTRL_SLEEP_MOCI#, this is required to have
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* peripherals on the carrier board powered.
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* If more granularity or power saving is required this can be disabled
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* in the carrier board device tree files.
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*/
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reg_force_sleep_moci: regulator-force-sleep-moci {
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compatible = "regulator-fixed";
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/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
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gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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regulator-boot-on;
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regulator-name = "CTRL_SLEEP_MOCI#";
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};
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reg_usb1_vbus: regulator-usb1-vbus {
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compatible = "regulator-fixed";
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/* Verdin USB_1_EN (SODIMM 155) */
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gpios = <&som_gpio_expander 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-name = "USB_1_EN";
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};
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reg_usb2_vbus: regulator-usb2-vbus {
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compatible = "regulator-fixed";
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/* Verdin USB_2_EN (SODIMM 185) */
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gpios = <&som_gpio_expander 8 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-name = "USB_2_EN";
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};
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reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
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compatible = "regulator-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2_vsel>;
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gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <1800000>;
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states = <1800000 0x1>,
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<3300000 0x0>;
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regulator-name = "PMIC_SD2_VSEL";
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};
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reg_usdhc2_vmmc: regulator-vmmc-usdhc2 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
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/* Verdin SD_1_PWR_EN (SODIMM 76) */
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gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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off-on-delay-us = <100000>;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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regulator-name = "SD_1_PWR_EN";
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startup-delay-us = <20000>;
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};
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cm7: remoteproc-cm7 {
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compatible = "fsl,imx95-cm7";
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mbox-names = "tx", "rx", "rxdb";
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mboxes = <&mu7 0 1
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&mu7 1 1
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&mu7 3 1>;
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memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
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<&vdev1vring0>, <&vdev1vring1>, <&rsc_table>, <&m7_reserved>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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linux_cma: linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0 0x3c000000>;
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alloc-ranges = <0 0x80000000 0 0x7F000000>;
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linux,cma-default;
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};
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m7_reserved: memory@80000000 {
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reg = <0 0x80000000 0 0x1000000>;
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no-map;
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};
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vdev0vring0: vdev0vring0@88000000 {
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reg = <0 0x88000000 0 0x8000>;
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no-map;
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};
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vdev0vring1: vdev0vring1@88008000 {
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reg = <0 0x88008000 0 0x8000>;
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no-map;
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};
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vdev1vring0: vdev1vring0@88010000 {
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reg = <0 0x88010000 0 0x8000>;
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no-map;
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};
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vdev1vring1: vdev1vring1@88018000 {
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reg = <0 0x88018000 0 0x8000>;
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no-map;
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};
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vdevbuffer: vdevbuffer@88020000 {
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compatible = "shared-dma-pool";
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reg = <0 0x88020000 0 0x100000>;
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no-map;
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};
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rsc_table: rsc-table@88220000 {
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reg = <0 0x88220000 0 0x1000>;
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no-map;
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};
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};
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};
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/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */
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&adc1 {
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vref-supply = <®_1p8v>;
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};
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/* Verdin ETH_1 (On-module PHY) */
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&enetc_port0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enetc0>;
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phy-handle = <ðphy1>;
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phy-mode = "rgmii-id";
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};
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/* Verdin ETH_2_RGMII */
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&enetc_port1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enetc1>;
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};
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/* Verdin CAN_1 */
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&flexcan1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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};
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/* Verdin CAN_2 */
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&flexcan2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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};
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/* Verdin QSPI_1 */
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&flexspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexspi1>;
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};
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&gpio1 {
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gpio-line-names =
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"", /* 0 */
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"",
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"",
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"",
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"SODIMM_147",
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"SODIMM_149",
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"SODIMM_151",
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"SODIMM_153",
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"SODIMM_20",
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"SODIMM_22",
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"SODIMM_252", /* 10 */
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"",
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"SODIMM_189",
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"IO_EXP_INT",
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"SODIMM_256",
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"";
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status = "okay";
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};
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&gpio2 {
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gpio-line-names =
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"SODIMM_206", /* 0 */
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"SODIMM_198",
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"SODIMM_200",
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"SODIMM_196",
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"",
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"SODIMM_15",
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"SODIMM_16",
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"",
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"SODIMM_131",
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"SODIMM_129",
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"SODIMM_135", /* 10 */
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"SODIMM_133",
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"SODIMM_139",
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"SODIMM_137",
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"SODIMM_143",
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"SODIMM_141",
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"SODIMM_30",
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"SODIMM_38",
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"SODIMM_208",
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"SODIMM_19",
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"SODIMM_36", /* 20 */
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"SODIMM_34",
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"SODIMM_93",
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"SODIMM_95",
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"SODIMM_210",
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"SODIMM_24",
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"SODIMM_32",
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"SODIMM_26",
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"SODIMM_53",
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"SODIMM_55",
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"SODIMM_12", /* 30 */
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"SODIMM_14";
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};
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&gpio3 {
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gpio-line-names =
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"SODIMM_84", /* 0 */
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"SODIMM_78",
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"SODIMM_74",
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"SODIMM_80",
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"SODIMM_82",
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"SODIMM_70",
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"SODIMM_72",
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"SODIMM_76",
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"",
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"",
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"", /* 10 */
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"PMIC_SD2_VSEL",
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"", /* 20 */
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"",
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"",
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"",
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"",
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"",
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"SODIMM_91",
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"SODIMM_218",
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"",
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"",
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"", /* 30 */
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"";
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};
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&gpio4 {
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gpio-line-names =
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"SODIMM_59", /* 0 */
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"SODIMM_57",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"", /* 10 */
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"",
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"",
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"",
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"SODIMM_193",
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"SODIMM_191",
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"SODIMM_215",
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"SODIMM_217",
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"SODIMM_219",
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"SODIMM_221",
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"SODIMM_211", /* 20 */
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"SODIMM_213",
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"SODIMM_199",
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"SODIMM_197",
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"SODIMM_201",
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"SODIMM_203",
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"SODIMM_205",
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"SODIMM_207",
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"SODIMM_216",
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"SODIMM_202";
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};
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&gpio5 {
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gpio-line-names =
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"SODIMM_56", /* 0 */
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"SODIMM_58",
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"SODIMM_60",
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"SODIMM_62",
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"SODIMM_46",
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"SODIMM_44",
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"SODIMM_42",
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"SODIMM_48",
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"SODIMM_66",
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"SODIMM_52",
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"SODIMM_54", /* 10 */
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"SODIMM_64",
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"SODIMM_212",
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"",
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"",
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"",
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"",
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"";
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};
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/* Verdin I2C_3_HDMI */
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&i3c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i3c2>;
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i2c-scl-hz = <400000>;
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};
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/* CTRL_I2C (On-module I2C) */
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&lpi2c2 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_lpi2c2>, <&pinctrl_io_exp_int>;
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pinctrl-1 = <&pinctrl_lpi2c2_gpio>, <&pinctrl_io_exp_int>;
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clock-frequency = <400000>;
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scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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single-master;
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status = "okay";
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som_gpio_expander: gpio@20 {
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compatible = "nxp,pcal6416";
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reg = <0x20>;
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#interrupt-cells = <2>;
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interrupt-controller;
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interrupt-parent = <&gpio1>;
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interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-line-names =
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"SODIMM_220", /* 0 */
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"SODIMM_222",
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"SODIMM_17",
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"SODIMM_21",
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"SODIMM_244",
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"SODIMM_161",
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"SODIMM_157",
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"SODIMM_155",
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"SODIMM_185",
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"SODIMM_187",
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"USB_RECOV_CTRL#", /* 10 */
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"ENET1_INT#",
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"TPM_INT#",
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"TPM_CS#",
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"",
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"";
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/*
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* Switch USB to default position:
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* - SoC USB2 -> Verdin USB_1
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* - SoC USB1 -> Verdin USB_2
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* Reset configuration:
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* - SoC USB1 -> Verdin USB_1 (USB recovery)
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* - SoC USB2 not connected
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*/
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usb_recov_ctrl: usb-recov-ctrl-hog {
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gpio-hog;
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gpios = <10 GPIO_ACTIVE_HIGH>;
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line-name = "USB_RECOV_CTRL#";
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output-high;
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};
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};
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rtc_i2c: rtc@32 {
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compatible = "epson,rx8130";
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reg = <0x32>;
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};
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temperature-sensor@48 {
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compatible = "ti,tmp1075";
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reg = <0x48>;
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};
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som_eeprom: eeprom@50 {
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compatible = "st,24c02", "atmel,24c02";
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reg = <0x50>;
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pagesize = <16>;
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};
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};
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/* Verdin I2C_2_DSI */
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&lpi2c3 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_lpi2c3>;
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pinctrl-1 = <&pinctrl_lpi2c3_gpio>;
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clock-frequency = <100000>;
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scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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single-master;
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};
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/* Verdin I2C_1 */
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&lpi2c4 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_lpi2c4>;
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pinctrl-1 = <&pinctrl_lpi2c4_gpio>;
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clock-frequency = <100000>;
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scl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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single-master;
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};
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/* Verdin I2C_4_CSI */
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&lpi2c5 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_lpi2c5>;
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pinctrl-1 = <&pinctrl_lpi2c5_gpio>;
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clock-frequency = <100000>;
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scl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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single-master;
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};
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/* Verdin SPI_1 */
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&lpspi6 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpspi6>, <&pinctrl_spi1_cs>;
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cs-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>,
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<&som_gpio_expander 13 GPIO_ACTIVE_LOW>;
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status = "okay";
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som_tpm: tpm@1 {
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compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
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reg = <0x1>;
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interrupt-parent = <&som_gpio_expander>;
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interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
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/*
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* Maximum TPM-supported speed is 18.5 MHz, limited to 12 MHz
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* here as lpspi6's per-clock (twice the max speed) is 24 MHz
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*/
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spi-max-frequency = <12000000>;
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};
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};
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/* Verdin UART_3, used as the Linux console */
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&lpuart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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};
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|
|
/* Verdin UART_4 */
|
|
&lpuart2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart2>;
|
|
};
|
|
|
|
/* Verdin UART_1 */
|
|
&lpuart7 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart7>;
|
|
uart-has-rtscts;
|
|
};
|
|
|
|
/* Verdin UART_2 */
|
|
&lpuart8 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart8>, <&pinctrl_uart8_cts>, <&pinctrl_uart8_rts>;
|
|
uart-has-rtscts;
|
|
};
|
|
|
|
&mu7 {
|
|
status = "okay";
|
|
};
|
|
|
|
&netc_blk_ctrl {
|
|
status = "okay";
|
|
};
|
|
|
|
&netc_bus0 {
|
|
msi-map = <0x0 &its 0x60 0x1>, //ENETC0 PF
|
|
<0x10 &its 0x61 0x1>, //ENETC0 VF0
|
|
<0x20 &its 0x62 0x1>, //ENETC0 VF1
|
|
<0x40 &its 0x63 0x1>, //ENETC1 PF
|
|
<0x50 &its 0x65 0x1>, //ENETC1 VF0
|
|
<0x60 &its 0x66 0x1>, //ENETC1 VF1
|
|
<0x80 &its 0x64 0x1>, //ENETC2 PF
|
|
<0xc0 &its 0x67 0x1>; //NETC Timer
|
|
iommu-map = <0x0 &smmu 0x20 0x1>,
|
|
<0x10 &smmu 0x21 0x1>,
|
|
<0x20 &smmu 0x22 0x1>,
|
|
<0x40 &smmu 0x23 0x1>,
|
|
<0x50 &smmu 0x25 0x1>,
|
|
<0x60 &smmu 0x26 0x1>,
|
|
<0x80 &smmu 0x24 0x1>,
|
|
<0xc0 &smmu 0x27 0x1>;
|
|
};
|
|
|
|
/* Verdin ETH_2_RGMII_MDIO, shared between all ethernet ports */
|
|
&netc_emdio {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_emdio>;
|
|
|
|
status = "okay";
|
|
|
|
ethphy1: ethernet-phy@0 {
|
|
reg = <0>;
|
|
interrupt-parent = <&som_gpio_expander>;
|
|
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
|
|
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
|
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
|
};
|
|
};
|
|
|
|
&netc_timer {
|
|
status = "okay";
|
|
};
|
|
|
|
&netcmix_blk_ctrl {
|
|
status = "okay";
|
|
};
|
|
|
|
/* Verdin PCIE_1 */
|
|
&pcie0 {
|
|
/* PCIE_1_RESET# (SODIMM 244) */
|
|
reset-gpios = <&som_gpio_expander 4 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
/* Verdin I2S_1 */
|
|
&sai3 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_sai3>;
|
|
assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
|
|
<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
|
|
<&scmi_clk IMX95_CLK_AUDIOPLL1>,
|
|
<&scmi_clk IMX95_CLK_AUDIOPLL2>,
|
|
<&scmi_clk IMX95_CLK_SAI3>;
|
|
assigned-clock-parents = <0>, <0>, <0>, <0>,
|
|
<&scmi_clk IMX95_CLK_AUDIOPLL1>;
|
|
assigned-clock-rates = <3932160000>,
|
|
<3612672000>, <393216000>,
|
|
<361267200>, <12288000>;
|
|
#sound-dai-cells = <0>;
|
|
fsl,sai-mclk-direction-output;
|
|
};
|
|
|
|
&scmi_bbm {
|
|
linux,code = <KEY_POWER>;
|
|
};
|
|
|
|
&thermal_zones {
|
|
/* PF09 Main PMIC */
|
|
pf09-thermal {
|
|
polling-delay = <2000>;
|
|
polling-delay-passive = <250>;
|
|
thermal-sensors = <&scmi_sensor 2>;
|
|
|
|
trips {
|
|
trip0 {
|
|
hysteresis = <2000>;
|
|
temperature = <155000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
/* PF53 VDD_ARM PMIC */
|
|
pf53-arm-thermal {
|
|
polling-delay = <2000>;
|
|
polling-delay-passive = <250>;
|
|
thermal-sensors = <&scmi_sensor 4>;
|
|
|
|
trips {
|
|
trip0 {
|
|
hysteresis = <2000>;
|
|
temperature = <155000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
/* PF53 VDD_SOC PMIC */
|
|
pf53-soc-thermal {
|
|
polling-delay = <2000>;
|
|
polling-delay-passive = <250>;
|
|
thermal-sensors = <&scmi_sensor 3>;
|
|
|
|
trips {
|
|
trip0 {
|
|
hysteresis = <2000>;
|
|
temperature = <155000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
/* Verdin PWM_1 */
|
|
&tpm4 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_tpm4>;
|
|
};
|
|
|
|
/* Verdin PWM_2 */
|
|
&tpm5 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_tpm5>;
|
|
};
|
|
|
|
/* Verdin PWM_3_DSI */
|
|
&tpm6 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_tpm6>;
|
|
};
|
|
|
|
/* Verdin USB_1 */
|
|
&usb2 {
|
|
dr_mode = "otg";
|
|
adp-disable;
|
|
hnp-disable;
|
|
srp-disable;
|
|
usb-role-switch;
|
|
vbus-supply = <®_usb1_vbus>;
|
|
|
|
port {
|
|
usb1_id: endpoint {
|
|
remote-endpoint = <&usb_dr_connector>;
|
|
};
|
|
};
|
|
};
|
|
|
|
/* Verdin USB_2 */
|
|
&usb3 {
|
|
fsl,disable-port-power-control;
|
|
};
|
|
|
|
&usb3_dwc3 {
|
|
dr_mode = "host";
|
|
};
|
|
|
|
&usb3_phy {
|
|
vbus-supply = <®_usb2_vbus>;
|
|
};
|
|
|
|
/* On-module eMMC */
|
|
&usdhc1 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
pinctrl-0 = <&pinctrl_usdhc1>;
|
|
pinctrl-1 = <&pinctrl_usdhc1>;
|
|
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
|
bus-width = <8>;
|
|
non-removable;
|
|
no-sdio;
|
|
no-sd;
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
/* Verdin SD_1 */
|
|
&usdhc2 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
|
|
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
|
|
pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
|
|
pinctrl-2 = <&pinctrl_usdhc2_200mhz>,<&pinctrl_usdhc2_cd>;
|
|
pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd>;
|
|
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
|
|
vmmc-supply = <®_usdhc2_vmmc>;
|
|
vqmmc-supply = <®_usdhc2_vqmmc>;
|
|
};
|
|
|
|
&wdog3 {
|
|
fsl,ext-reset-output;
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
&scmi_iomuxc {
|
|
/* On-module Bluetooth on WB SKUs, module-specific UART otherwise */
|
|
pinctrl_bt_uart: btuartgrp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO04__LPUART6_TX 0x31e>, /* WiFi_UART_SoC_TXD */
|
|
<IMX95_PAD_GPIO_IO33__LPUART6_RX 0x31e>, /* WiFi_UART_SoC_RXD */
|
|
<IMX95_PAD_GPIO_IO34__LPUART6_CTS_B 0x31e>, /* WiFi_UART_SoC_CTS */
|
|
<IMX95_PAD_GPIO_IO07__LPUART6_RTS_B 0x31e>; /* WiFi_UART_SoC_RTS */
|
|
};
|
|
|
|
/* Verdin CSI_1_MCLK */
|
|
pinctrl_csi1_mclk: csi1mclkgrp {
|
|
fsl,pins = <IMX95_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1 0x51e>; /* SODIMM 91 */
|
|
};
|
|
|
|
/* Verdin CTRL_SLEEP_MOCI# */
|
|
pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
|
|
fsl,pins = <IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14 0x51e>; /* SODIMM 256 */
|
|
};
|
|
|
|
/* Verdin CTRL_WAKE1_MICO# */
|
|
pinctrl_ctrl_wake1_mico: ctrlwake1micogrp {
|
|
fsl,pins = <IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10 0x31e>; /* SODIMM 252 */
|
|
};
|
|
|
|
/* Verdin ETH_2_RGMII_MDIO, shared between all ethernet ports */
|
|
pinctrl_emdio: emdiogrp {
|
|
fsl,pins = <IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x50e>, /* ENET2_MDC, SODIMM 193 */
|
|
<IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e>; /* ENET2_MDIO, SODIMM 191 */
|
|
};
|
|
|
|
/* Verdin ETH_1 (On-module PHY) */
|
|
pinctrl_enetc0: enetc0grp {
|
|
fsl,pins = <IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e>, /* ENET1_TX_CTL */
|
|
<IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e>, /* ENET1_TXC */
|
|
<IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e>, /* ENET1_TDO */
|
|
<IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e>, /* ENET1_TD1 */
|
|
<IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e>, /* ENET1_TD2 */
|
|
<IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e>, /* ENET1_TD3 */
|
|
<IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e>, /* ENET1_RX_CTL */
|
|
<IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e>, /* ENET1_RXC */
|
|
<IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e>, /* ENET1_RD0 */
|
|
<IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e>, /* ENET1_RD1 */
|
|
<IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e>, /* ENET1_RD2 */
|
|
<IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e>; /* ENET1_RD3 */
|
|
};
|
|
|
|
/* Verdin ETH_2_RGMII */
|
|
pinctrl_enetc1: enetc1grp {
|
|
fsl,pins = <IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e>, /* ENET2_TX_CTL */
|
|
<IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e>, /* ENET2_TXC */
|
|
<IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x50e>, /* ENET2_TD0 */
|
|
<IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x50e>, /* ENET2_TD1 */
|
|
<IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x50e>, /* ENET2_TD2 */
|
|
<IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x50e>, /* ENET2_TD3 */
|
|
<IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e>, /* ENET2_RX_CTL */
|
|
<IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x58e>, /* ENET2_RXC */
|
|
<IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e>, /* ENET2_RD0 */
|
|
<IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e>, /* ENET2_RD1 */
|
|
<IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e>, /* ENET2_RD2 */
|
|
<IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e>; /* ENET2_RD3 */
|
|
};
|
|
|
|
/* Verdin ETH_2_RGMII_INT# */
|
|
pinctrl_eth2_rgmii_int: eth2rgmiiintgrp {
|
|
fsl,pins = <IMX95_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_BIT12 0x31e>; /* SODIMM 189 */
|
|
};
|
|
|
|
/* Verdin CAN_1 */
|
|
pinctrl_flexcan1: flexcan1grp {
|
|
fsl,pins = <IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e>, /* SODIMM 20 */
|
|
<IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e>; /* SODIMM 22 */
|
|
};
|
|
|
|
/* Verdin CAN_2 */
|
|
pinctrl_flexcan2: flexcan2grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e>, /* SODIMM 24 */
|
|
<IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e>; /* SODIMM 26 */
|
|
};
|
|
|
|
/* Verdin QSPI_1 */
|
|
pinctrl_flexspi1: flexspi1grp {
|
|
fsl,pins = <IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x3fe>, /* SODIMM 54 */
|
|
<IMX95_PAD_XSPI1_SS1_B__FLEXSPI1_A_SS1_B 0x3fe>, /* SODIMM 64 */
|
|
<IMX95_PAD_XSPI1_SCLK__XSPI_CLK 0x3fe>, /* SODIMM 52 */
|
|
<IMX95_PAD_XSPI1_DATA0__XSPI_DATA_BIT0 0x3fe>, /* SODIMM 56 */
|
|
<IMX95_PAD_XSPI1_DATA1__XSPI_DATA_BIT1 0x3fe>, /* SODIMM 58 */
|
|
<IMX95_PAD_XSPI1_DATA2__XSPI_DATA_BIT2 0x3fe>, /* SODIMM 60 */
|
|
<IMX95_PAD_XSPI1_DATA3__XSPI_DATA_BIT3 0x3fe>, /* SODIMM 62 */
|
|
<IMX95_PAD_XSPI1_DQS__XSPI_DQS 0x3fe>; /* SODIMM 66 */
|
|
};
|
|
|
|
/* Verdin GPIO_1 */
|
|
pinctrl_gpio1: gpio1grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0 0x51e>; /* SODIMM 206 */
|
|
};
|
|
|
|
/* Verdin GPIO_2 */
|
|
pinctrl_gpio2: gpio2grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x51e>; /* SODIMM 208 */
|
|
};
|
|
|
|
/* Verdin GPIO_3 */
|
|
pinctrl_gpio3: gpio3grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24 0x51e>; /* SODIMM 210 */
|
|
};
|
|
|
|
/* Verdin GPIO_4 */
|
|
pinctrl_gpio4: gpio4grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO32__GPIO5_IO_BIT12 0x51e>; /* SODIMM 212 */
|
|
};
|
|
|
|
/* Verdin GPIO_5_CSI */
|
|
pinctrl_gpio5: gpio5grp {
|
|
fsl,pins = <IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x51e>; /* SODIMM 216 */
|
|
};
|
|
|
|
/* Verdin GPIO_6_CSI */
|
|
pinctrl_gpio6: gpio6grp {
|
|
fsl,pins = <IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x51e>; /* SODIMM 218 */
|
|
};
|
|
|
|
/* Verdin I2S_2_BCLK as GPIO (conflict with Verdin I2S_2) */
|
|
pinctrl_i2s_2_bclk_gpio: i2s2bclkgpiogrp {
|
|
fsl,pins = <IMX95_PAD_XSPI1_DATA6__GPIO5_IO_BIT6 0x51e>; /* SODIMM 42 */
|
|
};
|
|
|
|
/* Verdin I2S_2_D_IN as GPIO (conflict with Verdin I2S_2) */
|
|
pinctrl_i2s_2_d_in_gpio: i2s2dingpiogrp {
|
|
fsl,pins = <IMX95_PAD_XSPI1_DATA7__GPIO5_IO_BIT7 0x31e>; /* SODIMM 48 */
|
|
};
|
|
|
|
/* Verdin I2S_2_D_OUT as GPIO (conflict with Verdin I2S_2) */
|
|
pinctrl_i2s_2_d_out_gpio: i2s2doutgpiogrp {
|
|
fsl,pins = <IMX95_PAD_XSPI1_DATA4__GPIO5_IO_BIT4 0x51e>; /* SODIMM 46 */
|
|
};
|
|
|
|
/* Verdin I2S_2_SYNC as GPIO (conflict with Verdin I2S_2) */
|
|
pinctrl_i2s_2_sync_gpio: i2s2syncgpiogrp {
|
|
fsl,pins = <IMX95_PAD_XSPI1_DATA5__GPIO5_IO_BIT5 0x51e>; /* SODIMM 44 */
|
|
};
|
|
|
|
/* Verdin I2C_3_HDMI */
|
|
pinctrl_i3c2: i3c2cgrp {
|
|
fsl,pins = <IMX95_PAD_ENET1_MDC__I3C2_SCL 0x40001186>, /* SODIMM 59 */
|
|
<IMX95_PAD_ENET1_MDIO__I3C2_SDA 0x40001186>; /* SODIMM 57 */
|
|
};
|
|
|
|
pinctrl_io_exp_int: ioexpintgrp {
|
|
fsl,pins = <IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13 0x31e>; /* IO_EXP_INT */
|
|
};
|
|
|
|
/* CTRL_I2C (On-module I2C) */
|
|
pinctrl_lpi2c2_gpio: lpi2c2gpiogrp {
|
|
fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2 0x40001b9e>, /* CTRL_I2C_SCL */
|
|
<IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3 0x40001b9e>; /* CTRL_I2C_SDA */
|
|
};
|
|
|
|
pinctrl_lpi2c2: lpi2c2grp {
|
|
fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40001b9e>, /* CTRL_I2C_SCL */
|
|
<IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40001b9e>; /* CTRL_I2C_SDA */
|
|
};
|
|
|
|
/* Verdin I2C_2_DSI */
|
|
pinctrl_lpi2c3_gpio: lpi2c3gpiogrp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x40001b9e>, /* SODIMM 53 */
|
|
<IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x40001b9e>; /* SODIMM 55 */
|
|
};
|
|
|
|
pinctrl_lpi2c3: lpi2c3grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40001b9e>, /* SODIMM 53 */
|
|
<IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40001b9e>; /* SODIMM 55 */
|
|
};
|
|
|
|
/* Verdin I2C_1 */
|
|
pinctrl_lpi2c4_gpio: lpi2c4gpiogrp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x40001b9e>, /* SODIMM 14 */
|
|
<IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x40001b9e>; /* SODIMM 12 */
|
|
};
|
|
|
|
pinctrl_lpi2c4: lpi2c4grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40001b9e>, /* SODIMM 14 */
|
|
<IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40001b9e>; /* SODIMM 12 */
|
|
};
|
|
|
|
/* Verdin I2C_4_CSI */
|
|
pinctrl_lpi2c5_gpio: lpi2c5gpiogrp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x40001b9e>, /* SODIMM 93 */
|
|
<IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23 0x40001b9e>; /* SODIMM 95 */
|
|
};
|
|
|
|
pinctrl_lpi2c5: lpi2c5grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40001b9e>, /* SODIMM 93 */
|
|
<IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40001b9e>; /* SODIMM 95 */
|
|
};
|
|
|
|
/* Verdin SPI_1 */
|
|
pinctrl_lpspi6: lpspi6grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe>, /* SODIMM 198 */
|
|
<IMX95_PAD_GPIO_IO02__LPSPI6_SOUT 0x3fe>, /* SODIMM 200 */
|
|
<IMX95_PAD_GPIO_IO03__LPSPI6_SCK 0x3fe>; /* SODIMM 196 */
|
|
};
|
|
|
|
/* Verdin QSPI_1_CLK as GPIO (conflict with Verdin QSPI_1 interface) */
|
|
pinctrl_qspi1_clk_gpio: qspi1clkgpiogrp {
|
|
fsl,pins = <IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x11e>; /* SODIMM 52 */
|
|
};
|
|
|
|
/* Verdin QSPI_1_CS2# as GPIO (conflict with Verdin QSPI_1 interface) */
|
|
pinctrl_qspi1_cs2_gpio: qspi1cs2gpiogrp {
|
|
fsl,pins = <IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x11e>; /* SODIMM 64 */
|
|
};
|
|
|
|
/* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */
|
|
pinctrl_qspi1_cs_gpio: qspi1csgpiogrp {
|
|
fsl,pins = <IMX95_PAD_XSPI1_SS0_B__GPIO5_IO_BIT10 0x11e>; /* SODIMM 54 */
|
|
};
|
|
|
|
/* Verdin QSPI_1_DQS as GPIO (conflict with Verdin QSPI_1 interface) */
|
|
pinctrl_qspi1_dqs_gpio: qspi1dqsgpiogrp {
|
|
fsl,pins = <IMX95_PAD_XSPI1_DQS__GPIO5_IO_BIT8 0x11e>; /* SODIMM 66 */
|
|
};
|
|
|
|
/* Verdin QSPI_1_IO0 as GPIO (conflict with Verdin QSPI_1 interface) */
|
|
pinctrl_qspi1_io0_gpio: qspi1io0gpiogrp {
|
|
fsl,pins = <IMX95_PAD_XSPI1_DATA0__GPIO5_IO_BIT0 0x119e>; /* SODIMM 56 */
|
|
};
|
|
|
|
/* Verdin QSPI_1_IO1 as GPIO (conflict with Verdin QSPI_1 interface) */
|
|
pinctrl_qspi1_io1_gpio: qspi1io1gpiogrp {
|
|
fsl,pins = <IMX95_PAD_XSPI1_DATA1__GPIO5_IO_BIT1 0x119e>; /* SODIMM 58 */
|
|
};
|
|
|
|
/* Verdin QSPI_1_IO2 as GPIO (conflict with Verdin QSPI_1 interface) */
|
|
pinctrl_qspi1_io2_gpio: qspi1io2gpiogrp {
|
|
fsl,pins = <IMX95_PAD_XSPI1_DATA2__GPIO5_IO_BIT2 0x11e>; /* SODIMM 60 */
|
|
};
|
|
|
|
/* Verdin QSPI_1_IO3 as GPIO (conflict with Verdin QSPI_1 interface) */
|
|
pinctrl_qspi1_io3_gpio: qspi1io3gpiogrp {
|
|
fsl,pins = <IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3 0x11e>; /* SODIMM 62 */
|
|
};
|
|
|
|
/* Verdin I2S_1 */
|
|
pinctrl_sai3: sai3grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x11e>, /* SODIMM 30 */
|
|
<IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x11e>, /* SODIMM 36 */
|
|
<IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x11e>, /* SODIMM 34 */
|
|
<IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x11e>; /* SODIMM 32 */
|
|
};
|
|
|
|
/* Verdin I2S_1_MCLK */
|
|
pinctrl_sai3_mclk: sai3mclkgrp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e>; /* SODIMM 38 */
|
|
};
|
|
|
|
/* Verdin I2S_2 */
|
|
pinctrl_sai5: sai5grp {
|
|
fsl,pins = <IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x11e>, /* SODIMM 46 */
|
|
<IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC 0x11e>, /* SODIMM 44 */
|
|
<IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK 0x11e>, /* SODIMM 42 */
|
|
<IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x11e>; /* SODIMM 48 */
|
|
};
|
|
|
|
/* Verdin SPI_1_CS */
|
|
pinctrl_spi1_cs: spi1csgrp {
|
|
fsl,pins = <IMX95_PAD_CCM_CLKO4__GPIO4_IO_BIT29 0x3fe>; /* SODIMM 202 */
|
|
};
|
|
|
|
/* Verdin PWM_1 */
|
|
pinctrl_tpm4: tpm4grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO05__TPM4_CH0 0x11e>; /* SODIMM 15 */
|
|
};
|
|
|
|
/* Verdin PWM_2 */
|
|
pinctrl_tpm5: tpm5grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO06__TPM5_CH0 0x11e>; /* SODIMM 16 */
|
|
};
|
|
|
|
/* Verdin PWM_3_DSI as GPIO */
|
|
pinctrl_tpm6_gpio: tpm6gpiogrp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO19__GPIO2_IO_BIT19 0x51e>; /* SODIMM 19 */
|
|
};
|
|
|
|
/* Verdin PWM_3_DSI */
|
|
pinctrl_tpm6: tpm6grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO19__TPM6_CH2 0x11e>; /* SODIMM 19 */
|
|
};
|
|
|
|
/* Verdin UART_3, used as the Linux Console */
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e>, /* SODIMM 147 */
|
|
<IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e>; /* SODIMM 149 */
|
|
};
|
|
|
|
/* Verdin UART_4 */
|
|
pinctrl_uart2: uart2grp {
|
|
fsl,pins = <IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x31e>, /* SODIMM 151 */
|
|
<IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x31e>; /* SODIMM 153 */
|
|
};
|
|
|
|
/* Verdin UART_1 */
|
|
pinctrl_uart7: uart7grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO08__LPUART7_TX 0x31e>, /* SODIMM 131 */
|
|
<IMX95_PAD_GPIO_IO09__LPUART7_RX 0x31e>, /* SODIMM 129 */
|
|
<IMX95_PAD_GPIO_IO10__LPUART7_CTS_B 0x31e>, /* SODIMM 135 */
|
|
<IMX95_PAD_GPIO_IO11__LPUART7_RTS_B 0x31e>; /* SODIMM 133 */
|
|
};
|
|
|
|
/* Verdin UART_2 CTS */
|
|
pinctrl_uart8_cts: uart8ctsgrp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO14__LPUART8_CTS_B 0x31e>; /* SODIMM 143 */
|
|
};
|
|
|
|
/* Verdin UART_2 RTS */
|
|
pinctrl_uart8_rts: uart8rtsgrp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO15__LPUART8_RTS_B 0x31e>; /* SODIMM 141 */
|
|
};
|
|
|
|
/* Verdin UART_2 RX/TX */
|
|
pinctrl_uart8: uart8grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO12__LPUART8_TX 0x31e>, /* SODIMM 139 */
|
|
<IMX95_PAD_GPIO_IO13__LPUART8_RX 0x31e>; /* SODIMM 137 */
|
|
};
|
|
|
|
/* On-module eMMC */
|
|
pinctrl_usdhc1: usdhc1grp {
|
|
fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>, /* SD1_CLK */
|
|
<IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>, /* SD1_CMD */
|
|
<IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>, /* SD1_DATA0 */
|
|
<IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>, /* SD1_DATA1 */
|
|
<IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>, /* SD1_DATA2 */
|
|
<IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>, /* SD1_DATA3 */
|
|
<IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>, /* SD1_DATA4 */
|
|
<IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>, /* SD1_DATA5 */
|
|
<IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>, /* SD1_DATA6 */
|
|
<IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>, /* SD1_DATA7 */
|
|
<IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>; /* SD1_STROBE */
|
|
};
|
|
|
|
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
|
|
fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe>, /* SD1_CLK */
|
|
<IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe>, /* SD1_CMD */
|
|
<IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe>, /* SD1_DATA0 */
|
|
<IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe>, /* SD1_DATA1 */
|
|
<IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe>, /* SD1_DATA2 */
|
|
<IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe>, /* SD1_DATA3 */
|
|
<IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe>, /* SD1_DATA4 */
|
|
<IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe>, /* SD1_DATA5 */
|
|
<IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe>, /* SD1_DATA6 */
|
|
<IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe>, /* SD1_DATA7 */
|
|
<IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe>; /* SD1_STROBE */
|
|
};
|
|
|
|
/* Verdin SD_1 */
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e>, /* SODIMM 78 */
|
|
<IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e>, /* SODIMM 74 */
|
|
<IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e>, /* SODIMM 80 */
|
|
<IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e>, /* SODIMM 82 */
|
|
<IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e>, /* SODIMM 70 */
|
|
<IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e>; /* SODIMM 72 */
|
|
};
|
|
|
|
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
|
fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe>, /* SODIMM 78 */
|
|
<IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe>, /* SODIMM 74 */
|
|
<IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe>, /* SODIMM 80 */
|
|
<IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe>, /* SODIMM 82 */
|
|
<IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe>, /* SODIMM 70 */
|
|
<IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe>; /* SODIMM 72 */
|
|
};
|
|
|
|
pinctrl_usdhc2_sleep: usdhc2-sleepgrp {
|
|
fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x400>, /* SODIMM 78 */
|
|
<IMX95_PAD_SD2_CMD__USDHC2_CMD 0x400>, /* SODIMM 74 */
|
|
<IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x400>, /* SODIMM 80 */
|
|
<IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x400>, /* SODIMM 82 */
|
|
<IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x400>, /* SODIMM 70 */
|
|
<IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x400>; /* SODIMM 72 */
|
|
};
|
|
|
|
/* Verdin SD_1_CD# */
|
|
pinctrl_usdhc2_cd: usdhc2-cdgrp {
|
|
fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>; /* SODIMM 84 */
|
|
};
|
|
|
|
/* Verdin SD_1_PWR_EN */
|
|
pinctrl_usdhc2_pwr_en: usdhc2-pwrengrp {
|
|
fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x11e>; /* SODIMM 76 */
|
|
};
|
|
|
|
pinctrl_usdhc2_vsel: usdhc2-vselgrp {
|
|
fsl,pins = <IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19 0x4>; /* PMIC_SD2_VSEL */
|
|
};
|
|
|
|
/* On-module Wi-Fi on WB SKUs, module-specific SDIO otherwise */
|
|
pinctrl_usdhc3: usdhc3grp {
|
|
fsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e>, /* SD3_CLK */
|
|
<IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e>, /* SD3_CMD */
|
|
<IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e>, /* SD3_DATA0 */
|
|
<IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e>, /* SD3_DATA1 */
|
|
<IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e>, /* SD3_DATA2 */
|
|
<IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e>; /* SD3_DATA3 */
|
|
};
|
|
|
|
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
|
fsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe>, /* SD3_CLK */
|
|
<IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe>, /* SD3_CMD */
|
|
<IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe>, /* SD3_DATA1 */
|
|
<IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe>, /* SD3_DATA2 */
|
|
<IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe>, /* SD3_DATA3 */
|
|
<IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe>; /* SD3_DATA4 */
|
|
};
|
|
|
|
pinctrl_wifi_pwr_en: wifipwrengrp {
|
|
fsl,pins = <IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11 0x51e>; /* PMIC_EN_WIFI */
|
|
};
|
|
};
|