115 lines
3.4 KiB
YAML
115 lines
3.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/spacemit,k1-combo-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SpacemiT K1 PCIe/USB3 Combo PHY
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maintainers:
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- Alex Elder <elder@riscstar.com>
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description: >
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Of the three PHYs on the SpacemiT K1 SoC capable of being used for
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PCIe, one is a combo PHY that can also be configured for use by a
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USB 3 controller. Using PCIe or USB 3 is a board design decision.
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The combo PHY is also the only PCIe PHY that is able to determine
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PCIe calibration values to use, and this must be determined before
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the other two PCIe PHYs can be used. This calibration must be
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performed with the combo PHY in PCIe mode, and is this is done
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when the combo PHY is probed.
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The combo PHY uses an external oscillator as a reference clock.
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During normal operation, the PCIe or USB port driver is responsible
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for ensuring all other clocks needed by a PHY are enabled, and all
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resets affecting the PHY are deasserted. However, for the combo
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PHY to perform calibration independent of whether it's later used
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for PCIe or USB, all PCIe mode clocks and resets must be defined.
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properties:
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compatible:
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const: spacemit,k1-combo-phy
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reg:
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items:
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- description: PHY control registers
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clocks:
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items:
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- description: External oscillator used by the PHY PLL
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- description: DWC PCIe Data Bus Interface (DBI) clock
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- description: DWC PCIe application AXI-bus Master interface clock
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- description: DWC PCIe application AXI-bus slave interface clock
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clock-names:
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items:
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- const: refclk
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- const: dbi
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- const: mstr
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- const: slv
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resets:
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items:
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- description: PHY reset; remains deasserted after initialization
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- description: DWC PCIe Data Bus Interface (DBI) reset
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- description: DWC PCIe application AXI-bus Master interface reset
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- description: DWC PCIe application AXI-bus slave interface reset
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reset-names:
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items:
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- const: phy
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- const: dbi
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- const: mstr
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- const: slv
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spacemit,apmu:
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description:
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A phandle that refers to the APMU system controller, whose
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regmap is used in setting the mode
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$ref: /schemas/types.yaml#/definitions/phandle
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"#phy-cells":
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const: 1
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description:
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The argument value (PHY_TYPE_PCIE or PHY_TYPE_USB3) determines
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whether the PHY operates in PCIe or USB3 mode.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- reset-names
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- spacemit,apmu
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- "#phy-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/spacemit,k1-syscon.h>
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phy@c0b10000 {
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compatible = "spacemit,k1-combo-phy";
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reg = <0xc0b10000 0x1000>;
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clocks = <&vctcxo_24m>,
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<&syscon_apmu CLK_PCIE0_DBI>,
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<&syscon_apmu CLK_PCIE0_MASTER>,
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<&syscon_apmu CLK_PCIE0_SLAVE>;
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clock-names = "refclk",
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"dbi",
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"mstr",
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"slv";
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resets = <&syscon_apmu RESET_PCIE0_GLOBAL>,
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<&syscon_apmu RESET_PCIE0_DBI>,
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<&syscon_apmu RESET_PCIE0_MASTER>,
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<&syscon_apmu RESET_PCIE0_SLAVE>;
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reset-names = "phy",
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"dbi",
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"mstr",
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"slv";
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spacemit,apmu = <&syscon_apmu>;
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#phy-cells = <1>;
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};
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