801 lines
27 KiB
YAML
801 lines
27 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/sound/renesas,r9a09g047-sound.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/G3E Sound Controller
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maintainers:
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- Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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- John Madieu <john.madieu.xa@bp.renesas.com>
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description:
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The RZ/G3E (R9A09G047) sound controller is based on R-Car Sound IP
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with extended DMA channel support (up to 5 DMACs per direction),
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additional clock domains (47 clocks including per-SSI ADG clocks),
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and additional reset lines (14 including SCU, ADG and Audio DMAC
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peri-peri resets). SSI operates exclusively in BUSIF mode with
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2-4 BUSIF channels per SSI.
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allOf:
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- $ref: dai-common.yaml#
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properties:
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compatible:
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const: renesas,r9a09g047-sound
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reg:
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maxItems: 5
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reg-names:
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items:
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- const: scu
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- const: adg
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- const: ssiu
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- const: ssi
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- const: audmapp
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"#sound-dai-cells":
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const: 1
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"#clock-cells":
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const: 0
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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clocks:
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maxItems: 47
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clock-names:
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items:
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- const: ssi-all
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- const: ssi-0
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- const: ssi-1
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- const: ssi-2
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- const: ssi-3
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- const: ssi-4
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- const: ssi-5
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- const: ssi-6
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- const: ssi-7
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- const: ssi-8
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- const: ssi-9
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- const: src-0
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- const: src-1
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- const: src-2
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- const: src-3
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- const: src-4
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- const: src-5
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- const: src-6
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- const: src-7
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- const: src-8
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- const: src-9
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- const: mix-0
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- const: mix-1
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- const: ctu-0
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- const: ctu-1
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- const: dvc-0
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- const: dvc-1
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- const: audio-clka
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- const: audio-clkb
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- const: audio-clkc
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- const: audio-clki
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- const: ssif_supply
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- const: scu
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- const: scu_x2
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- const: scu_supply
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- const: adg-ssi-0
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- const: adg-ssi-1
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- const: adg-ssi-2
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- const: adg-ssi-3
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- const: adg-ssi-4
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- const: adg-ssi-5
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- const: adg-ssi-6
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- const: adg-ssi-7
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- const: adg-ssi-8
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- const: adg-ssi-9
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- const: audmapp
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- const: adg
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power-domains:
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maxItems: 1
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resets:
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maxItems: 14
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reset-names:
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items:
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- const: ssi-all
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- const: ssi-0
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- const: ssi-1
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- const: ssi-2
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- const: ssi-3
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- const: ssi-4
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- const: ssi-5
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- const: ssi-6
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- const: ssi-7
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- const: ssi-8
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- const: ssi-9
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- const: scu
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- const: adg
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- const: audmapp
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dvc:
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type: object
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additionalProperties: false
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patternProperties:
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"^dvc-[0-1]$":
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type: object
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additionalProperties: false
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properties:
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dmas:
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maxItems: 5
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description:
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List of references to DMA specifiers, one per DMA
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controller, all for the transmission direction
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(DVC is playback-only). The dma-engine core falls
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through the list to find a free channel.
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dma-names:
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maxItems: 5
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allOf:
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- items:
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enum:
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- tx
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required:
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- dmas
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- dma-names
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mix:
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type: object
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additionalProperties: false
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description:
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Per-channel Mixer (MIX) sub-nodes. Each mix-N node has no
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properties of its own. It exists so the driver can enumerate
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the MIX instances and so that DT labels can be attached to it
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for the dai/playback/capture phandle routing arrays.
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patternProperties:
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"^mix-[0-1]$":
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type: object
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additionalProperties: false
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ctu:
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type: object
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additionalProperties: false
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description:
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Per-channel Channel Transfer Unit (CTU) sub-nodes. Each ctu-N
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node has no properties of its own. It exists so the driver
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can enumerate the CTU instances and so that DT labels can be
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attached to it for the dai/playback/capture phandle routing arrays.
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patternProperties:
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"^ctu-[0-7]$":
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type: object
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additionalProperties: false
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src:
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type: object
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additionalProperties: false
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patternProperties:
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"^src-[0-9]$":
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type: object
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additionalProperties: false
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properties:
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interrupts:
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maxItems: 1
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dmas:
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maxItems: 10
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description:
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Must contain a list of pairs of references to DMA
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specifiers, one for transmission and one for reception,
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repeated for each DMA controller. The dma-engine core
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falls through the list to find a free channel.
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dma-names:
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maxItems: 10
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allOf:
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- items:
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enum:
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- tx
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- rx
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ssiu:
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type: object
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additionalProperties: false
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patternProperties:
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"^ssiu-[0-9]+$":
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type: object
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additionalProperties: false
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properties:
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dmas:
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maxItems: 10
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description:
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Must contain a list of pairs of references to DMA
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specifiers, one for transmission and one for reception,
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repeated for each DMA controller. The dma-engine core
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falls through the list to find a free channel.
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dma-names:
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maxItems: 10
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allOf:
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- items:
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enum:
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- tx
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- rx
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required:
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- dmas
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- dma-names
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ssi:
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type: object
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additionalProperties: false
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patternProperties:
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"^ssi-[0-9]$":
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type: object
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additionalProperties: false
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properties:
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interrupts:
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maxItems: 1
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shared-pin:
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description: Shared clock pin.
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$ref: /schemas/types.yaml#/definitions/flag
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required:
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- interrupts
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ports:
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$ref: audio-graph-port.yaml#/definitions/port-base
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unevaluatedProperties: false
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patternProperties:
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'^port@[0-9a-f]+$':
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$ref: audio-graph-port.yaml#/definitions/port-base
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unevaluatedProperties: false
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properties:
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reg:
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maxItems: 1
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endpoint:
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$ref: audio-graph-port.yaml#/definitions/endpoint-base
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unevaluatedProperties: false
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properties:
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playback:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description:
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Ordered list of phandles to the in-SoC modules used
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by this DAI in the playback direction. Each phandle
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must reference one of the ssi-N, src-N, ctu-N,
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mix-N or dvc-N sub-nodes of the parent sound
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controller. The list order is the pipeline order
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from CPU to off-SoC endpoint.
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capture:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description:
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Ordered list of phandles to the in-SoC modules used
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by this DAI in the capture direction. Each phandle
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must reference one of the ssi-N, src-N, ctu-N,
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mix-N or dvc-N sub-nodes of the parent sound
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controller. The list order is the pipeline order
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from off-SoC endpoint to CPU.
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required:
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- compatible
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- reg
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- reg-names
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- "#sound-dai-cells"
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- "#clock-cells"
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- clocks
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- clock-names
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- resets
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- reset-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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sound@13c00000 {
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#sound-dai-cells = <1>;
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#clock-cells = <0>;
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compatible = "renesas,r9a09g047-sound";
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reg = <0x13c00000 0x10000>,
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<0x13c20000 0x10000>,
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<0x13c30000 0x1000>,
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<0x13c31000 0x1f000>,
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<0x13c50000 0x10000>;
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reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
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clocks = <&cpg 245>,
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<&cpg 385>, <&cpg 386>,
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<&cpg 387>, <&cpg 388>,
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<&cpg 389>, <&cpg 390>,
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<&cpg 391>, <&cpg 392>,
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<&cpg 393>, <&cpg 394>,
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<&cpg 372>, <&cpg 373>,
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<&cpg 374>, <&cpg 375>,
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<&cpg 376>, <&cpg 377>,
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<&cpg 378>, <&cpg 379>,
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<&cpg 380>, <&cpg 381>,
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<&cpg 370>, <&cpg 371>,
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<&cpg 370>, <&cpg 371>,
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<&cpg 368>, <&cpg 369>,
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<&cpg 251>, <&cpg 252>,
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<&cpg 253>, <&cpg 250>,
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<&cpg 384>,
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<&cpg 246>, <&cpg 247>,
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<&cpg 382>,
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<&cpg 352>, <&cpg 353>,
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<&cpg 354>, <&cpg 355>,
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<&cpg 356>, <&cpg 357>,
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<&cpg 358>, <&cpg 359>,
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<&cpg 360>, <&cpg 361>,
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<&cpg 248>, <&cpg 249>;
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clock-names = "ssi-all",
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"ssi-0", "ssi-1",
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"ssi-2", "ssi-3",
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"ssi-4", "ssi-5",
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"ssi-6", "ssi-7",
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"ssi-8", "ssi-9",
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"src-0", "src-1",
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"src-2", "src-3",
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"src-4", "src-5",
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"src-6", "src-7",
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"src-8", "src-9",
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"mix-0", "mix-1",
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"ctu-0", "ctu-1",
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"dvc-0", "dvc-1",
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"audio-clka", "audio-clkb",
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"audio-clkc", "audio-clki",
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"ssif_supply",
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"scu", "scu_x2",
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"scu_supply",
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"adg-ssi-0", "adg-ssi-1",
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"adg-ssi-2", "adg-ssi-3",
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"adg-ssi-4", "adg-ssi-5",
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"adg-ssi-6", "adg-ssi-7",
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"adg-ssi-8", "adg-ssi-9",
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"audmapp", "adg";
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power-domains = <&cpg>;
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resets = <&cpg 225>,
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<&cpg 226>, <&cpg 227>,
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<&cpg 228>, <&cpg 229>,
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<&cpg 230>, <&cpg 231>,
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<&cpg 232>, <&cpg 233>,
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<&cpg 234>, <&cpg 235>,
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<&cpg 236>, <&cpg 238>, <&cpg 237>;
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reset-names = "ssi-all",
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"ssi-0", "ssi-1",
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"ssi-2", "ssi-3",
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"ssi-4", "ssi-5",
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"ssi-6", "ssi-7",
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"ssi-8", "ssi-9",
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"scu", "adg",
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"audmapp";
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ctu {
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ctu-0 { };
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ctu-1 { };
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ctu-2 { };
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ctu-3 { };
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ctu-4 { };
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ctu-5 { };
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ctu-6 { };
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ctu-7 { };
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};
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dvc {
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dvc0: dvc-0 {
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dmas = <&dmac0 0x1db3>, <&dmac1 0x1db3>,
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<&dmac2 0x1db3>, <&dmac3 0x1db3>,
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<&dmac4 0x1db3>;
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dma-names = "tx", "tx", "tx", "tx", "tx";
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};
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dvc1: dvc-1 {
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dmas = <&dmac0 0x1db4>, <&dmac1 0x1db4>,
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<&dmac2 0x1db4>, <&dmac3 0x1db4>,
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<&dmac4 0x1db4>;
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dma-names = "tx", "tx", "tx", "tx", "tx";
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};
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};
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mix {
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mix-0 { };
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mix-1 { };
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};
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src {
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src0: src-0 {
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interrupts = <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dmac0 0x1d9f>, <&dmac0 0x1da9>,
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<&dmac1 0x1d9f>, <&dmac1 0x1da9>,
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<&dmac2 0x1d9f>, <&dmac2 0x1da9>,
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<&dmac3 0x1d9f>, <&dmac3 0x1da9>,
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<&dmac4 0x1d9f>, <&dmac4 0x1da9>;
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dma-names = "rx", "tx", "rx", "tx", "rx", "tx",
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"rx", "tx", "rx", "tx";
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};
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src1: src-1 {
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interrupts = <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dmac0 0x1da0>, <&dmac0 0x1daa>,
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<&dmac1 0x1da0>, <&dmac1 0x1daa>,
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<&dmac2 0x1da0>, <&dmac2 0x1daa>,
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<&dmac3 0x1da0>, <&dmac3 0x1daa>,
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<&dmac4 0x1da0>, <&dmac4 0x1daa>;
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dma-names = "rx", "tx", "rx", "tx", "rx", "tx",
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"rx", "tx", "rx", "tx";
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};
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src-2 {
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interrupts = <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dmac0 0x1da1>, <&dmac0 0x1dab>,
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<&dmac1 0x1da1>, <&dmac1 0x1dab>,
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<&dmac2 0x1da1>, <&dmac2 0x1dab>,
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<&dmac3 0x1da1>, <&dmac3 0x1dab>,
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<&dmac4 0x1da1>, <&dmac4 0x1dab>;
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dma-names = "rx", "tx", "rx", "tx", "rx", "tx",
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"rx", "tx", "rx", "tx";
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};
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src-3 {
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interrupts = <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dmac0 0x1da2>, <&dmac0 0x1dac>,
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<&dmac1 0x1da2>, <&dmac1 0x1dac>,
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<&dmac2 0x1da2>, <&dmac2 0x1dac>,
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<&dmac3 0x1da2>, <&dmac3 0x1dac>,
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<&dmac4 0x1da2>, <&dmac4 0x1dac>;
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dma-names = "rx", "tx", "rx", "tx", "rx", "tx",
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"rx", "tx", "rx", "tx";
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};
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src-4 {
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interrupts = <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dmac0 0x1da3>, <&dmac0 0x1dad>,
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<&dmac1 0x1da3>, <&dmac1 0x1dad>,
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<&dmac2 0x1da3>, <&dmac2 0x1dad>,
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<&dmac3 0x1da3>, <&dmac3 0x1dad>,
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<&dmac4 0x1da3>, <&dmac4 0x1dad>;
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dma-names = "rx", "tx", "rx", "tx", "rx", "tx",
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"rx", "tx", "rx", "tx";
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};
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src-5 {
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interrupts = <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dmac0 0x1da4>, <&dmac0 0x1dae>,
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<&dmac1 0x1da4>, <&dmac1 0x1dae>,
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<&dmac2 0x1da4>, <&dmac2 0x1dae>,
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<&dmac3 0x1da4>, <&dmac3 0x1dae>,
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<&dmac4 0x1da4>, <&dmac4 0x1dae>;
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dma-names = "rx", "tx", "rx", "tx", "rx", "tx",
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"rx", "tx", "rx", "tx";
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};
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src-6 {
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interrupts = <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dmac0 0x1da5>, <&dmac0 0x1daf>,
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<&dmac1 0x1da5>, <&dmac1 0x1daf>,
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<&dmac2 0x1da5>, <&dmac2 0x1daf>,
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<&dmac3 0x1da5>, <&dmac3 0x1daf>,
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<&dmac4 0x1da5>, <&dmac4 0x1daf>;
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dma-names = "rx", "tx", "rx", "tx", "rx", "tx",
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"rx", "tx", "rx", "tx";
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};
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src-7 {
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interrupts = <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dmac0 0x1da6>, <&dmac0 0x1db0>,
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<&dmac1 0x1da6>, <&dmac1 0x1db0>,
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<&dmac2 0x1da6>, <&dmac2 0x1db0>,
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<&dmac3 0x1da6>, <&dmac3 0x1db0>,
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<&dmac4 0x1da6>, <&dmac4 0x1db0>;
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|
dma-names = "rx", "tx", "rx", "tx", "rx", "tx",
|
|
"rx", "tx", "rx", "tx";
|
|
};
|
|
src-8 {
|
|
interrupts = <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac0 0x1da7>, <&dmac0 0x1db1>,
|
|
<&dmac1 0x1da7>, <&dmac1 0x1db1>,
|
|
<&dmac2 0x1da7>, <&dmac2 0x1db1>,
|
|
<&dmac3 0x1da7>, <&dmac3 0x1db1>,
|
|
<&dmac4 0x1da7>, <&dmac4 0x1db1>;
|
|
dma-names = "rx", "tx", "rx", "tx", "rx", "tx",
|
|
"rx", "tx", "rx", "tx";
|
|
};
|
|
src-9 {
|
|
interrupts = <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac0 0x1da8>, <&dmac0 0x1db2>,
|
|
<&dmac1 0x1da8>, <&dmac1 0x1db2>,
|
|
<&dmac2 0x1da8>, <&dmac2 0x1db2>,
|
|
<&dmac3 0x1da8>, <&dmac3 0x1db2>,
|
|
<&dmac4 0x1da8>, <&dmac4 0x1db2>;
|
|
dma-names = "rx", "tx", "rx", "tx", "rx", "tx",
|
|
"rx", "tx", "rx", "tx";
|
|
};
|
|
};
|
|
|
|
ssi {
|
|
ssi-0 {
|
|
interrupts = <GIC_SPI 889 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
ssi-1 {
|
|
interrupts = <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
ssi-2 {
|
|
interrupts = <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
ssi3: ssi-3 {
|
|
interrupts = <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
ssi4: ssi-4 {
|
|
interrupts = <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>;
|
|
shared-pin;
|
|
};
|
|
ssi-5 {
|
|
interrupts = <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
ssi-6 {
|
|
interrupts = <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
ssi-7 {
|
|
interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
ssi-8 {
|
|
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
ssi-9 {
|
|
interrupts = <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
ssiu {
|
|
ssiu-0 {
|
|
dmas = <&dmac0 0x1d61>, <&dmac0 0x1d62>,
|
|
<&dmac1 0x1d61>, <&dmac1 0x1d62>,
|
|
<&dmac2 0x1d61>, <&dmac2 0x1d62>,
|
|
<&dmac3 0x1d61>, <&dmac3 0x1d62>,
|
|
<&dmac4 0x1d61>, <&dmac4 0x1d62>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-1 {
|
|
dmas = <&dmac0 0x1d63>, <&dmac0 0x1d64>,
|
|
<&dmac1 0x1d63>, <&dmac1 0x1d64>,
|
|
<&dmac2 0x1d63>, <&dmac2 0x1d64>,
|
|
<&dmac3 0x1d63>, <&dmac3 0x1d64>,
|
|
<&dmac4 0x1d63>, <&dmac4 0x1d64>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-2 {
|
|
dmas = <&dmac0 0x1d65>, <&dmac0 0x1d66>,
|
|
<&dmac1 0x1d65>, <&dmac1 0x1d66>,
|
|
<&dmac2 0x1d65>, <&dmac2 0x1d66>,
|
|
<&dmac3 0x1d65>, <&dmac3 0x1d66>,
|
|
<&dmac4 0x1d65>, <&dmac4 0x1d66>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-3 {
|
|
dmas = <&dmac0 0x1d67>, <&dmac0 0x1d68>,
|
|
<&dmac1 0x1d67>, <&dmac1 0x1d68>,
|
|
<&dmac2 0x1d67>, <&dmac2 0x1d68>,
|
|
<&dmac3 0x1d67>, <&dmac3 0x1d68>,
|
|
<&dmac4 0x1d67>, <&dmac4 0x1d68>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-4 {
|
|
dmas = <&dmac0 0x1d69>, <&dmac0 0x1d6a>,
|
|
<&dmac1 0x1d69>, <&dmac1 0x1d6a>,
|
|
<&dmac2 0x1d69>, <&dmac2 0x1d6a>,
|
|
<&dmac3 0x1d69>, <&dmac3 0x1d6a>,
|
|
<&dmac4 0x1d69>, <&dmac4 0x1d6a>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-5 {
|
|
dmas = <&dmac0 0x1d6b>, <&dmac0 0x1d6c>,
|
|
<&dmac1 0x1d6b>, <&dmac1 0x1d6c>,
|
|
<&dmac2 0x1d6b>, <&dmac2 0x1d6c>,
|
|
<&dmac3 0x1d6b>, <&dmac3 0x1d6c>,
|
|
<&dmac4 0x1d6b>, <&dmac4 0x1d6c>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-6 {
|
|
dmas = <&dmac0 0x1d6d>, <&dmac0 0x1d6e>,
|
|
<&dmac1 0x1d6d>, <&dmac1 0x1d6e>,
|
|
<&dmac2 0x1d6d>, <&dmac2 0x1d6e>,
|
|
<&dmac3 0x1d6d>, <&dmac3 0x1d6e>,
|
|
<&dmac4 0x1d6d>, <&dmac4 0x1d6e>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-7 {
|
|
dmas = <&dmac0 0x1d6f>, <&dmac0 0x1d70>,
|
|
<&dmac1 0x1d6f>, <&dmac1 0x1d70>,
|
|
<&dmac2 0x1d6f>, <&dmac2 0x1d70>,
|
|
<&dmac3 0x1d6f>, <&dmac3 0x1d70>,
|
|
<&dmac4 0x1d6f>, <&dmac4 0x1d70>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-8 {
|
|
dmas = <&dmac0 0x1d71>, <&dmac0 0x1d72>,
|
|
<&dmac1 0x1d71>, <&dmac1 0x1d72>,
|
|
<&dmac2 0x1d71>, <&dmac2 0x1d72>,
|
|
<&dmac3 0x1d71>, <&dmac3 0x1d72>,
|
|
<&dmac4 0x1d71>, <&dmac4 0x1d72>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-9 {
|
|
dmas = <&dmac0 0x1d73>, <&dmac0 0x1d74>,
|
|
<&dmac1 0x1d73>, <&dmac1 0x1d74>,
|
|
<&dmac2 0x1d73>, <&dmac2 0x1d74>,
|
|
<&dmac3 0x1d73>, <&dmac3 0x1d74>,
|
|
<&dmac4 0x1d73>, <&dmac4 0x1d74>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-10 {
|
|
dmas = <&dmac0 0x1d75>, <&dmac0 0x1d76>,
|
|
<&dmac1 0x1d75>, <&dmac1 0x1d76>,
|
|
<&dmac2 0x1d75>, <&dmac2 0x1d76>,
|
|
<&dmac3 0x1d75>, <&dmac3 0x1d76>,
|
|
<&dmac4 0x1d75>, <&dmac4 0x1d76>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-11 {
|
|
dmas = <&dmac0 0x1d77>, <&dmac0 0x1d78>,
|
|
<&dmac1 0x1d77>, <&dmac1 0x1d78>,
|
|
<&dmac2 0x1d77>, <&dmac2 0x1d78>,
|
|
<&dmac3 0x1d77>, <&dmac3 0x1d78>,
|
|
<&dmac4 0x1d77>, <&dmac4 0x1d78>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-12 {
|
|
dmas = <&dmac0 0x1d79>, <&dmac0 0x1d7a>,
|
|
<&dmac1 0x1d79>, <&dmac1 0x1d7a>,
|
|
<&dmac2 0x1d79>, <&dmac2 0x1d7a>,
|
|
<&dmac3 0x1d79>, <&dmac3 0x1d7a>,
|
|
<&dmac4 0x1d79>, <&dmac4 0x1d7a>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-13 {
|
|
dmas = <&dmac0 0x1d7b>, <&dmac0 0x1d7c>,
|
|
<&dmac1 0x1d7b>, <&dmac1 0x1d7c>,
|
|
<&dmac2 0x1d7b>, <&dmac2 0x1d7c>,
|
|
<&dmac3 0x1d7b>, <&dmac3 0x1d7c>,
|
|
<&dmac4 0x1d7b>, <&dmac4 0x1d7c>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-14 {
|
|
dmas = <&dmac0 0x1d7d>, <&dmac0 0x1d7e>,
|
|
<&dmac1 0x1d7d>, <&dmac1 0x1d7e>,
|
|
<&dmac2 0x1d7d>, <&dmac2 0x1d7e>,
|
|
<&dmac3 0x1d7d>, <&dmac3 0x1d7e>,
|
|
<&dmac4 0x1d7d>, <&dmac4 0x1d7e>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-15 {
|
|
dmas = <&dmac0 0x1d7f>, <&dmac0 0x1d80>,
|
|
<&dmac1 0x1d7f>, <&dmac1 0x1d80>,
|
|
<&dmac2 0x1d7f>, <&dmac2 0x1d80>,
|
|
<&dmac3 0x1d7f>, <&dmac3 0x1d80>,
|
|
<&dmac4 0x1d7f>, <&dmac4 0x1d80>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-16 {
|
|
dmas = <&dmac0 0x1d81>, <&dmac0 0x1d82>,
|
|
<&dmac1 0x1d81>, <&dmac1 0x1d82>,
|
|
<&dmac2 0x1d81>, <&dmac2 0x1d82>,
|
|
<&dmac3 0x1d81>, <&dmac3 0x1d82>,
|
|
<&dmac4 0x1d81>, <&dmac4 0x1d82>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-17 {
|
|
dmas = <&dmac0 0x1d83>, <&dmac0 0x1d84>,
|
|
<&dmac1 0x1d83>, <&dmac1 0x1d84>,
|
|
<&dmac2 0x1d83>, <&dmac2 0x1d84>,
|
|
<&dmac3 0x1d83>, <&dmac3 0x1d84>,
|
|
<&dmac4 0x1d83>, <&dmac4 0x1d84>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-18 {
|
|
dmas = <&dmac0 0x1d85>, <&dmac0 0x1d86>,
|
|
<&dmac1 0x1d85>, <&dmac1 0x1d86>,
|
|
<&dmac2 0x1d85>, <&dmac2 0x1d86>,
|
|
<&dmac3 0x1d85>, <&dmac3 0x1d86>,
|
|
<&dmac4 0x1d85>, <&dmac4 0x1d86>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-19 {
|
|
dmas = <&dmac0 0x1d87>, <&dmac0 0x1d88>,
|
|
<&dmac1 0x1d87>, <&dmac1 0x1d88>,
|
|
<&dmac2 0x1d87>, <&dmac2 0x1d88>,
|
|
<&dmac3 0x1d87>, <&dmac3 0x1d88>,
|
|
<&dmac4 0x1d87>, <&dmac4 0x1d88>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-20 {
|
|
dmas = <&dmac0 0x1d89>, <&dmac0 0x1d8a>,
|
|
<&dmac1 0x1d89>, <&dmac1 0x1d8a>,
|
|
<&dmac2 0x1d89>, <&dmac2 0x1d8a>,
|
|
<&dmac3 0x1d89>, <&dmac3 0x1d8a>,
|
|
<&dmac4 0x1d89>, <&dmac4 0x1d8a>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-21 {
|
|
dmas = <&dmac0 0x1d8b>, <&dmac0 0x1d8c>,
|
|
<&dmac1 0x1d8b>, <&dmac1 0x1d8c>,
|
|
<&dmac2 0x1d8b>, <&dmac2 0x1d8c>,
|
|
<&dmac3 0x1d8b>, <&dmac3 0x1d8c>,
|
|
<&dmac4 0x1d8b>, <&dmac4 0x1d8c>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-22 {
|
|
dmas = <&dmac0 0x1d8d>, <&dmac0 0x1d8e>,
|
|
<&dmac1 0x1d8d>, <&dmac1 0x1d8e>,
|
|
<&dmac2 0x1d8d>, <&dmac2 0x1d8e>,
|
|
<&dmac3 0x1d8d>, <&dmac3 0x1d8e>,
|
|
<&dmac4 0x1d8d>, <&dmac4 0x1d8e>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-23 {
|
|
dmas = <&dmac0 0x1d8f>, <&dmac0 0x1d90>,
|
|
<&dmac1 0x1d8f>, <&dmac1 0x1d90>,
|
|
<&dmac2 0x1d8f>, <&dmac2 0x1d90>,
|
|
<&dmac3 0x1d8f>, <&dmac3 0x1d90>,
|
|
<&dmac4 0x1d8f>, <&dmac4 0x1d90>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-24 {
|
|
dmas = <&dmac0 0x1d91>, <&dmac0 0x1d92>,
|
|
<&dmac1 0x1d91>, <&dmac1 0x1d92>,
|
|
<&dmac2 0x1d91>, <&dmac2 0x1d92>,
|
|
<&dmac3 0x1d91>, <&dmac3 0x1d92>,
|
|
<&dmac4 0x1d91>, <&dmac4 0x1d92>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-25 {
|
|
dmas = <&dmac0 0x1d93>, <&dmac0 0x1d94>,
|
|
<&dmac1 0x1d93>, <&dmac1 0x1d94>,
|
|
<&dmac2 0x1d93>, <&dmac2 0x1d94>,
|
|
<&dmac3 0x1d93>, <&dmac3 0x1d94>,
|
|
<&dmac4 0x1d93>, <&dmac4 0x1d94>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-26 {
|
|
dmas = <&dmac0 0x1d95>, <&dmac0 0x1d96>,
|
|
<&dmac1 0x1d95>, <&dmac1 0x1d96>,
|
|
<&dmac2 0x1d95>, <&dmac2 0x1d96>,
|
|
<&dmac3 0x1d95>, <&dmac3 0x1d96>,
|
|
<&dmac4 0x1d95>, <&dmac4 0x1d96>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
ssiu-27 {
|
|
dmas = <&dmac0 0x1d97>, <&dmac0 0x1d98>,
|
|
<&dmac1 0x1d97>, <&dmac1 0x1d98>,
|
|
<&dmac2 0x1d97>, <&dmac2 0x1d98>,
|
|
<&dmac3 0x1d97>, <&dmac3 0x1d98>,
|
|
<&dmac4 0x1d97>, <&dmac4 0x1d98>;
|
|
dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx";
|
|
};
|
|
};
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
port@0 {
|
|
reg = <0>;
|
|
rsnd_endpoint0: endpoint {
|
|
remote-endpoint = <&codec_endpoint>;
|
|
dai-format = "i2s";
|
|
bitclock-master = <&rsnd_endpoint0>;
|
|
frame-master = <&rsnd_endpoint0>;
|
|
playback = <&ssi3>, <&src1>, <&dvc1>;
|
|
capture = <&ssi4>, <&src0>, <&dvc0>;
|
|
};
|
|
};
|
|
};
|
|
};
|