80 lines
1.9 KiB
Devicetree
80 lines
1.9 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Ethernet ENET2 support for Variscite VAR-SOM-6UL module.
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*
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* Copyright 2019-2024 Variscite Ltd.
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* Copyright 2026 Dimonoff
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*/
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/ {
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rmii_ref_clk: rmii-ref-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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clock-output-names = "rmii-ref";
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};
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>;
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phy-mode = "rmii";
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phy-handle = <ðphy1>;
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status = "okay";
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mdio_enet2: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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clocks = <&rmii_ref_clk>;
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clock-names = "rmii-ref";
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reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
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reset-assert-us = <100000>;
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micrel,led-mode = <1>;
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micrel,rmii-reference-clock-select-25-mhz;
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};
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ethphy1: ethernet-phy@3 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <3>;
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clocks = <&rmii_ref_clk>;
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clock-names = "rmii-ref";
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reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
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reset-assert-us = <100000>;
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micrel,led-mode = <0>;
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micrel,rmii-reference-clock-select-25-mhz;
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};
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};
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};
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&iomuxc {
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pinctrl_enet2: enet2grp {
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fsl,pins = <
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MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
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MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
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MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
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MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
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MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
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MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
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>;
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};
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pinctrl_enet2_gpio: enet2-gpiogrp {
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fsl,pins = <
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MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* fec2 reset */
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>;
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};
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pinctrl_enet2_mdio: enet2-mdiogrp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
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MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
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>;
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};
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};
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