34 lines
969 B
C
34 lines
969 B
C
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
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/*
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* Copyright 2025 NXP
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*/
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#ifndef __IMX8MP_AIPSTZ_H
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#define __IMX8MP_AIPSTZ_H
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/* consumer type - master or peripheral */
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#define IMX8MP_AIPSTZ_MASTER 0x0
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#define IMX8MP_AIPSTZ_PERIPH 0x1
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/* master configuration options */
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#define IMX8MP_AIPSTZ_MPL (1 << 0)
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#define IMX8MP_AIPSTZ_MTW (1 << 1)
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#define IMX8MP_AIPSTZ_MTR (1 << 2)
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#define IMX8MP_AIPSTZ_MBW (1 << 3)
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/* peripheral configuration options */
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#define IMX8MP_AIPSTZ_TP (1 << 0)
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#define IMX8MP_AIPSTZ_WP (1 << 1)
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#define IMX8MP_AIPSTZ_SP (1 << 2)
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#define IMX8MP_AIPSTZ_BW (1 << 3)
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/* master ID definitions */
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#define IMX8MP_AIPSTZ_EDMA 0 /* AUDIOMIX EDMA */
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#define IMX8MP_AIPSTZ_CA53 1 /* Cortex-A53 cluster */
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#define IMX8MP_AIPSTZ_SDMA2 3 /* AUDIOMIX SDMA2 */
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#define IMX8MP_AIPSTZ_SDMA3 3 /* AUDIOMIX SDMA3 */
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#define IMX8MP_AIPSTZ_HIFI4 5 /* HIFI4 DSP */
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#define IMX8MP_AIPSTZ_CM7 6 /* Cortex-M7 */
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#endif /* __IMX8MP_AIPSTZ_H */
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