186 lines
3.1 KiB
Devicetree
186 lines
3.1 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the Ironhide board
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*
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* Copyright (C) 2025 Renesas Electronics Corp.
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*/
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/dts-v1/;
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#include <dt-bindings/soc/renesas,r8a78000-mfis.h>
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#include "r8a78000.dtsi"
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/ {
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model = "Renesas Ironhide board based on r8a78000";
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compatible = "renesas,ironhide", "renesas,r8a78000";
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aliases {
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serial0 = &hscif0;
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};
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chosen {
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stdout-path = "serial0:1843200n8";
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};
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firmware {
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scmi: scmi {
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compatible = "arm,scmi";
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mboxes = <&mfis_scp 2 MFIS_CHANNEL_TX>,
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<&mfis_scp 2 MFIS_CHANNEL_RX>;
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mbox-names = "tx", "rx";
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shmem = <&scmi_tx_shmem>, <&scmi_rx_shmem>;
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arm,no-completion-irq;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0x0 0x80000000>;
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};
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memory@1080000000 {
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device_type = "memory";
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reg = <0x10 0x80000000 0x0 0x80000000>;
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};
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memory@1200000000 {
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device_type = "memory";
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reg = <0x12 0x00000000 0x1 0x00000000>;
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};
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memory@1400000000 {
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device_type = "memory";
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reg = <0x14 0x00000000 0x1 0x00000000>;
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};
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memory@1600000000 {
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device_type = "memory";
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reg = <0x16 0x00000000 0x1 0x00000000>;
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};
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memory@1800000000 {
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device_type = "memory";
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reg = <0x18 0x00000000 0x1 0x00000000>;
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};
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memory@1a00000000 {
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device_type = "memory";
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reg = <0x1a 0x00000000 0x1 0x00000000>;
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};
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memory@1c00000000 {
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device_type = "memory";
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reg = <0x1c 0x00000000 0x1 0x00000000>;
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};
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memory@1e00000000 {
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device_type = "memory";
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reg = <0x1e 0x00000000 0x1 0x00000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* First 518 MiB is reserved for other purposes. */
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firmware@40000000 {
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reg = <0x0 0x40000000 0x0 0x20600000>;
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no-map;
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};
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/* Parameters set by IPL. */
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parameters@8c100000 {
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reg = <0x0 0x8c100000 0x0 0x00008000>;
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no-map;
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};
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/* TFA BL31. */
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tfa-bl31@8c200000 {
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reg = <0x0 0x8c200000 0x0 0x00080000>;
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no-map;
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};
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/* TEE TZ DRAM. */
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tee@8c400000 {
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reg = <0x0 0x8c400000 0x0 0x02000000>;
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no-map;
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};
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/* DRAM controller inline ECC areas */
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ecc@10cccc0000 {
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reg = <0x10 0xcccc0000 0x0 0x33340000>;
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no-map;
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};
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ecc@12cccc0000 {
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reg = <0x12 0xcccc0000 0x0 0x33340000>;
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no-map;
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};
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ecc@14cccc0000 {
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reg = <0x14 0xcccc0000 0x0 0x33340000>;
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no-map;
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};
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ecc@16cccc0000 {
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reg = <0x16 0xcccc0000 0x0 0x33340000>;
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no-map;
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};
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ecc@18cccc0000 {
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reg = <0x18 0xcccc0000 0x0 0x33340000>;
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no-map;
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};
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ecc@1a66660000 {
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reg = <0x1a 0x66660000 0x0 0x999a0000>;
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no-map;
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};
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ecc@1c66660000 {
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reg = <0x1c 0x66660000 0x0 0x999a0000>;
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no-map;
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};
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ecc@1e66660000 {
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reg = <0x1e 0x66660000 0x0 0x999a0000>;
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no-map;
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};
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};
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};
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&extal_clk {
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clock-frequency = <16666600>;
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};
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&extalr_clk {
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clock-frequency = <32768>;
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};
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&hscif0 {
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uart-has-rtscts;
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status = "okay";
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};
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&mfis_scp {
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status = "okay";
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};
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&scif_clk {
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clock-frequency = <26000000>;
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};
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&stcm_transport {
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scmi_tx_shmem: sram@1200 {
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compatible = "arm,scmi-shmem";
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reg = <0x1200 0x0100>;
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};
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scmi_rx_shmem: sram@1300 {
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compatible = "arm,scmi-shmem";
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reg = <0x1300 0x100>;
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};
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};
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