206 lines
4.1 KiB
C
206 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* mt8196-afe-common.h -- Mediatek 8196 audio driver definitions
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*
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* Copyright (c) 2025 MediaTek Inc.
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* Author: Darren Ye <darren.ye@mediatek.com>
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*/
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#ifndef _MT_8196_AFE_COMMON_H_
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#define _MT_8196_AFE_COMMON_H_
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#include <sound/pcm.h>
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#include <sound/soc.h>
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#include "mt8196-reg.h"
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#include "../common/mtk-base-afe.h"
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/* HW IPM 2.0 */
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enum {
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MTK_AFE_IPM2P0_RATE_8K = 0x0,
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MTK_AFE_IPM2P0_RATE_11K = 0x1,
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MTK_AFE_IPM2P0_RATE_12K = 0x2,
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MTK_AFE_IPM2P0_RATE_16K = 0x4,
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MTK_AFE_IPM2P0_RATE_22K = 0x5,
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MTK_AFE_IPM2P0_RATE_24K = 0x6,
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MTK_AFE_IPM2P0_RATE_32K = 0x8,
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MTK_AFE_IPM2P0_RATE_44K = 0x9,
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MTK_AFE_IPM2P0_RATE_48K = 0xa,
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MTK_AFE_IPM2P0_RATE_88K = 0xd,
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MTK_AFE_IPM2P0_RATE_96K = 0xe,
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MTK_AFE_IPM2P0_RATE_176K = 0x11,
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MTK_AFE_IPM2P0_RATE_192K = 0x12,
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MTK_AFE_IPM2P0_RATE_352K = 0x15,
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MTK_AFE_IPM2P0_RATE_384K = 0x16,
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};
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enum {
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MTKAIF_PROTOCOL_1,
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MTKAIF_PROTOCOL_2,
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MTKAIF_PROTOCOL_2_CLK_P2,
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};
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enum {
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MT8196_MEMIF_DL0,
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MT8196_MEMIF_DL1,
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MT8196_MEMIF_DL2,
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MT8196_MEMIF_DL3,
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MT8196_MEMIF_DL4,
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MT8196_MEMIF_DL5,
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MT8196_MEMIF_DL6,
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MT8196_MEMIF_DL7,
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MT8196_MEMIF_DL8,
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MT8196_MEMIF_DL23,
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MT8196_MEMIF_DL24,
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MT8196_MEMIF_DL25,
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MT8196_MEMIF_DL26,
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MT8196_MEMIF_DL_4CH,
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MT8196_MEMIF_DL_24CH,
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MT8196_MEMIF_VUL0,
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MT8196_MEMIF_VUL1,
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MT8196_MEMIF_VUL2,
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MT8196_MEMIF_VUL3,
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MT8196_MEMIF_VUL4,
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MT8196_MEMIF_VUL5,
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MT8196_MEMIF_VUL6,
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MT8196_MEMIF_VUL7,
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MT8196_MEMIF_VUL8,
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MT8196_MEMIF_VUL9,
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MT8196_MEMIF_VUL10,
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MT8196_MEMIF_VUL24,
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MT8196_MEMIF_VUL25,
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MT8196_MEMIF_VUL26,
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MT8196_MEMIF_VUL_CM0,
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MT8196_MEMIF_VUL_CM1,
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MT8196_MEMIF_VUL_CM2,
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MT8196_MEMIF_ETDM_IN0,
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MT8196_MEMIF_ETDM_IN1,
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MT8196_MEMIF_ETDM_IN2,
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MT8196_MEMIF_ETDM_IN3,
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MT8196_MEMIF_ETDM_IN4,
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MT8196_MEMIF_ETDM_IN6,
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MT8196_MEMIF_HDMI,
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MT8196_MEMIF_NUM,
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MT8196_DAI_ADDA = MT8196_MEMIF_NUM,
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MT8196_DAI_ADDA_CH34,
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MT8196_DAI_ADDA_CH56,
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MT8196_DAI_AP_DMIC,
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MT8196_DAI_AP_DMIC_CH34,
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MT8196_DAI_AP_DMIC_MULTICH,
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MT8196_DAI_I2S_IN0,
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MT8196_DAI_I2S_IN1,
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MT8196_DAI_I2S_IN2,
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MT8196_DAI_I2S_IN3,
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MT8196_DAI_I2S_IN4,
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MT8196_DAI_I2S_IN6,
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MT8196_DAI_I2S_OUT0,
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MT8196_DAI_I2S_OUT1,
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MT8196_DAI_I2S_OUT2,
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MT8196_DAI_I2S_OUT3,
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MT8196_DAI_I2S_OUT4,
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MT8196_DAI_I2S_OUT6,
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MT8196_DAI_FM_I2S_MASTER,
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MT8196_DAI_TDM,
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MT8196_DAI_TDM_DPTX,
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MT8196_DAI_NUM,
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};
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#define MT8196_DAI_I2S_MAX_NUM 13 //depends each platform's max i2s num
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/* update irq ID (= enum) from AFE_IRQ_MCU_STATUS */
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enum {
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MT8196_IRQ_0,
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MT8196_IRQ_1,
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MT8196_IRQ_2,
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MT8196_IRQ_3,
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MT8196_IRQ_4,
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MT8196_IRQ_5,
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MT8196_IRQ_6,
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MT8196_IRQ_7,
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MT8196_IRQ_8,
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MT8196_IRQ_9,
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MT8196_IRQ_10,
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MT8196_IRQ_11,
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MT8196_IRQ_12,
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MT8196_IRQ_13,
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MT8196_IRQ_14,
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MT8196_IRQ_15,
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MT8196_IRQ_16,
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MT8196_IRQ_17,
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MT8196_IRQ_18,
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MT8196_IRQ_19,
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MT8196_IRQ_20,
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MT8196_IRQ_21,
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MT8196_IRQ_22,
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MT8196_IRQ_23,
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MT8196_IRQ_24,
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MT8196_IRQ_25,
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MT8196_IRQ_26,
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MT8196_IRQ_31, /* used only for TDM */
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MT8196_IRQ_NUM,
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};
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/* update irq ID (= enum) from AFE_IRQ_MCU_STATUS */
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enum {
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MT8196_CUS_IRQ_TDM, /* used only for TDM */
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MT8196_CUS_IRQ_NUM,
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};
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enum {
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/* AUDIO_ENGEN_CON0 */
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MT8196_AUDIO_26M_EN_ON,
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MT8196_AUDIO_F3P25M_EN_ON,
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MT8196_AUDIO_APLL1_EN_ON,
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MT8196_AUDIO_APLL2_EN_ON,
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MT8196_AUDIO_F26M_EN_RST,
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MT8196_MULTI_USER_RST,
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MT8196_MULTI_USER_BYPASS,
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/* AUDIO_TOP_CON4 */
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MT8196_CG_AUDIO_HOPPING_CK,
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MT8196_CG_AUDIO_F26M_CK,
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MT8196_CG_APLL1_CK,
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MT8196_CG_APLL2_CK,
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MT8196_PDN_APLL_TUNER2,
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MT8196_PDN_APLL_TUNER1,
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MT8196_AUDIO_CG_NUM,
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};
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/* MCLK */
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enum {
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MT8196_I2SIN0_MCK,
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MT8196_I2SIN1_MCK,
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MT8196_FMI2S_MCK,
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MT8196_TDMOUT_MCK,
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MT8196_TDMOUT_BCK,
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MT8196_MCK_NUM,
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};
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/* CM*/
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enum {
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CM0,
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CM1,
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CM2,
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CM_NUM,
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};
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struct clk;
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struct mtk_base_afe;
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struct mt8196_afe_private {
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struct clk **clk;
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/* dai */
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void *dai_priv[MT8196_DAI_NUM];
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/* mck */
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int mck_rate[MT8196_MCK_NUM];
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/* channel merge */
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u32 cm_rate[CM_NUM];
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u32 cm_channels;
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};
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int mt8196_dai_adda_register(struct mtk_base_afe *afe);
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int mt8196_dai_i2s_register(struct mtk_base_afe *afe);
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int mt8196_dai_tdm_register(struct mtk_base_afe *afe);
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int mt8196_dai_set_priv(struct mtk_base_afe *afe, int id,
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int priv_size, const void *priv_data);
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#endif
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