394 lines
9.6 KiB
Devicetree
394 lines
9.6 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2025 Josua Mayer <josua@solid-run.com>
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*/
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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#include "imx8mm.dtsi"
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/ {
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compatible = "solidrun,imx8mm-sr-som", "fsl,imx8mm";
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model = "SolidRun i.MX8MM SoM";
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chosen {
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bootargs = "earlycon=ec_imx6q,0x30890000,115200";
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stdout-path = &uart2;
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};
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v_1_8: regulator-1-8 {
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compatible = "regulator-fixed";
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regulator-name = "1v8";
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regulator-max-microvolt = <1800000>;
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regulator-min-microvolt = <1800000>;
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};
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v_3_3: regulator-3-3 {
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compatible = "regulator-fixed";
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regulator-name = "3v3";
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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};
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usdhc1_pwrseq: usdhc1-pwrseq {
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compatible = "mmc-pwrseq-simple";
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reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
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};
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memory@40000000 {
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reg = <0x0 0x40000000 0 0x80000000>;
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device_type = "memory";
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};
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};
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&fec1 {
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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pinctrl-0 = <&fec1_pins>;
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pinctrl-names = "default";
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0x4>;
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phy-reset-duration = <10>;
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reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
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vddio-supply = <&vddio>;
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qca,smarteee-tw-us-1g = <24>;
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vddio: vddio-regulator {
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regulator-max-microvolt = <1800000>;
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regulator-min-microvolt = <1800000>;
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};
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};
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};
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};
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-names = "default";
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status = "okay";
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pmic@4b {
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compatible = "rohm,bd71847";
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reg = <0x4b>;
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interrupt-parent = <&gpio1>;
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interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&osc_32k>;
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#clock-cells = <0>;
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clock-output-names = "clk-32k-out";
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pinctrl-0 = <&pmic_pins>;
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pinctrl-names = "default";
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rohm,reset-snvs-powered;
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regulators {
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buck1_reg: BUCK1 {
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regulator-name = "buck1";
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1300000>;
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regulator-min-microvolt = <700000>;
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regulator-ramp-delay = <1250>;
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};
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buck2_reg: BUCK2 {
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regulator-name = "buck2";
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1300000>;
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regulator-min-microvolt = <700000>;
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regulator-ramp-delay = <1250>;
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rohm,dvs-idle-voltage = <900000>;
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rohm,dvs-run-voltage = <1000000>;
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};
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buck3_reg: BUCK3 {
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// BUCK5 in datasheet
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regulator-name = "buck3";
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1350000>;
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regulator-min-microvolt = <700000>;
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};
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buck4_reg: BUCK4 {
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// BUCK6 in datasheet
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regulator-name = "buck4";
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3000000>;
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};
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buck5_reg: BUCK5 {
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// BUCK7 in datasheet
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regulator-name = "buck5";
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1995000>;
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regulator-min-microvolt = <1605000>;
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};
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buck6_reg: BUCK6 {
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// BUCK8 in datasheet
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regulator-name = "buck6";
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1400000>;
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regulator-min-microvolt = <800000>;
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};
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ldo1_reg: LDO1 {
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regulator-name = "ldo1";
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <1600000>;
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};
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ldo2_reg: LDO2 {
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regulator-name = "ldo2";
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <900000>;
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regulator-min-microvolt = <800000>;
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};
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ldo3_reg: LDO3 {
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regulator-name = "ldo3";
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <1800000>;
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};
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ldo4_reg: LDO4 {
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regulator-name = "ldo4";
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1800000>;
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regulator-min-microvolt = <900000>;
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};
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ldo6_reg: LDO6 {
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regulator-name = "ldo6";
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1800000>;
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regulator-min-microvolt = <900000>;
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};
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};
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};
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som_eeprom: eeprom@50 {
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compatible = "st,24c01", "atmel,24c01";
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reg = <0x50>;
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pagesize = <16>;
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};
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};
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&iomuxc {
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fec1_pins: pinctrl-fec1-grp {
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fsl,pins = <
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MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
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MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
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MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
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MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
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MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
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MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
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MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
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MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
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MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
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MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
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MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
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MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
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MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
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MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
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MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
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>;
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};
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i2c1_pins: pinctrl-i2c1-grp {
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fsl,pins = <
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MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
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MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
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>;
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};
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pcie_pins: pinctrl-pcie-grp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x0
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>;
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};
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pmic_pins: pinctrl-pmic-grp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140
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>;
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};
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uart1_pins: pinctrl-uart1-grp {
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fsl,pins = <
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MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
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MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
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MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
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MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
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/* BT_REG_ON */
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MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0
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/* BT_WAKE_DEV */
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MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0
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/* BT_WAKE_HOST */
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MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x100
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>;
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};
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uart2_pins: pinctrl-uart2-grp {
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fsl,pins = <
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MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
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MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
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>;
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};
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usdhc1_pins: pinctrl-usdhc1-grp {
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fsl,pins = <
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MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
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MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
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MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
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MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
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MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
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MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
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/* wifi refclk */
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MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x0
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/* WL_REG_ON */
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MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0
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/* WL_WAKE_HOST */
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MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x100
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>;
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};
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usdhc3_100mhz_pins: pinctrl-usdhc3-100mhz-grp {
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fsl,pins = <
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MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
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MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
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MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
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MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
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MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
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MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
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MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
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MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
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MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
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MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
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MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
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>;
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};
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usdhc3_200mhz_pins: pinctrl-usdhc3-200mhz-grp {
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fsl,pins = <
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MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
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MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
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MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
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MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
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MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
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MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
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MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
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MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
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MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
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MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
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MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
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>;
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};
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usdhc3_pins: pinctrl-usdhc3-grp {
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fsl,pins = <
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MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
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MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
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MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
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MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
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MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
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MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
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MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
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MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
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MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
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MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
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MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
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>;
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};
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wdog1_pins: pinctrl-wdog1-grp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x140
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>;
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};
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};
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/* assembly-option for AI accelerator on SoM, otherwise routed to carrier */
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&pcie0 {
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pinctrl-0 = <&pcie_pins>;
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pinctrl-names = "default";
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reset-gpios = <&gpio1 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
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status = "okay";
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};
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&pcie_phy {
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fsl,clkreq-unsupported;
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fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
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status = "okay";
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};
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&uart1 {
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/* select 80MHz parent clock to support maximum baudrate 4Mbps */
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
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assigned-clocks = <&clk IMX8MM_CLK_UART1>;
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pinctrl-0 = <&uart1_pins>;
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pinctrl-names = "default";
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uart-has-rtscts;
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status = "okay";
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bluetooth {
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compatible = "brcm,bcm4330-bt";
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device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
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host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
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max-speed = <3000000>;
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shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
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};
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};
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&uart2 {
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pinctrl-0 = <&uart2_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&usdhc1 {
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bus-width = <4>;
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mmc-pwrseq = <&usdhc1_pwrseq>;
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pinctrl-0 = <&usdhc1_pins>;
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pinctrl-names = "default";
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vmmc-supply = <&v_3_3>;
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vqmmc-supply = <&v_1_8>;
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status = "okay";
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};
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&usdhc3 {
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bus-width = <8>;
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non-removable;
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pinctrl-0 = <&usdhc3_pins>;
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pinctrl-1 = <&usdhc3_100mhz_pins>;
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pinctrl-2 = <&usdhc3_200mhz_pins>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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vmmc-supply = <&v_3_3>;
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vqmmc-supply = <&v_1_8>;
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status = "okay";
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};
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&wdog1 {
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pinctrl-0 = <&wdog1_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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